EPOX P55-TH Manual de usuario

TRADEMARK

All products and company names are

trademarks or registered trademarks of

their respective holders.

with Onboard PCI IDE and Super Multi-I/O.

P55-TH

ISA PCI

MotherBoard

The specification is subject to change without notice.

82430HX PCIset

Contents

page

Chapter 1 - Introduction ................................................ 1-1

P55-TH Board Layout ..............................................................1-2

Chapter 2 - Hardware Design......................................... 2-1

Motherboard Layout .............................................................2-1

Connectors and Jumpers.......................................................2-2

System Memory configuration ..............................................2-4

Cache Memory configuration ...............................................2-6

Integrated PCI Bridge...........................................................2-8

Chapter 3 - Award BIOS ................................................ 3-1

Standard CMOS Setup .........................................................3-2

BIOS Features Setup ............................................................3-2

Chipset Features Setup .........................................................3-6

Power Management Setup ....................................................3-8

PNP/PCI Configuration Setup ..............................................3-10

Integated Peripherals ............................................................3-14

Load Setup Defaults .............................................................3-12

Change password .................................................................3-15

IDE HDD Auto Detection.....................................................3-16

HDD Low Level Format .......................................................3-18

Save & Exit Setup ............................................................... 3-18

Exit Without Saving .............................................................3-18

Chapter 4-Onboard Technical Information...................4-1

I/O & Memory Map..............................................................4-1

Time & DMA Channels Map ...............................................4-2

Interrupt Map .......................................................................4-2

RTC & CMOS RAM Map ....................................................4-3

Appendix A: Post Codes.......................................................4-4

Appendix B: I/O Connector..................................................4-8

Introduction 1-1

Chapter 1

Introduction

The P55-TH motherboard is a high performance system hardware

based on Intel Pentium processor and is equipped with four PCI slots, four

standard ISA slots, Super Multi-I/O controller and dual ports PCI-IDE

connectors for the future expansion. The hardware dimension is 220mm x

280mm with four layer design technology.

Specification

Intel Pentium Processor operating at50/75, 60/90, 66/100, 60/120, 66/

133, 60/150, 66/166 MHz and P54C/P54CTB/P55C with 321 ZIF

socket 7 and scalability to accept faster Pentium Processors in the feature.

Supports up to 512 MegaBytes DRAM(minimum of 8 MB) on board(72

Pins SIMM x 4), and BIOS auto DRAM/EDO RAM configuration.(Refer

to Chapter 2-3 System Memory Configuration)

Supports both Fast Page DRAM or EDO DRAM SIMM. Optional DRAM

Parity or Error Checking and Correction (ECC) with 72-bit Wide memory.

Intel 82430HX PCIset chipset.

Supports Onboard Pipelined burst synchronous and the COAST(v2.0) or

later Version solusion L2 Write Back Cache. The cache memory

combination could be 256KB/512KB (32KB*32 or 64KB*32 SRAM

respectively).

Support four 16 bits ISA slots, four 32 bits PCI slots, and provides two

independent high performance PCI IDE interface capable of supporting

PIO Mode 3 and Mode 4 devices. The P55-TH supports four PCI Bus

Masters and a jumperless PCI INT# control scheme which reduces

configuration confusion when plug in PCI I/O controller card(s).

Supports ATAPI (e.g.CD-ROM) devices on both IDE interface.

Supports 1 floppy port(up to 2.88 MB), 1 parallel port (EPP,ECP port), and

2 serial port (16550 Fast UART compatible).

Supports a PS/2 style mouse and standard AT style keyboard connectors.

Support Award Plug & Play BIOS . The BIOS is stored in Flash EPROM

form. It provides better upgradeability for the system.

Supports CPU Hardware sleep and SMM (System Management Mode).

P55-TH utilizes Lithium battery which provides environmental protection

and longer life time.

1-2 P55-TH

Keyboard BIOS

PCI#1

PCI#3

M 4

M 3

M 2

M 1

1 2 1 2

PRINTER

FDD CONN.

Figure 1-1

Socket 7

SRAM Module

IDE 2 CONN.

IDE 1 CONN.

39 40

Power Conn.

1 1

181

160 80

BANK1

TAG SRAM (U20)

+12V

GND

BIOS

COM1

P55-TH Layout

K/B

CONN.

U31 U30

82438

BANK0

PCI#2

JP5

+JP12

G-LEDRESET SLEEPKEYLOCK

TB-LED J2 J3 J6

J1 +

J44

TXC

J25

COM2

CPU FAN.

PCI#4

SMC

37C669

PIIX3

82371

intel

32K*32

JP14

RTC

JP8 JP6 +

JP11

JP10

J10

1 14

13 26

JP1

32K*32

JP3

J24

SPKR.

J33JP15

J13 J14

J11

J15

Hardware Design 2-1

Chapter 2

Hardware design

2-1 Motherboard Layout

The P55-TH is designed with Intel 82430HX PCIset chipset which is developed

by INTEL Corporation to fully support Intel Pentium processor PCI/ISA system.

The Intel 82430HX PCIset chipset prpovides increased integration and improved

performance designs. The 82430HX chipset provides an integrated IDE controller

with two high performance IDE interfaces for up to four IDE devices (hard devices,

CD-ROM device, etc). The SMC (STANDARD MICROSYSTEMS CORPORA-

TION) FDC37C669 Super I/O controller provides the standard PC I/O function:

floppy interface (up to 2.88 MB), two 16 Byte FIFO serial ports and EPP/ECP

capable parallel port. The P55-TH layout is shown in previous page (left page) for

user's reference. Care must be taken when inserting memory modules, inserting

Intel P54C/P54CT/P54CSTprocessor, or even plugging PCI card into associated

slots to avoid damaging any circuits or sockets on board. A cooling fan is strongly

recommended when installing P54C/P54CT/P54CST processor due to possible

overheat.

The P55-TH supports minimum of 8MB of System Memory and maximum of

512MB while L2 Cache can be 256KB/512KB synchronous SRAM Onboard with

the COASt 2.0 or later Version"Cache-On-A-STick" solution to increase system

performance.( refer to Page 2-5 Cache Memory Configuration for the details.)

The P55-TH support standard Fast Page or EDO (Extended Data Out or Hyper

Page Mode) DRAM. The EDO DRAM is designed to improve the DRAM read

performance (When L2 Cache is installed). The P55-TH provides four 72-pins

SIMM sites for memory expansion. The socket support 1M x 32(4MB), 2M x

32(8MB), 4M x 32(16MB), 8M x 32(32MB) and 16MB x 32(64MB) single-sided

or double-sided SIMM modules. The memory timing requires 70 nS Fast page

devices or 60 nS EDO DRAM. Memory parity generation and checking or ECC

(Error Checking and Correction) are supported. (DRAM Modules may be parity[x

72] or non-parity[x 64] or ECC[x72]. The BIOS will automaticlly detct which

DRAM has installed in SIMM sites.

The P55-TH supports Onboard two PCI IDE connectors, and detects IDE

harddisk type by BIOS utility automatic.

The P55-TH supports Award Plug & Play BIOS for the ISA and PCI cards. The

BIOS can be located in Flash EPROM. The advantage of having Flash EPROM is

much easier to replace BIOS code if necessary.

2-2 P55-TH

1.Power LED(+)

2.N/C

3.GND

4.Keylock

5.GND

JP5 IDE LED indicator - LED ON when Onboard PCI IDE

Harddisks activites.

2-2 Connectors and Jumpers

This section describes all of the connectors and jumpers equipped in the

motherboard. Please refer to Figure 1-1 for actual location of each connector and

jumper.

J1 KeyLock - Keyboard lock switch & Power LED connector.

J2 Speaker - connect to the system's speaker for beeping.

1. Speaker

2. N/C

3. GND

4. GND

J3 Reset - Close to restart system.

J44 Turbo LED indicator - LED ON when higher speed is

selected by a BIOS hot key<CTRL><ALT><+>and also brings

system to a slower speed while a hot key<CTRL><ALT><->.

J6 Power Saving LED indicator(Green-LED) LED ON when

system is in any Saving mode.

J7 1 2 The Power supply of the CPU cooling fan

1,2 GND

3,4+12v

5 6 5,6 GND

3 4

Hardware Design 2-3

JP14 Sleep/Resume switch : Close to enter sleep mode.

A keystrobe or mouse movement (the mouse driver exists). The

systemwill instantly "wake up".

J24 Onboard SMC's chip select :

Open: Normal operation.(Default)

Close: Disable the Onboard SMC chip.

JP15 Keyboard Operation Clock Select :

1-2 The clock rate is depend on the system AT

CLOCK(J25).(Default)

2-3 The clock rate is 12MHz.

JP6 EPROM BIOS Select :

1-2 for 5V Flash EPROM.

2-3 for 12V Flash EPROM.

Note: The JP6 setting is depand on which EPROM type was

attach board.

JP8 BIOS FLASH MODE:

1-2 for normal flash mode. (Default)

2-3 for 12V Flash EPROM to do BOOT BLOCK Flash Mode.

J10 PS/2 MOUSE CONNECTOR:

1.RED wire

2.BLUE wire

3.GREEN wire

4.NC

J33 IrDA/ASK IR CONNECTOR:

1.VCC

2.NC

3.IRRX

4.GND

5.IRTX

1 2 3

J25 System AT BUS CLOCK Select:

1-2 ATCLK is devided PCICLK* by 3.

2-3 ATCLK is devided PCICLK* by 4.(Default)

* PCICLK = System Clock / 2

If system is operating at 66/100 MHz, than PCICLK is 33MHz.

1 2 3

2-4 P55-TH

JP1:CPU Clock Rate Select.

JP3 CPU Install:

1-2:for Intel Pentium Processor (P54C/P54CS/

P54CT/P54CTB) and Cyrix 6x86(Note)

2-3:Intel Pentium Processor P55C.

1 14

13 26

3-16 66/100MHz (Default)

4-17 60/120MHz 6x86-P150+(120MHz)

5-18 66/133MHz 6x86-P166+(133MHz)

6-19 60/150MHz

7-20 66/166MHz

8-21 60/180MHz

9-22 66/200MHz

10-23 6x86-P120+(100MHz)

11-24

12-25

13-26

1-14 50/75MHz

2-15 60/90MHz

Pentium Processor Cyrix 6x86 Processor

BANK1 Single Side DRAM

BANK2,3 Dual Side DRAM

BANK0 Single Side DRAM

BANK0,1 Dual Side DRAM

2-3 System Memory Configuration

The P55-TH supports different type of settings for the system memory. There is no

jumper nor connector needed for memory configuration. Following figures provides

all possible memory cominations.

Note:When Cyrix's CPU installed on board. Please take special care on the CPU

cooling fan to avoid Cyrix CPU overheat problem.

Hardware Design 2-5

M1,M2(BANK 0) M3,M4( BANK 1) Total Size

1M x 32 (4 MB) Empty 8MB

1M x 32 (4 MB) 1M x 32 (4 MB) 16MB

1M x 32 (4 MB) 2M x 32 (8 MB) 24MB

1M x 32 (4 MB) 4M x 32 (16 MB) 40MB

1M x 32 (4 MB) 8M x 32 (32 MB) 72MB

2M x 32 (8 MB) Empty 16MB

2M x 32 (8 MB) 1M x 32 (4 MB) 24MB

2M x 32 (8 MB) 2M x 32 (8 MB) 32MB

2M x 32 (8 MB) 4M x 32 (16 MB) 48MB

2M x 32 (8 MB) 8M x 32 (32 MB) 80MB

4M x 32 (16 MB) Empty 32MB

4M x 32 (16 MB) 1M x 32 (4 MB) 40MB

4M x 32 (16 MB) 2M x 32 (8 MB) 48MB

4M x 32 (16 MB) 4M x 32 (16 MB) 64MB

4M x 32 (16 MB) 8M x 32 (32 MB) 96MB

8M x 32 (32 MB) Empty 64MB

8M x 32 (32 MB) 1M x 32 (4 MB) 72MB

8M x 32 (32 MB) 2M x 32 (8 MB) 80MB

8M x 32 (32 MB) 4M x 32 (16 MB) 96MB

8M x 32 (32 MB) 8M x 32 (32 MB) 128MB

16M x 32 (64MB)-S 16M x 32 (64MB)-S 256MB

16M x 32 (64MB)-D 16M x 32 (64MB)-D 512MB

NOTE : 1. P55-TH support both Fast Page DRAM or EDO

DRAM SIMMs, but they cannot be mixed within

the same memory bank.

2. SIMMs may be parrity (x 72) or non parity (x 64) or

ECC(x 72).

3. The 70nS Fast Page Mode or 60ns EDO DRAM is

necessary.

4. "BANK"=64 Bit=M1, M2 = M3, M4

5. "-S" denotes signal-sided SIMM's, "-D" denotes double-sided

SIMM's.

2-6 P55-TH

2-4 Cache Memory Configuration

The second level (L2) of cache is installed in the motherboard to increase the

system performance. The P55-TH supports different type of combinations for the

cache installation. The COASt 2.0 or later Version(Cache-On-A-STick. The

cache modules has a TAG SRAM.) solution provides Onboard flexibility,

allowing Onboard and modules to accommodate 256KB/512KB piplined burst

synchronous SRAM. Jumper JP10 and JP11 settings is used to Onboard's

synchronous SRAM for differential such combinations. Please refer to following

configurations for the details.

Size (U30,U31) (SRM1) JP10 JP11

SYN.CACHE On Board On Module Jumper Setting

80 1

81160 v

Pipelined burst SRAM Modules( COASt 2.x)

256KB 256KB None 1-2 1-2

256KB None 256KB 1-2 2-3

512KB 256KB 256KB (Extended) 1-2 1-2

512KB 512KB None 2-3 1-2

512KB None 512KB 1-2 2-3

U28

U29

U32

U33

U34

U37

U41

U30 U31

32K*32 32K*32

DATA SRAM

JP10

JP11

U20

TAG SRAM

KEY

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