Cypress Semiconductor CY62148E Manual de usuario

CY62148E MoBL®

4-Mbit (512K x 8) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05442 Rev. *F Revised March 28, 2007

Features

• Very high speed: 45 ns

• Voltage range: 4.5V–5.5V

• Pin compatible with CY62148B

• Ultra low standby power

— Typical standby current: 1 µA

— Maximum standby current: 7 µA (Industrial)

• Ultra low active power

—Typical active current: 2.0 mA @ f = 1 MHz

• Easy memory expansion with CE, and OE features

• Automatic power down when deselected

• CMOS for optimum speed and power

• Available in Pb-free 32-pin TSOP II and 32-pin SOIC [2]

packages

Functional Description [1]

The CY62148E is a high performance CMOS static RAM

organized as 512K words by 8 bits. This device features

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life™ (MoBL®) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption when addresses are not toggling.

Placing the device into standby mode reduces power

consumption by more than 99% when deselected (CE HIGH).

The eight input and output pins (IO0through IO7) are placed

in a high impedance state when:

• Deselected (CE HIGH)

• Outputs are disabled (OE HIGH)

• Write operation is active (CE LOW and WE LOW)

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. Data on the eight IO pins (IO0through IO7)

is then written into the location specified on the address pins

(A0through A18).

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH.

Under these conditions, the contents of the memory location

specified by the address pins appear on the IO pins.

Product Portfolio

Product Range VCC Range (V) Speed

(ns)

Power Dissipation

Operating ICC (mA)

Standby ISB2 ( µA)

f = 1MHz f = fmax

Min Typ [3] Max Typ [3] Max Typ [3] Max Typ [3] Max

CY62148ELL TSOP II Ind’l 4.5 5.0 5.5 45 2 2.5 15 20 1 7

CY62148ELL SOIC Ind’l/Auto-A 4.5 5.0 5.5 55 2 2.5 15 20 1 7

Notes

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

2. SOIC package is available only in 55 ns speed bin.

3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.

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Logic Block Diagram

Pin Configuration [2, 4]

A0IO0

IO7

IO1

IO2

IO3

IO4

IO5

IO6

SENSE AMPS

POWER

DOWN

A13

A14

A15

A16

A17

ROW DECODER

COLUMN DECODER

512K x 8

ARRAY

INPUT BUFFER

A10

A11

A12

A18

Note

4. NC pins are not connected on the die.

32-pin SOIC/TSOP II Pinout

Top View

VSS

VCC

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Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with

Power Applied............................................ –55°C to + 125°C

Supply Voltage to Ground

Potential.................................–0.5V to 6.0V (VCCmax + 0.5V)

DC Voltage Applied to Outputs

in High-Z State [5, 6]................–0.5V to 6.0V (VCCmax + 0.5V)

DC Input Voltage [5, 6] ............ –0.5V to 6.0V (VCCmax + 0.5V)

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage........................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current ......................................................>200mA

Operating Range

Device Range Ambient

Temperature VCC [7]

CY62148E Ind’l/Auto-A –40°C to +85°C 4.5V to 5.5V

Electrical Characteristics (Over the Operating Range)

Parameter Description Test Conditions 45 ns 55 ns [2]

Unit

Min Typ [3] Max Min Typ [3] Max

VOH Output HIGH

Voltage

IOH = –1 mA 2.4 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA 0.4 0.4 V

VIH Input HIGH Voltage VCC = 4.5V to 5.5V 2.2 VCC + 0.5 2.2 VCC + 0.5 V

VIL Input LOW voltage VCC = 4.5V to 5.5V For TSOPII

package

–0.5 0.8 V

For SOIC

package

–0.5 0.6 [8]

IIX Input Leakage

Current

GND < VI< VCC –1 +1 –1 +1 µA

IOZ Output Leakage

Current

GND < VO <VCC, Output Disabled –1 +1 –1 +1 µA

ICC VCC Operating

Supply Current

f = fmax = 1/tRC VCC = VCC(max)

IOUT = 0 mA

CMOS levels

15 20 15 20 mA

f = 1 MHz 2 2.5 2 2.5

ISB2 [9] Automatic CE Power

down Current —

CMOS Inputs

CE > VCC – 0.2V

VIN > VCC – 0.2V or VIN <0.2V,

f = 0, VCC = VCC(max)

17 17µA

Capacitance (For All Packages) [10]

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = VCC(typ)

10 pF

COUT Output Capacitance 10 pF

Notes

5. VIL(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA.

6. VIH(max) = VCC+0.75V for pulse durations less than 20 ns.

7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.

8. Under DC conditions the device meets a VIL of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6V. This

is applicable to SOIC package only. Refer to AN13470 for details.

9. Only chip enable (CE) must be HIGH at CMOS level to meet the ISB2 spec. Other inputs can be left floating.

10. Tested initially and after any design or process changes that may affect these parameters.

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Thermal Resistance [10]

Parameter Description Test Conditions SOIC

Package

TSOP II

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Still Air, soldered on a 3 × 4.5 inch,

two-layer printed circuit board

75 77 °C/W

ΘJC Thermal Resistance

(Junction to Case)

10 13 °C/W

AC Test Loads and Waveforms

Parameters 5.0V Unit

R1 1800 Ω

R2 990 Ω

RTH 639 Ω

VTH 1.77 V

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min Typ [3] Max Unit

VDR VCC for Data Retention 2 V

ICCDR Data Retention Current VCC= VDR, CE > VCC – 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V

Ind’l/Auto-A 1 7 µA

tCDR [10] Chip Deselect to Data Retention Time 0 ns

tR [11] Operation Recovery Time tRC ns

Data Retention Waveform

3.0V

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

Rise Time = 1 V/ns Fall Time = 1 V/ns

OUTPUT V

Equivalent to: THEVENIN EQUIVALENT

ALL INPUT PULSES

RTH

VCC(min)

tCDR

VDR >2.0V

DATA RETENTION MODE

VCC

Note

11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.

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Document #: 38-05442 Rev. *F Page 5 of 10

Switching Characteristics (Over the Operating Range) [12]

Parameter Description 45 ns 55 ns [2]

Unit

Min Max Min Max

Read Cycle

tRC Read Cycle Time 45 55 ns

tAA Address to Data Valid 45 55 ns

tOHA Data Hold from Address Change 10 10 ns

tACE CE LOW to Data Valid 45 55 ns

tDOE OE LOW to Data Valid 22 25 ns

tLZOE OE LOW to LOW Z [13] 55ns

tHZOE OE HIGH to High Z [13, 14] 18 20 ns

tLZCE CE LOW to Low Z [13] 10 10 ns

tHZCE CE HIGH to High Z [13, 14] 18 20 ns

tPU CE LOW to Power up 00ns

tPD CE HIGH to Power down 45 55 ns

Write Cycle [15]

tWC Write Cycle Time 45 55 ns

tSCE CE LOW to Write End 35 40 ns

tAW Address Setup to Write End 35 40 ns

tHA Address Hold from Write End 0 0 ns

tSA Address Setup to Write Start 0 0 ns

tPWE WE Pulse Width 35 40 ns

tSD Data Setup to Write End 25 25 ns

tHD Data Hold from Write End 0 0 ns

tHZWE WE LOW to High-Z [13, 14] 18 20 ns

tLZWE WE HIGH to Low-Z [13] 10 10 ns

Notes

12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels

of 0 to 3V, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.

13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

14. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.

15. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can

terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.

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CY62148E MoBL®

Document #: 38-05442 Rev. *F Page 6 of 10

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled) [16, 17]

Read Cycle No. 2 (OE Controlled) [17, 18]

Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [19, 20]

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tHZCE

tPD

IMPEDANCE

ICC

ISB

HIGH

ADDRESS

DATA OUT

VCC

SUPPLY

CURRENT

DATA VALID

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

ADDRESS

DATA IO

NOTE

Notes:

16. Device is continuously selected. OE, CE = VIL.

17. WE is HIGH for read cycles.

18. Address valid before or similar to CE transition LOW.

19. Data IO is high impedance if OE = VIH.

20. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.

21. During this period, the IOs are in output state and input signals must not be applied.

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Document #: 38-05442 Rev. *F Page 7 of 10

Write Cycle No. 2 (CE Controlled) [19, 20]

Write Cycle No. 3 (WE Controlled, OE LOW) [20]

Truth Table

CE WE OE IO’s Mode Power

H X X High Z Deselect/Power down Standby (ISB)

L H L Data Out Read Active (ICC)

L L X Data In Write Active (ICC)

L H H High Z Selected, Outputs Disabled Active (ICC)

Switching Waveforms (continued)

tWC

DATA VALID

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

ADDRESS

DATA IO

DATA VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

ADDRESS

DATA IO

NOTE

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CY62148E MoBL®

Document #: 38-05442 Rev. *F Page 8 of 10

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

45 CY62148ELL-45ZSXI 51-85095 32-pin Thin Small Outline Package II (Pb-free) Industrial

55 CY62148ELL-55SXI 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Industrial

55 CY62148ELL-55SXA 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Automotive-A

Contact your local Cypress sales representative for availability of these parts.

Package Diagrams

Figure 1. 32-pin TSOP II, 51-85095

51-85095-**

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CY62148E MoBL®

Document #: 38-05442 Rev. *F Page 9 of 10

the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended

to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Figure 2. 32-pin (450 MIL) Molded SOIC, 51-85081

MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names

mentioned in this document are the trademarks of their respective holders.

Package Diagrams (continued)

0.546[13.868]

0.440[11.176]

0.101[2.565]

0.050[1.270]

0.014[0.355]

0.118[2.997]

0.004[0.102]

0.047[1.193]

0.006[0.152]

0.023[0.584]

0.793[20.142]

0.450[11.430]

0.566[14.376]

0.111[2.819]

0.817[20.751]

BSC.

0.020[0.508]

MIN.

MAX.

0.012[0.304]

0.039[0.990]

0.063[1.600]

SEATING PLANE

116

17 32

0.004[0.102]

51-85081-*B

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Document #: 38-05442 Rev. *F Page 10 of 10

Document History Page

Document Title: CY62148E MoBL®, 4-Mbit (512K x 8) Static RAM

Document Number: 38-05442

REV. ECN NO. Issue

Date

Orig. of

Change Description of Change

** 201580 01/08/04 AJU New Data Sheet

*A 249276 See ECN SYT Changed from Advance Information to Preliminary

Moved Product Portfolio to Page 2

Added RTSOP II and Removed FBGA Package

Changed VCC stabilization time in footnote #7 from 100 µs to 200 µs

Changed ICCDR from 2.0 µA to 2.5 µA

Changed typo in Data Retention Characteristics(tR) from 100 µs to tRC ns

Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin

Changed tHZOE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45

ns Speed Bin

Changed tSCE from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed

Bin

Changed tHZCE from 12 to18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns

Speed Bin

Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for

45 ns Speed Bin

Changed tDOE from 15 to 18 ns for 35 ns Speed Bin

Corrected typo in Package Name

Changed Ordering Information to include Pb-Free Packages

*B 414820 See ECN ZSD Changed from Preliminary to Final

Changed the address of Cypress Semiconductor Corporation on Page #1 from

“3901 North First Street” to “198 Champion Court”

Removed 35ns Speed Bin

Removed “L” version of CY62148E

Changed ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz

Changed ICC (Max) value from 2 mA to 2.5 mA at f=1 MHz

Changed ICC (Typ) value from 12 mA to 15 mA at f=fmax

Removed ISB1 spec from the Electrical characteristics table

Changed ISB2 Typ values from 0.7 µA to 1 µA and Max values from 2.5 µA to 7 µA

Modified footnote #4 to include current limit

Removed redundant footnote on DNU pins

Changed the AC testload capacitance from 100 pF to 30 pF on page #4

Changed test load parameters R1, R2, RTH and VTH from 1838 Ω, 994 Ω,

645 Ω and 1.75V to 1800 Ω, 990 Ω, 639 Ω and 1.77V

Changed ICCDR from 2.5 µA to 7 µA

Added ICCDR typical value

Changed tLZOE from 3 ns to 5 ns

Changed tLZCE and tLZWE from 6 ns to 10 ns

Changed tHZCE from 22 ns to 18 ns

Changed tPWE from 30 ns to 35 ns

Changed tSD from 22 ns to 25 ns

Updated the ordering information table and replaced Package Name column with

Package Diagram

*C 464503 See ECN NXR Included Automotive Range in product offering

Updated the Ordering Information

*D 485639 See ECN VKN Corrected the operating range to 4.5V - 5.5V on page# 3

*E 833080 See ECN VKN Added footnote #8

Added VILspec for SOIC package

*F 890962 See ECN VKN Added Automotive-A part and its related information

Removed Automotive-E part and its related information

Added footnote #2 related to SOIC package

Added footnote #9 related to ISB2

Added AC values for 55 ns Industrial-SOIC range

Updated Ordering Information table

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