Cypress Semiconductor STK12C68-5 Manual de usuario

STK12C68-5 (SMD5962-94599)

64 Kbit (8K x 8) AutoStore nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-51026 Rev. ** Revised March 02, 2009

Features

■35 ns and 55 ns access times

■Hands off automatic STORE on power down with external

68 µF capacitor

■STORE to QuantumTrap™ nonvolatile elements is initiated

by software, hardware, or AutoStore™ on power down

■RECALL to SRAM initiated by software or power up

■Unlimited Read, Write, and Recall cycles

■1,000,000 STORE cycles to QuantumTrap

■100 year data retention to QuantumTrap

■Single 5V+10% operation

■Military temperature

■28-pin (300mil) CDIP and 28-pad LCC packages

Functional Description

The Cypress STK12C68-5 is a fast static RAM with a nonvol-

atile element in each memory cell. The embedded nonvolatile

elements incorporate QuantumTrap technology producing the

world’s most reliable nonvolatile memory. The SRAM provides

unlimited read and write cycles, while independent nonvolatile

data resides in the highly reliable QuantumTrap cell. Data

transfers from the SRAM to the nonvolatile elements (the

STORE operation) takes place automatically at power down.

On power up, data is restored to the SRAM (the RECALL

operation) from the nonvolatile memory. Both the STORE and

RECALL operations are also available under software control.

A hardware STORE is initiated with the HSB pin.

Logic Block Diagram

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

128 X 512

Quantum Trap

128 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT BUFFERS

HSB

CC V

CAP

A0-A12

A0A1A2A3A4A10

A11

A12

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

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STK12C68-5 (SMD5962-94599)

Document Number: 001-51026 Rev. ** Page 2 of 18

Pinouts

Pin Definitions

Pin Name Alt IO Type Description

A0–A12 Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

DQ0-DQ7Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.

WE WInput Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO

pins is written to the specific address location.

CE EInput Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the

chip.

OE GInput OutputEnable,ActiveLOW.TheactiveLOWOEinputenablesthedataoutputbuffersduring

read cycles. Deasserting OE HIGH causes the IO pins to tri-state.

VSS Ground Ground for the Device. The device is connected to ground of the system.

VCC Power Supply Power Supply Inputs to the Device.

HSB Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in

progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A

weak internal pull up resistor keeps this pin high if not connected (connection optional).

VCAP Power Supply AutoStoreCapacitor.SuppliespowertonvSRAMduringpowerlosstostoredatafromSRAM

to nonvolatile elements.

Figure 1. Pin Diagram - 28-Pin DIP Figure 2. Pin Diagram - 28-Pin LLC

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STK12C68-5 (SMD5962-94599)

Document Number: 001-51026 Rev. ** Page 3 of 18

Device Operation

The STK12C68-5 nvSRAM is made up of two functional compo-

nents paired in the same physical cell. These are an SRAM

memory cell and a nonvolatile QuantumTrap cell. The SRAM

memory cell operates as a standard fast static RAM. Data in the

SRAM is transferred to the nonvolatile cell (the STORE

operation) or from the nonvolatile cell to SRAM (the RECALL

operation). This unique architecture enables the storage and

recall of all cells in parallel. During the STORE and RECALL

operations, SRAM Read and Write operations are inhibited. The

STK12C68-5 supports unlimited reads and writes similar to a

typical SRAM. In addition, it provides unlimited RECALL opera-

tions from the nonvolatile cells and up to one million STORE

operations.

SRAM Read

The STK12C68-5 performs a Read cycle whenever CE and OE

are LOW while WE and HSB are HIGH. The address specified

on pins A0–12 determines the 8,192 data bytes accessed. When

the Read is initiated by an address transition, the outputs are

valid after a delay of tAA (Read cycle 1). If the Read is initiated

by CE or OE, the outputs are valid at tACE or at tDOE, whichever

is later (Read cycle 2). The data outputs repeatedly respond to

address changes within the tAA access time without the need for

transitions on any control input pins, and remains valid until

another address change or until CE or OE is brought HIGH, or

WE or HSB is brought LOW.

SRAM Write

A Write cycle is performed whenever CE and WE are LOW and

HSBis HIGH.The addressinputsmustbe stableprior toentering

the Write cycle and must remain stable until either CE or WE

goes HIGH at the end of the cycle. The data on the common IO

pins DQ0–7 are written into the memory if it has valid tSD, before

the end of a WE controlled Write or before the end of an CE

controlled Write. Keep OE HIGH during the entire Write cycle to

avoid data bus contention on common IO lines. If OE is left LOW,

internal circuitry turns off the output buffers tHZWE after WE goes

LOW.

AutoStore Operation

The STK12C68-5 stores data to nvSRAM using one of three

storage operations:

1. Hardware store activated by HSB

2. Software store activated by an address sequence

3. AutoStore on device power down

AutoStore operation is a unique feature of QuantumTrap

technology and is enabled by default on the STK12C68-5.

During normal operation, the device draws current from VCC to

charge a capacitor connected to the VCAP pin. This stored

charge is used by the chip to perform a single STORE operation.

If the voltage on the VCC pin drops below VSWITCH, the part

automatically disconnects the VCAP pin from VCC. A STORE

operation is initiated with power provided by the VCAP capacitor.

Figure 3 shows the proper connection of the storage capacitor

(VCAP) for automatic store operation. A charge storage capacitor

between 68 µFand220µF(+20%)rated at 6V mustbeprovided.

The voltage on the VCAP pin is driven to 5V by a charge pump

internal to the chip. A pull up is placed on WE to hold it inactive

during power up.

In system power mode, both VCC and VCAP are connected to the

+5V power supply without the 68 μF capacitor. In this mode, the

AutoStore function of the STK12C68-5 operates on the stored

system charge as power goes down. The user must, however,

guarantee that VCC does not drop below 3.6V during the 10 ms

STORE cycle.

To reduce unnecessary nonvolatile stores, AutoStore, and

Hardware Store operations areignored,unlessat least oneWrite

operation has taken place since the most recent STORE or

RECALL cycle. Software initiated STORE cycles are performed

regardless of whether a Write operation has taken place. An

optional pull up resistor is shown connected to HSB.The HSB

signal is monitored by the system to detect if an AutoStore cycle

is in progress.

Figure 3. AutoStore Mode

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STK12C68-5 (SMD5962-94599)

Document Number: 001-51026 Rev. ** Page 4 of 18

Figure 4. AutoStore Inhibit Mode

If the power supply drops faster than 20 us/volt before Vcc

reaches VSWITCH, then a 2.2 ohm resistor must be connected

between VCC and the system supply to avoid momentary

excess of current between VCC and VCAP.

AutoStore Inhibit Mode

Ifan automaticSTOREonpower lossis notrequired,then VCC

is tied to ground and +5V is applied to VCAP (Figure 4). This is

the AutoStore Inhibit mode, where the AutoStore function is

disabled. If the STK12C68-5 is operated in this configuration,

references to VCC are changed to VCAP throughout this data

sheet. In this mode, STORE operations are triggered through

softwarecontrolortheHSBpin. To enableordisableAutostore

using an IO port pin see Preventing Store on page 5.It is not

permissible to change between these three options “on the

fly”.

Hardware STORE (HSB) Operation

The STK12C68-5 provides the HSB pin for controlling and

acknowledging the STORE operations. The HSB pin is used

to request a hardware STORE cycle. When the HSB pin is

driven LOW, the STK12C68-5 conditionally initiates a STORE

operation after tDELAY. An actual STORE cycle only begins if a

Write to the SRAM takes place since the last STORE or

RECALL cycle. The HSB pin also acts as an open drain driver

that is internally driven LOW to indicate a busy condition, while

the STORE (initiated by any means) is in progress.

SRAM Read and Write operations, that are in progress when

HSB is driven LOW by any means, are given time to complete

before the STORE operation is initiated. After HSB goes LOW,

the STK12C68-5 continues SRAM operations for tDELAY.

During tDELAY, multiple SRAM Read operations take place. If

a Write is in progress when HSB is pulled LOW, it allows a

time, tDELAY to complete. However, any SRAM Write cycles

requested after HSB goes LOW are inhibited until HSB returns

HIGH.

During any STORE operation, regardless of how it is initiated,

the STK12C68-5 continues to drive the HSB pin LOW,

releasing it only when the STORE is complete. After

completing the STORE operation, the STK12C68-5 remains

disabled until the HSB pin returns HIGH.

If HSB is not used, it is left unconnected.

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC <

VRESET), an internal RECALL request is latched. When VCC

once again exceeds the sense voltage of VSWITCH, a RECALL

cycleis automaticallyinitiatedandtakestHRECALL tocomplete.

If the STK12C68-5 is in a Write state at the end of power up

RECALL, the SRAM data is corrupted. To help avoid this

situation, a 10 Kohm resistor is connected either between WE

and system VCC or between CE and system VCC.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory

by a software address sequence. The STK12C68-5 software

STOREcycleisinitiatedbyexecutingsequentialCEcontrolled

Read cycles from six specific address locations in exact order.

During the STORE cycle, an erase of the previous nonvolatile

data is first performed followed by a program of the nonvolatile

elements. When a STORE cycle is initiated, input and output

are disabled until the cycle is completed.

Because a sequence of Reads from specific addresses is

used for STORE initiation, it is important that no other Read or

Write accesses intervene in the sequence. If they intervene,

the sequence is aborted and no STORE or RECALL takes

place.

To initiate the software STORE cycle, the following Read

sequence is performed:

1. Read address 0x0000, Valid READ

2. Read address 0x1555, Valid READ

3. Read address 0x0AAA, Valid READ

4. Read address 0x1FFF, Valid READ

5. Read address 0x10F0, Valid READ

6. Read address 0x0F0F, Initiate STORE cycle

The software sequence is clocked with CE controlled Reads

or OE controlled Reads. When the sixth address in the

sequence is entered, the STORE cycle commences and the

chip is disabled. It is important that Read cycles and not Write

cycles are used in the sequence. It is not necessary that OE

is LOW for a valid sequence. After the tSTORE cycle time is

fulfilled, the SRAM is again activated for Read and Write

operation.

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM

by a software address sequence. A software RECALL cycle is

initiated with a sequence of Read operations in a manner

similar to the software STORE initiation. To initiate the

RECALL cycle, the following sequence of CE controlled Read

operations is performed:

1. Read address 0x0000, Valid READ

2. Read address 0x1555, Valid READ

3. Read address 0x0AAA, Valid READ

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STK12C68-5 (SMD5962-94599)

Document Number: 001-51026 Rev. ** Page 5 of 18

4. Read address 0x1FFF, Valid READ

5. Read address 0x10F0, Valid READ

6. Read address 0x0F0E, Initiate RECALL cycle

Internally, RECALLis atwo stepprocedure.First, the SRAMdata

is cleared; then, the nonvolatile information is transferred into the

SRAM cells. After the tRECALL cycle time, the SRAM is again

ready for Read and Write operations. The RECALL operation

does not alter the data in the nonvolatile elements. The nonvol-

atile data can be recalled an unlimited number of times.

Data Protection

The STK12C68-5 protects data from corruption during low

voltage conditions by inhibiting all externally initiated STORE

and Write operations. The low voltage condition is detected

when VCC is less than VSWITCH. If the STK12C68-5 is in a Write

mode (both CE and WE are low) at power up after a RECALL or

after a STORE, the Write is inhibited until a negative transition

onCEorWEisdetected.Thisprotectsagainstinadvertentwrites

during power up or brown out conditions.

Noise Considerations

The STK12C68-5 is a high speed memory. It must have a high

frequency bypass capacitor of approximately 0.1 µF connected

between VCC and VSS, using leads and traces that are as short

as possible. As with all high speed CMOS ICs, careful routing of

power, ground, and signals reduce circuit noise.

Hardware Protect

The STK12C68-5 offers hardware protection against inadvertent

STORE operation and SRAM Writes during low voltage condi-

tions. When VCAP<VSWITCH, all externally initiated STORE

operations and SRAM Writes are inhibited. AutoStore can be

completely disabled by tying VCC to ground and applying +5V to

VCAP. This is the AutoStore Inhibit mode; in this mode, STOREs

are only initiated by explicit request using either the software

sequence or the HSB pin.

Low Average Active Power

CMOS technology provides the STK12C68-5 the benefit of

drawing significantly lesscurrentwhenitis cycled at timeslonger

than 50 ns. Figure 5 and Figure 6 shows the relationship

between ICC and Read or Write cycle time. Worst case current

consumption is shown for both CMOS and TTL input levels

(commercial temperature range, VCC = 5.5V, 100% duty cycle

on chip enable). Only standby current is drawn when the chip is

disabled. The overall average current drawn by the STK12C68-5

depends on the following items:

■The duty cycle of chip enable

■The overall cycle rate for accesses

■The ratio of Reads to Writes

■CMOS versus TTL input levels

■The operating temperature

■The VCC level

Preventing Store

The STORE function is disabled by holding HSB high with a

driver capable of sourcing 30 mA at a VOH of at least 2.2V,

because it must overpower the internal pull down device. This

device drives HSB LOW for 20 μs at the onset of a STORE.

When the STK12C68-5 is connected for AutoStore operation

(system VCC connected to VCC and a 68 μF capacitor on VCAP)

and VCC crosses VSWITCH on the way down, the STK12C68-5

attempts to pull HSB LOW. If HSB does not actually get below

VIL, the part stops trying to pull HSB LOW and abort the STORE

attempt.

Figure 5. Current Versus Cycle Time (Read)

Figure 6. Current Versus Cycle Time (Write)

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STK12C68-5 (SMD5962-94599)

Document Number: 001-51026 Rev. ** Page 6 of 18

Best Practices

nvSRAM products have been used effectively for over 15

years. While ease-of-use is one of the product’s main system

values, experience gained working with hundreds of applica-

tions has resulted in the following suggestions as best

practices:

■The nonvolatile cells in an nvSRAM are programmed on the

test floor during final test and quality assurance. Incoming

inspection routines at customer or contract manufacturer’s

sitessometimesreprogramsthesevalues.FinalNVpatterns

are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.

The end product’s firmware must not assume that an NV

array is in a set programmed state. Routines that check

memorycontentvaluestodeterminefirsttimesystemconfig-

uration, cold or warm boot status, and so on must always

program a unique NV pattern (for example, complex 4-byte

pattern of 46 E6 49 53 hex or more random bytes) as part of

the final system manufacturing test to ensure these system

routines work consistently.

■Power up boot firmware routines must rewrite the nvSRAM

into the desired state. While the nvSRAM is shipped in a

preset state, best practice is to again rewrite the nvSRAM

into the desired state as a safeguard against events that

might flip the bit inadvertently (program bugs, incoming

inspection routines, and so on).

■The Vcap value specified in this data sheet includes a

minimum and a maximum value size. The best practice is to

meet this requirement and not exceed the maximum Vcap

value because the higher inrush currents may reduce the

reliabilityoftheinternalpasstransistor.Customerswhowant

to use a larger Vcap value to make sure there is extra store

charge must discuss their Vcap size selection with Cypress.

Table 1. Hardware Mode Selection

CE WE HSB A12–A0 Mode IO Power

H X H X Not Selected Output High Z Standby

L H H X Read SRAM Output Data Active[3]

L L H X Write SRAM Input Data Active

X X L X Nonvolatile STORE Output High Z ICC2[1]

L H H 0x0000

0x1555

0x0AAA

0x1FFF

0x10F0

0x0F0F

Read SRAM

Nonvolatile STORE

Output Data

Output High Z

Active ICC2[2, 3]

L H H 0x0000

0x1555

0x0AAA

0x1FFF

0x10F0

0x0F0E

Read SRAM

Nonvolatile RECALL

Output Data

Output High Z

Active[2, 3]

Notes

1. HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby

mode, inhibiting all operations until HSB rises.

2. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.

3. IO state assumes OE < VIL. Activation of nonvolatile cycles does not depend on state of OE.

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STK12C68-5 (SMD5962-94599)

Document Number: 001-51026 Rev. ** Page 7 of 18

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Temperature under Bias............................. –55°C to +125°C

Voltage on Input Relative to GND.....................–0.5V to 7.0V

Voltage on Input Relative to Vss............–0.6V to VCC + 0.5V

Voltage on DQ0-7 or HSB .......................–0.5V to Vcc + 0.5V

Power Dissipation..........................................................1.0W

DC output Current (1 output at a time, 1s duration) ....15 mA

Operating Range

Range Ambient Temperature VCC

Military -55°C to +125°C 4.5V to 5.5V

DC Electrical Characteristics

Over the operating range (VCC = 4.5V to 5.5V) [4]

Parameter Description Test Conditions Min Max Unit

ICC1 Average VCC Current tRC = 35 ns

tRC = 55 ns

Dependent on output loading and cycle rate. Values

obtained without output loads.

IOUT = 0 mA.

55 mA

ICC2 Average VCC Current

during STORE All Inputs Do Not Care, VCC = Max

Average current for duration tSTORE 3mA

ICC3 AverageVCCCurrentat

tRC= 200 ns, 5V, 25°C

Typical

WE > (VCC – 0.2V). All other inputs cycling.

Dependent on output loading and cycle rate. Values

obtained without output loads.

10 mA

ICC4 Average VCAP Current

during AutoStore Cycle All Inputs Do Not Care, VCC = Max

Average current for duration tSTORE 2mA

ISB1[5] VCC Standby Current

(Standby, Cycling TTL

Input Levels)

tRC = 35 ns, CE > VIH

tRC = 55 ns, CE > VIH 24

19 mA

ISB2 [5] VCC Standby Current CE > (VCC – 0.2V). All others VIN <0.2V or > (VCC – 0.2V).

Standby current level after nonvolatile cycle is complete.

Inputs are static. f = 0 MHz.

2.5 mA

IIX Input Leakage Current VCC = Max, VSS < VIN <VCC -1 +1 μA

IOZ Off State Output

Leakage Current VCC = Max, VSS < VIN <VCC, CE or OE > VIH or WE < VIL -5 +5 μA

VIH Input HIGH Voltage 2.2 VCC + 0.5 V

VIL Input LOW Voltage VSS – 0.5 0.8 V

VOH Output HIGH Voltage IOUT = –4 mA 2.4 V

VOL Output LOW Voltage IOUT = 8 mA 0.4 V

VBL Logic ‘0’ Voltage on

HSB Output IOUT = 3 mA 0.4 V

VCAP Storage Capacitor Between Vcap pin and Vss, 6V rated. 68 µF +20% nom. 54 260 µF

Notes

4. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground.

5. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.

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STK12C68-5 (SMD5962-94599)

Document Number: 001-51026 Rev. ** Page 8 of 18

Data Retention and Endurance

Parameter Description Min Unit

DATARData Retention 100 Years

NVCNonvolatile STORE Operations 1,000 K

Capacitance

In the following table, the capacitance parameters are listed.[6]

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = 0 to 3.0 V 8pF

COUT Output Capacitance 7pF

Thermal Resistance

In the following table, the thermal resistance parameters are listed.[6]

Parameter Description Test Conditions 28-CDIP 28-LCC Unit

ΘJA Thermal Resistance

(Junction to Ambient) Test conditions follow standard test methods and

procedures for measuring thermal impedance, per

EIA / JESD51.

TBD TBD °C/W

ΘJC Thermal Resistance

(Junction to Case) TBD TBD °C/W

Figure 7. AC Test Loads

AC Test Conditions

5.0V

Output

30 pF

R1 963Ω

512Ω

5.0V

Output

5 pF

R1 963

512

For Tri-state Specs

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times (10% to 90%)...................... <5 ns

Input and Output Timing Reference Levels.......................1.5

Note

6. These parameters are guaranteed by design and are not tested.

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STK12C68-5 (SMD5962-94599)

Document Number: 001-51026 Rev. ** Page 9 of 18

AC Switching Characteristics

SRAM Read Cycle

Parameter Description 35 ns 55 ns Unit

Min Max Min Max

Cypress

Parameter Alt

tACE tELQV Chip Enable Access Time 35 55 ns

tRC [7] tAVAV, tELEH Read Cycle Time 35 55 ns

tAA [8] tAVQV Address Access Time 35 55 ns

tDOE tGLQV Output Enable to Data Valid 15 35 ns

tOHA [8] tAXQX Output Hold After Address Change 5 5 ns

tLZCE [9] tELQX Chip Enable to Output Active 5 5 ns

tHZCE [9] tEHQZ Chip Disable to Output Inactive 10 12 ns

tLZOE [9] tGLQX Output Enable to Output Active 0 0 ns

tHZOE [9] tGHQZ Output Disable to Output Inactive 10 12 ns

tPU [6] tELICCH Chip Enable to Power Active 0 0 ns

tPD [6] tEHICCL Chip Disable to Power Standby 35 55 ns

Switching Waveforms Figure 8. SRAM Read Cycle 1: Address Controlled [7, 8]

Figure 9. SRAM Read Cycle 2: CE and OE Controlled [7]

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Notes

7. WE and HSB must be High during SRAM Read cycles.

8. Device is continuously selected with CE and OE both Low.

9. Measured ±200 mV from steady state output voltage.

[+] Feedback

STK12C68-5 (SMD5962-94599)

Document Number: 001-51026 Rev. ** Page 10 of 18

SRAM Write Cycle

Parameter Description 35 ns 55 ns Unit

Min Max Min Max

Cypress

Parameter Alt

tWC tAVAV Write Cycle Time 35 55 ns

tPWE tWLWH, tWLEH Write Pulse Width 25 45 ns

tSCE tELWH, tELEH Chip Enable To End of Write 25 45 ns

tSD tDVWH, tDVEH Data Setup to End of Write 12 25 ns

tHD tWHDX, tEHDX Data Hold After End of Write 0 0 ns

tAW tAVWH, tAVEH Address Setup to End of Write 25 45 ns

tSA tAVWL, tAVEL Address Setup to Start of Write 0 0 ns

tHA tWHAX, tEHAX Address Hold After End of Write 0 0 ns

tHZWE [9,10] tWLQZ Write Enable to Output Disable 13 15 ns

tLZWE [9] tWHQX Output Active After End of Write 5 5 ns

Switching Waveforms Figure 10. SRAM Write Cycle 1: WE Controlled [11, 12]

Figure 11. SRAM Write Cycle 2: CE Controlled [11, 12]

tWC

tSCE

tHA

tAW

tSA

tPWE

tSD tHD

tHZWE tLZWE

ADDRESS

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

ADDRESS

SCE

PWE

DATA IN

DATA OUT HIGH IMPEDANCE

DATA VALID

Notes

10.If WE is Low when CE goes Low, the outputs remain in the high impedance state.

11. HSB must be high during SRAM Write cycles.

12.CE or WE must be greater than VIH during address transitions.

[+] Feedback

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