Cypress Semiconductor CY7C0241AV Manual de usuario

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

3.3V 4K/8K/16K x 16/18 Dual-Port

Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document #: 38-06052 Rev. *J Revised December 10, 2008

Features

■

True dual-ported memory cells which enable simultaneous

access of the same memory location

■

4, 8 or 16K × 16 organization

■

(CY7C024AV/024BV

[1]

/ 025AV/026AV)

■

4 or 8K × 18 organization (CY7C0241AV/0251AV)

■

16K × 18 organization (CY7C036AV)

■

0.35 micron CMOS for optimum speed and power

■

High speed access: 20 and 25 ns

■

Low operating power

❐

Active: I

= 115 mA (typical)

❐

Standby: I

SB3

= 10 μA (typical)

■

Fully asynchronous operation

■

Automatic power down

■

Expandable data bus to 32 bits, 36 bits or more using Master

and Slave chip select when using more than one device

■

On chip arbitration logic

■

Semaphores included to permit software handshaking

between ports

■

INT flag for port-to-port communication

■

Separate upper byte and lower byte control

■

Pin select for Master or Slave (M/S)

■

Commercial and industrial temperature ranges

■

Available in 100-pin Pb-free TQFP and 100-pin TQFP

Notes

1. CY7C024AV and CY7C024BV are functionally identical.

2. IO

–IO

for x16 devices; IO

–IO

for x18 devices.

3. IO

–IO

for x16 devices; IO

–IO

for x18 devices.

4. A

–A

for 4K devices; A

–A

for 8K devices; A

–A

for 16K devices.

5. BUSY is an output in master mode and an input in slave mode.

R/W

8/9L

–IO

15/17L

Control

Address

Decode

–A

11/12/13L

R/W

BUSY

Control

Interrupt

Semaphore

Arbitration

SEM

INT

M/S

–IO

7/8L

R/W

8/9L

–IO

15/17R

–IO

7/8R

–A

11/1213L

True Dual-Ported

RAM Array

–A

11/12/13R

R/W

BUSY

SEM

INT

Address

Decode A

–A

11/12/13R

[2] [2]

[3] [3]

[5] [5]

12/13/14

8/9

12/13/14

8/9

12/13/14 12/13/14

[4]

Logic Block Diagram

[+] Feedback

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *J Page 2 of 19

Pin Configurations

Figure 1. 100-Pin TQFP (Top View)

Notes

6. A

12L

on the CY7C025AV.

7. A

12R

on the CY7C025AV.

100 99 9798 96

4241

95 94

27 28 3029 31 32 3534 36 37 3833

89 88 8687 8593 92 84

INT

BUSY

GND

INT

10L

11L

15L

GND

9091

M/S

BUSY

14L

GND

12L

13L

83 82 81 80 79 78 77 76

43 44 45 46 4748 49 50

GND

SEM

11L

10L

10R

11R

12R

13R

14R

GND

15R

R\W

GND

SEM

11R

10R

CY7C024AV/024BV (4K × 16)

[6]

[7]

CY7C025AV (8K × 16)

[+] Feedback

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *J Page 3 of 19

Figure 2. 100-Pin TQFP (Top View)

Notes

8. A

12L

on the CY7C0251AV.

9. A

12R

on the CY7C0251AVC.

Pin Configurations

(continued)

100 99 9798 96

4241

95 94

27 28 3029 31 32 3534 36 37 3833

89 88 8687 8593 92 84

INT

BUSY

GND

INT

11L

12L

16L

GND

9091

BUSY

15L

GND

13L

14L

83 82 81 80 79 78 77 76

43 44 45 46 47 48 49 50

10L

GND

SEM

11L

10L

16R

10R

11R

12R

13R

14R

GND

15R

GND

SEM

11R

10R

CY7C0241AV (4K × 18)

17L

17R

[9] [8]

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

A6L

A5L

A4L

INT

A2L

A0L

GND

A0R

A1R

A1L

A3L

BUSY

INT

A2R

A3R

A4R

A5R

BUSY

CY7C026AV (16K × 16)

IO10L

IO11L

IO15L

IO13L

IO14L

GND

IO0R

VCC

IO3R

GND

IO12L

IO1R

IO2R

IO4R

IO5R

IO6R

VCC

IO9L

IO8L

IO7L

IO6L

IO5L

IO4L

IO0L

IO2L

IO1L

VCC

GND

IO3L

SEM

A13L

A12L

A11L

A10L

A9L

A8L

A7L

34 35 36 424139 403837 43 44 45 5048 494746

A6R

A7R

A8R

A9R

A10R

A11R

A13R

GND

IO14R

A12R

IO15R

IO13R

IO12R

IO11R

IO10R

IO9R

IO8R

IO7R

SEM

3332313029282726

CY7C0251AV (8K × 18)

[+] Feedback

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *J Page 4 of 19

Figure 3. 100-Pin TQFP (Top View)

Pin Configurations

(continued)

100 99 9798 96

4241

4039

95 94

27 28 3029 31 32 3534 36 37 3833

89 88 8687 8593 92 84

INT

BUSY

GND

INT

11L

12L

16L

GND

9091

M/S

BUSY

15L

GND

13L

14L

83 82 81 80 79 78 77 76

43 44 45 46 4748 49 50

10L

GND

SEM

11L

10L

16R

10R

11R

12R

13R

14R

GND

15R

R/W

GND

SEM

11R

10R

17L

17R

R/W

CY7C036AV (16K × 18)

13L

13R

12L

12R

Selection Guide

Parameter CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

-20

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

-25 Unit

Maximum Access Time 20 25 ns

Typical Operating Current 120 115 mA

Typical Standby Current for I

SB1

(Both ports TTL Level) 35 30 mA

Typical Standby Current for I

SB3

(Both ports CMOS Level) 10 10 μA

[+] Feedback

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *J Page 5 of 19

Architecture

The CY7C024AV/024BV/025AV/026AV and

CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and

16K words of 16 and 18 bits each of dual-port RAM cells, IO and

addresslines,andcontrolsignals(CE, OE,RW). Thesecontrol pins

permit independent access for reads or writes to any location in

memory. To handle simultaneous writes and reads to the same

location, a BUSY pin is provided on each port. Two Interrupt (INT)

pins can be used for port to port communication. Two Semaphore

(SEM) control pins are used for allocating shared resources. With

the M/S pin, the devices can function as a master (BUSY pins are

outputs) or as a slave (BUSY pins are inputs). They also have an

automatic power down feature controlled by CE. Each port has its

ownoutputenablecontrol(OE),whichenables data to bereadfrom

the device.

Functional Description

The CY7C024AV/024BV/025AV/026AV and

CY7C0241AV/0251AV/036AV are low power CMOS 4K, 8K, and

16K ×16/18 dual port static RAMs. Various arbitration schemes are

included on the devices to handle situations when multiple

processors access the same piece of data. There are two ports

permitting independent, asynchronous access for reads and writes

to any location in memory. The devices can be used as standalone

16 or18-bit dual port static RAMs or multiple devices can be

combined to function as a 32 or 36-bit or wider master and slave

dual port static RAM. An M/S pin is provided for implementing 32 or

36-bit or wider memory applications. It does not need separate

master and slave devices or additional discrete logic. Application

areas include interprocessor/multiprocessor designs, communica-

tions status buffering, and dual port video and graphics memory.

Each port has independent control pins: Chip Enable (CE), Read

or Write Enable (R/W), and Output Enable (OE). Two flags are

provided on each port (BUSY and INT). BUSY signals that the

port is trying to access the same location currently being

accessed by the other port. The Interrupt flag (INT) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from one

port to the other to indicate that a shared resource is in use. The

semaphore logic has eight shared latches. Only one side can

control the latch (semaphore) at any time. Control of a

semaphore indicates that a shared resource is in use. An

automatic power down feature is controlled independently on

each port by a Chip Select (CE) pin.

The CY7C024AV/024BV/025AV/026AV and

CY7C0241AV0251AV/036AV are available in 100-pin Pb-free Thin

Quad Flat Pack (TQFP) and 100-pin TQFP.

Write Operation

Data must be set up for a duration of t

before the rising edge

of RW to guarantee a valid write. A write operation is controlled

byeitherthe RWpin(seeFigure 8onpage12) or theCE pin(see

Figure 9 on page 12). Required inputs for non-contention opera-

tions are summarized in Table 1 on page 7.

If a location is being written to by one port and the opposite port

triesto readthatlocation,there mustbe a portto portflowthrough

delay before the data is read on the output; otherwise the data

read is not deterministic. Data is valid on the port t

DDD

after the

data is presented on the other port.

Read Operation

When reading the device, the user must assert both the OE and

CE pins. Data is available t

ACE

after CE or t

DOE

after OE is

asserted. If the user wants to access a semaphore flag, then the

SEM pin and OE must be asserted.

Interrupts

The upper two memory locations are for message passing. The

highest memory location (FFF for the

CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV,

Pin Definitions

Left Port Right Port Description

Chip Enable

R/W

Read and Write Enable

Output Enable

–A

13L

–A

13R

Address (A

–A

for 4K devices; A

–A

for 8K devices; A

–A

for 16K)

–IO

17L

–IO

17R

Data Bus Input and Output

SEM

Semaphore Enable

Upper Byte Select (IO

–IO

for x16 devices; IO

–IO

for x18 devices)

Lower Byte Select (IO

–IO

for x16 devices; IO

–IO

for x18 devices)

INT

Interrupt Flag

BUSY

Busy Flag

M/S Master or Slave Select

Power

GND Ground

NC No Connect

[+] Feedback

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *J Page 6 of 19

3FFF for the CY7C026AV/36AV) is the mailbox for the right port

and the second highest memory location (FFE for the

CY7C024AV/024BV/41AV/1FFE for the CY7C025AV/51AV,

3FFE for the CY7C026AV/36AV) is the mailbox for the left port.

When one port writes to the other port’s mailbox, an interrupt is

generated to the owner. The interrupt is reset when the owner

reads the contents of the mailbox. The message is user defined.

Each port can read the other port’s mailbox without resetting the

interrupt. The active state of the busy signal (to a port) prevents

the port from setting the interrupt to the winning port. Also, an

active busy to a port prevents that port from reading its own

mailbox and, thus, resetting the interrupt to it.

If an application does not require message passing, do not

connect the interrupt pin to the processor’s interrupt request

input pin.

The operation of the interrupts and their interaction with Busy are

summarized in Table 2 on page 7.

Busy

The CY7C024AV/024BV/025AV/026AV and

CY7C0241AV/0251AV/036AV provide on-chip arbitration to resolve

simultaneous memory location access (contention). If both ports’

CEs are asserted and an address match occurs within t

of each

other, the busy logic determines which port has access. If t

violated, one port definitely gains permission to the location, but it is

not predictable which port gets that permission. BUSY is asserted

BLA

after an address match or t

BLC

after CE is taken LOW.

Master/Slave

A M/S pin helps to expand the word width by configuring the

device as a master or a slave. The BUSY output of the master is

connected to the BUSY input of the slave. This enables the

device to interface to a master device with no external compo-

nents. Writing to slave devices must be delayed until after the

BUSY input has settled (t

BLC

or t

BLA

). Otherwise, the slave chip

may begin a write cycle during a contention situation. When tied

HIGH, the M/S pin enables the device to be used as a master

and, therefore, the BUSY line is an output. BUSY can then be

used to send the arbitration outcome to a slave.

Semaphore Operation

The CY7C024AV/024BV/025AV/026AV and

CY7C0241AV/0251AV/036AV provide eight semaphore latches,

which are separate from the dual port memory locations.

Semaphores are used to reserve resources that are shared

between the two ports. The state of the semaphore indicates that

a resource is in use. For example, if the left port wants to request

a given resource, it sets a latch by writing a zero to a semaphore

location. The left port then verifies its success in setting the latch

by reading it. After writing to the semaphore, SEM or OE must

bedeasserted fort

SOP

beforeattempting to read the semaphore.

The semaphore value is available t

SWRD

+ t

DOE

after the rising

edge of the semaphore write. If the left port was successful

(reads a zero), it assumes control of the shared resource.

Otherwise (reads a one), it assumes the right port has control

and continues to poll the semaphore. When the right side has

relinquished control of the semaphore (by writing a one), the left

side succeeds in gaining control of the semaphore. If the left side

no longer requires the semaphore, a one is written to cancel its

request.

Semaphores are accessed by asserting SEM LOW. The SEM

pin functions as a chip select for the semaphore latches (CE

must remain HIGH during SEM LOW). A

0–2

represents the

semaphore address. OE and RW are used in the same manner

as a normal memory access. When writing or reading a

semaphore, the other address pins have no effect.

When writing to the semaphore, only IO

is used. If a zero is

written to the left port of an available semaphore, a one appears

at the same semaphore address on the right port. That

semaphore can now only be modified by the side showing zero

(the left port in this case). If the left port now relinquishes control

by writing a one to the semaphore, the semaphore is set to one

for both sides. However, if the right port had requested the

semaphore (written a zero) while the left port had control, the

right port would immediately own the semaphore as soon as the

left port released it. Table 3 on page 7 shows sample semaphore

operations.

When reading a semaphore, all 16 and 18 data lines output the

semaphore value. The read value is latched in an output register

to prevent the semaphore from changing state during a write

from the other port. If both ports attempt to access the

semaphore within t

SPS

of each other, the semaphore is definitely

obtained by one of them. But there is no guarantee which side

controls the semaphore.

[+] Feedback

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *J Page 7 of 19

Table 1. Non-Contending Read/Write

Inputs Outputs Operation

CE R/W OE UB LB SEM IO

–IO

H X X X X H High Z High Z Deselected: Power Down

X X X H H H High Z High Z Deselected: Power Down

L L X L H H Data In High Z Write to Upper Byte Only

L L X H L H High Z Data In Write to Lower Byte Only

L L X L L H Data In Data In Write to Both Bytes

L H L L H H Data Out High Z Read Upper Byte Only

L H L H L H High Z Data Out Read Lower Byte Only

L H L L L H Data Out Data Out Read Both Bytes

X X H X X X High Z High Z Outputs Disabled

H H L X X L Data Out Data Out Read Data in Semaphore Flag

X H L H H L Data Out Data Out Read Data in Semaphore Flag

H X X X L Data In Data In Write D

IN0

into Semaphore Flag

X X H H L Data In Data In Write D

IN0

into Semaphore Flag

L X X L X L Not Allowed

L X X X L L Not Allowed

Table 2. Interrupt Operation Example (assumes BUSY

= BUSY

= HIGH)

[10]

Left Port Right Port

Function R/W

0L–13L

INT

R/W

0R–13R

INT

Set Right INT

Flag L L X FFF

[13]

XXXX X L

[12]

Reset Right INT

Flag X X X X X X L L FFF (or 1/3FFF) H

[11]

Set Left INT

Flag XXX X L

[11]

L L X 1FFE (or 1/3FFE) X

Reset Left INT

Flag X L L 1FFE

[13]

[12]

XXX X X

Table 3. Semaphore Operation Example

Function IO

–IO

Left IO

–IO

Right Status

No action 1 1 Semaphore-free

Left port writes 0 to semaphore 0 1 Left Port has semaphore token

Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore

Left port writes 1 to semaphore 1 0 Right port obtains semaphore token

Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore

Right port writes 1 to semaphore 0 1 Left port obtains semaphore token

Left port writes 1 to semaphore 1 1 Semaphore-free

Right port writes 0 to semaphore 1 0 Right port has semaphore token

Right port writes 1 to semaphore 1 1 Semaphore free

Left port writes 0 to semaphore 0 1 Left port has semaphore token

Left port writes 1 to semaphore 1 1 Semaphore-free

Notes

10.See Functional Description on page 5 for specific highest memory locations by device.

11. If BUSY

=L, then no change.

12. If BUSY

=L, then no change.

13.See Functional Description on page 5 for specific addresses by device.

[+] Feedback

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *J Page 8 of 19

Maximum Ratings

Exceeding maximum ratings

[14]

may shorten the useful life of the

device. User guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied ............................................–55°C to +125°C

Supply Voltage to Ground Potential............... –0.5V to +4.6V

DC Voltage Applied to

Outputs in High-Z State .........................–0.5V to V

+ 0.5V

DC Input Voltage

[15]

...............................–0.5V to V

+ 0.5V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage.......................................... > 2001V

Latch-up Current.................................................... > 200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 3.3V ±300 mV

Industrial

[16]

–40°C to +85°C 3.3V ±300 mV

Electrical Characteristics

Over the Operating Range

Parameter Description

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV Unit

-20 -25

Min Typ Max Min Typ Max

Output HIGH Voltage (V

=3.3V) 2.4 2.4 V

Output LOW Voltage 0.4 0.4 V

Input HIGH Voltage 2.0 2.0 V

Input LOW Voltage –0.3

[17]

0.8 0.8 V

Output Leakage Current –10 10 –10 10 μA

Input Leakage Current –10 10 –10 10 μA

Operating Current (V

= Max.,

OUT

= 0 mA) Outputs Disabled Com’l. 120 175 115 165 mA

Ind.

[16]

135 185 mA

SB1

Standby Current (Both Ports TTL Level)

& CE

≥V

, f = f

MAX

Com’l. 35 45 30 40 mA

Ind.

[16]

40 50 mA

SB2

Standby Current (One Port TTL Level)

| CE

≥V

, f = f

MAX

Com’l. 75 110 65 95 mA

Ind.

[16]

75 105 mA

SB3

Standby Current (Both Ports CMOS Level)

& CE

≥V

−0.2V, f = 0 Com’l. 10 500 10 500 μA

Ind.

[16]

10 500 μA

SB4

Standby Current (One Port CMOS Level)

| CE

≥V

, f = f

MAX[18]

Com’l. 70 95 60 80 mA

Ind.

[16]

70 90 mA

Capacitance

Parameter

[19]

Description Test Conditions Max Unit

Input Capacitance T

= 25

C, f = 1 MHz,

= 3.3V 10 pF

OUT

Output Capacitance 10 pF

Notes

14.The voltage on any input or IO pin cannot exceed the power pin during power up.

15.Pulse width < 20 ns.

16.Industrial parts are available in CY7C026AV and CY7C036AV only.

17.VIL > –1.5V for pulse width less than 10ns.

18.f

MAX

= 1/t

= All inputs cycling at f = 1/t

(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level

standby I

SB3

19.Tested initially and after any design or process changes that may affect these parameters.

[+] Feedback

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *J Page 9 of 19

Figure 4. AC Test Loads and Waveforms

3.0V

GND 90% 90%

10%

3ns 3ns

10%

ALL INPUTPULSES

(a) Normal Load (Load 1)

R1 = 590Ω

3.3V

OUTPUT

R2 = 435Ω

C= 30pF

=1.4V

OUTPUT

C= 30pF

(b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2)

R1 = 590Ω

R2 = 435Ω

3.3V

OUTPUT

C= 5pF

= 250Ω

≤≤

including scope and jig)

(Used for t

, t

HZWE

, and t

LZWE

Switching Characteristics

Over the Operating Range

[20]

Parameter Description

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV Unit

-20 -25

Min Max Min Max

Read Cycle

Read Cycle Time 20 25 ns

Address to Data Valid 20 25 ns

OHA

Output Hold From Address Change 3 3 ns

ACE[21]

CE LOW to Data Valid 20 25 ns

DOE

OE LOW to Data Valid 12 13 ns

LZOE[22, 23, 24]

OE Low to Low Z 3 3 ns

HZOE[22, 23, 24]

OE HIGH to High Z 12 15 ns

LZCE[22, 23, 24]

CE LOW to Low Z 3 3 ns

HZCE[22, 23, 24]

CE HIGH to High Z 12 15 ns

PU[24]

CE LOW to Power Up 0 0 ns

PD[24]

CE HIGH to Power Down 20 25 ns

ABE[21]

Byte Enable Access Time 20 25 ns

Write Cycle

Write Cycle Time 20 25 ns

SCE[21]

CE LOW to Write End 15 20 ns

Address Valid to Write End 15 20 ns

Address Hold From Write End 0 0 ns

SA[21]

Address Setup to Write Start 0 0 ns

Notes

20.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I

and 30 pF load capacitance.

21.To access RAM, CE= L, UB = L, SEM = H. To access semaphore, CE= H and SEM =L. Either condition must be valid for the entire t

SCE

time.

22.At any given temperature and voltage condition for any given device, t

HZCE

is less than t

LZCE

and t

HZOE

is less than t

LZOE

23.Test conditions used are Load 3.

24.This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.

[+] Feedback

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *J Page 10 of 19

Data Retention Mode

The CY7C024AV/024BV/025AV/026AV and

CY7C0241AV/0251AV/036AV are designed for battery backup.

Data retention voltage and supply current are guaranteed over

temperature. The following rules ensure data retention:

1. Chip Enable (CE) must be held HIGH during data retention,

within V

to V

– 0.2V.

2. CE must be kept between V

– 0.2V and 70 percent of V

during the power up and power down transitions.

3. The RAM can begin operation >t

after V

reaches the

minimum operating voltage (3.0V).

Notes

25.For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.

26.Test conditions used are Load 2.

27.t

BDD

is a calculated parameter and is the greater of t

WDD

– t

PWE

(actual) or t

DDD

– t

(actual).

28.CE = V

, V

= GND to V

, T

= 25°C. This parameter is guaranteed but not tested.

PWE

Write Pulse Width 15 20 ns

Data Setup to Write End 15 15 ns

Data Hold From Write End 0 0 ns

HZWE[23, 24]

R/WLOW to High Z 12 15 ns

LZWE[23, 24]

R/WHIGH to Low Z 3 0 ns

WDD[25]

Write Pulse to Data Delay 45 50 ns

DDD[25]

Write Data Valid to Read Data Valid 30 35 ns

Busy Timing

[26]

BLA

BUSY LOW from Address Match 20 20 ns

BHA

BUSY HIGH from Address Mismatch 20 20 ns

BLC

BUSY LOW from CE LOW 20 20 ns

BHC

BUSY HIGH from CE HIGH 17 17 ns

Port Setup for Priority 5 5 ns

R/W HIGH after BUSY (Slave) 0 0 ns

R/W HIGH after BUSY HIGH (Slave) 15 17 ns

BDD[27]

BUSY HIGH to Data Valid 20 25 ns

Interrupt Timing

[26]

INS

INT Set Time 20 20 ns

INR

INT Reset Time 20 20 ns

Semaphore Timing

SOP

SEM Flag Update Pulse (OEor SEM)1012ns

SWRD

SEM Flag Write to Read Time 5 5 ns

SPS

SEM Flag Contention Window 5 5 ns

SAA

SEM Address Access Time 20 25 ns

Switching Characteristics

Over the Operating Range (continued)

[20]

Parameter Description

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV Unit

-20 -25

Min Max Min Max

Timing

Parameter Test Conditions

[28]

Max Unit

ICC

DR1

at VCC

= 2V 50 μA

Data Retention Mode

3.0V 3.0V

> 2.0V

to V

–0.2V

VIH

[+] Feedback

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