Cypress Semiconductor CYV15G0100EQ Manual de usuario

CYV15G0100EQ

Prosumer Video Cable Equalizer

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-12520 Rev. ** Revised October 25, 2007

Features

■Multi rate adaptive equalization

■Operates from 143 to 1485 Mbps serial data rate

■SMPTE 292M, SMPTE 344M, and SMPTE 259M compliant

■Supports DVB-ASI at 270 Mbps

■Cable length indicator for HD-SDI and SD-SDI data rates

■Maximum cable length adjustment for HD-SDI and SD-SDI

data rates

■Carrier detect and mute functionality for HD-SDI and SD-SDI

data rates

■Equalizer bypass mode

■Seamless connection with HOTLink II™ family

■Equalizes up to 175m of Canare L-5CFB and Belden 1694A

coaxial cable at 270 Mbps

■Equalizes up to 70m of Canare L-5CFB and Belden 1694A

coaxial cable at 1.485 Gbps

■Low power: 160 mW at 3.3V

■Single 3.3V supply

■16-pin SOIC

■0.18 μm CMOS technology

■Pb-free and RoHS compliant

■Uses Cypress CLEANLink™ technology

■Pin compatible to existing equalizer devices

Functional Description

The CYV15G0100EQ is a multi rate adaptive equalizer designed

to equalize and restore signals received over 75Ωcoaxial cable.

The equalizer meets SMPTE 292M, SMPTE 344M, and SMPTE

259M data rates. The CYV15G0100EQ is optimized to equalize

up to 175m of Belden 1694A coaxial cable at 270 Mbps and up

to70mofBelden1694Acoaxialcableat1.485Gbps.Thisdevice

is mainly targeted for Prosumer Video applications where the

cable length requirements are not as stringent as professional

broadcast video applications. The CYV15G0100EQ connects

seamlessly to the HOTLink II family of transceivers.

The CYV15G0100EQ has DC restoration to compensate for the

DC content of the SMPTE pathological patterns. A cable length

indicator (CLI) provides an indication of the cable length

equalized at HD-SDI and SD-SDI data rates. The maximum

cable length adjust (MCLADJ) sets the approximate maximum

cable length to equalize at SD and HD data rates. The

CYV15G0100EQ’s differential serial outputs (SDO, SDO) mute

when the approximate cable length set by MCLADJ is reached.

CD/MUTE is a bidirectional pin that provides an indication of the

signal present at the equalizer inputs. It also controls muting the

outputs of the equalizer at HD and SD data rates.

Power consumption is typically 160 mW at 3.3V.

Serial Links

Copper Cable

CYV15G0100EQ

Prosumer Video

Cable

Equalizer

Connections

Equalizer System Connection Diagram

Cable

Driver

HOTLink II

Serializer

HOTLink II

Deserializer

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CYV15G0100EQ

Document Number: 001-12520 Rev. ** Page 2 of 10

Pinouts

Figure 1. Pin Diagram - 16 Pin SOIC (Top View)

CYV15G0100EQ Prosumer Video Cable Equalizer Block Diagram

Differential Output

Cable Length Analog

Adjustor and Mute

Threshold Block

Carrier Detect and

Mute Control Block

DC Restore

Equalizer

MUTE

BYPASS

SDO, SDO

SDI, SDI

MCLADJ CD

CYV15G0100EQ

VCC

GND

SDO

GND

MCLADJ

BYPASS

CD/MUTE

VCC

GND

SDI

GND

AGC+

AGC-

CLI

16-PIN SOIC Top View

Equalizer Block Diagram

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CYV15G0100EQ

Document Number: 001-12520 Rev. ** Page 3 of 10

Table 1. Pin Descriptions - CYV15G0100EQ Single Channel Cable Equalizer

Name IO Characteristics Signal Description

Control Signals

CLI Analog Output Cable Length Indicator. CLI provides an analog voltage proportional to the equalized

cable length. CLI works at both SD-SDI and HD-SDI data rates.

CD/MUTE LVTTL IO Carrier Detect or Mute Indicator.

Output:

Whentheincomingdatastreamispresentand the cable length does notexceedthelength

that is set by MCLADJ, the CD/MUTE outputs a voltage less than 0.8V.

When the incoming data stream is not present or the cable length exceeds the length that

is set by MCLADJ, the CD/MUTE outputs a voltage greater than 2.8V.

Input:

When the CD/MUTE pin is set LOW, the equalizer’s differential serial outputs are not

muted.

When the CD/MUTE pin is set HIGH, the equalizer’s differential serial outputs are muted.

MCLADJ Analog Input Maximum Cable Length Adjust. The maximum equalized cable length is set by the

voltage applied to the MCLADJ input. When the maximum cable length set by MCLADJ

is reached, CD is driven high and the differential output is muted.

If MCLADJ functionality is not needed, then this pin should be left floating or tied to ground

to allow maximum equalized cable length.

MCLADJ works at both SD and HD data rates.

BYPASS LVTTL Input Equalizer Bypass. When BYPASS is set HIGH, the signal presented at the equalizer’s

differential serial inputs (SDI, SDI) is routed to the equalizer’s differential serial outputs

(SDO, SDO) without equalizing.

When BYPASS is set LOW, the incoming video data stream is equalized and presented

at the equalizer‘s serial differential outputs (SDO, SDO).

In equalizer bypass mode, CD/MUTE is not functional.

AGC± Analog Automatic Gain Control. Place a capacitor of 1 μF between the AGC± pins.

SDO, SDO Differential

Output Differential Serial Outputs. The equalized serial video data stream is presented at the

SDO/SDO differential serial CML output.

SDI, SDI Differential

Input Differential Serial Inputs. SDI/SDI accepts either a single-ended or differential serial

video data stream over 75Ωcoaxial cable.

Power

VCC Power +3.3V Power.

GND Gnd Connect to Ground.

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CYV15G0100EQ

Document Number: 001-12520 Rev. ** Page 4 of 10

Equalizer Operation

The CYV15G0100EQ is a high speed adaptive cable equalizer

designed to equalize standard definition (SD) and high definition

(HD) serial digital interface (SDI) video data streams. The

CYV15G0100EQ equalizer is optimized to equalize up to 175m

of Canare L-5CFB and Belden 1694A cable at 270 Mbps and up

to 70m of Canare L-5CFB and Belden 1694A cable at 1.485

Gbps. The CYV15G0100EQ equalizer contains one power

supply and typically consumes 160 mW power at 3.3V. The multi

rate equalizer meets the SMPTE 259M, SMPTE 292M, SMPTE

344M, and DVB-ASI video standards. It meets all pathological

requirements for SMPTE 292M as defined by RP198 and for

SMPTE 259M as defined by RP178. The CYV15G0100EQ

Prosumer video cable equalizer is auto adaptive from 143 Mbps

to 1.485 Gbps.

The CYV15G0100EQ equalizer has variable gain and multiple

equalization stages that reverse the effects of the cable. This

equalization is achieved by separate regulation of the lower and

higher frequency components in the signal to give a clean output

eye diagram. The CYV15G0100EQ has DC restoration for

compensating the DC content of the SMPTE pathological

patterns.

SDI, SDI

The CYV15G0100EQ accepts single-ended or differential serial

video data streams over 75Ωcoaxial cable. It is recommended

to AC couple the SDI and SDI inputs as theyare internally biased

to 1.2V.

SDO, SDO

The CYV15G0100EQ has differential serial output interface

drivers that use current mode logic (CML) drivers to provide

source matching for the transmission line. These outputs are

either AC coupled or DC coupled to the HOTLink II SerDes

device.

CLI

Cable Length Indicator (CLI) is an analog output that gives an

output voltage proportional to the equalized cable length. CLI

gives an approximation of the length of cable at the differential

serial inputs (SDI, SDI). CLI works at high definition (HD) data

rates and standard definition (SD) data rates. The graph in

Figure 3 on page 7 illustrates the CLI output voltage at various

Belden 1694A cable lengths. With an increase in cable length,

CLI output voltage decreases.

MCLADJ

Maximum Cable Length Adjust (MCLADJ) sets the approximate

maximum amount of cable to be equalized. MCLADJ works at

SD and HD data rates.

If the MCLADJ voltage is greater than the CLI output voltage, the

CDpin is driven HIGH and the outputs are muted. If the MCLADJ

voltage is less than CLI voltage, then the equalizer’s CD pin is

driven LOW and the incoming data stream is equalized. The

graph in Figure 2 on page 7 illustrates the voltage required at

MCLADJ input to equalize various Belden 1694A cable lengths

for SD and HD data rates.

If MCLADJ functionality is not needed, then this pin should be left

floating or tied to ground to allow maximum equalized cable

length.

CD/MUTE

Carrier Detect/MUTE (CD/MUTE) is a bidirectional pin that

provides an indication of the signal present at the equalizer’s

input or it controls the muting of the equalizer’s output. The

(CD/MUTE) operates for both HD and SD data rates.

If CD/MUTE is used as an output and the incoming data stream

is not present or the cable length exceeds the length that is set

by MCLADJ, the voltage at the CD/MUTE output is greater than

2.8V.IfCD/MUTEis used as an output,theincomingdatastream

is present and the cable length does not exceed the length that

is set by MCLADJ, then the voltage at the CD/MUTE output is

less than 0.8V.

If CD/MUTE is used as an input and is set LOW, the equalizer

serial outputs are not muted. If the CD/MUTE is used as an input

and is set HIGH, then the equalizer serial outputs are muted.

When an invalid signal or a signal transmitted with a launch

amplitude of less than 500 mV at HD data rates is received, the

equalizer’s serial outputs are muted.

BYPASS

The CYV15G0100EQ has a bypass mode that enables the user

to bypass the equalizer’s equalization and DC restoration

functions. When the bypass mode is set HIGH, the signal

presented at the equalizer’s differential serial inputs (SDI, SDI)

is routed to the equalizer’s differential serial outputs (SDO, SDO)

without equalizing.

When BYPASS is set LOW, the incoming video data stream is

equalized and presented at the equalizer‘s differential serial

outputs (SDO, SDO).

In equalizer bypass mode, CD/MUTE is not functional.

AGC

Place a capacitor of 1 μF between the AGC± pins of the

CYV15G0100EQ equalizer.

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CYV15G0100EQ

Document Number: 001-12520 Rev. ** Page 5 of 10

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Storage Temperature.................................. –65°C to +150°C

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Supply Voltage to Ground Potential................–0.5V to +3.8V

DC Voltage Applied to Outputs

in High Z State.......................................–0.5V to VCC + 0.5V

DC Input Voltage .....................................–0.5V to VCC+0.5V

Electro Static Discharge (ESD) HBM.......................> 2000 V

(JEDEC EIA/JESD-A114A)

Latch Up Current....................................................> 200 mA

Power Up Requirements

The CYV15G0100EQ contains one power supply. The voltage

on any input or IO pin must not exceed the power pin during

power up.

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C +3.3V ±5%

DC Electrical Characteristics

Parameter Description Test Conditions Min Typ Max Unit

VCC Supply Voltage[1] –3.135 3.3 3.465 V

PDPower Consumption[2] –125 160 190 mW

ISSupply Current[1] –38 48 60 mA

VCMOUT Output Common Mode Voltage[1] Load = 50Ω– VCC–ΔVSDO/2

= 2.9 – V

VCMIN Input Common Mode Voltage[1]

(Bypass = High) – 1 1.4 V

Input Common Mode Voltage[1]

(Bypass = Low) – 0 2.9 V

–CLI DC Voltage (0m)[1] –2.2 2.65 2.95 V

–CLI DC Voltage (No Signal)[1] –1.5 1.9 2.3 V

–Floating MCLADJ DC Voltage[1] –1.3 V

–MCLADJ Range[3] –0.4 0.72 1.02 V

VCD/MUTE(OH) CD/MUTE Output Voltage[1] Carrier Not Present 2.8 – – V

VCD/MUTE(OL) Carrier Present – – 0.8 V

VCD/MUTE CD/MUTE Input Voltage Required to

Force Outputs to Mute[1] Min to Mute 2.5 – – V

VCD/MUTE CD/MUTE Input Voltage Required to

Force Active[1] Max to Activate – – 1 V

Notes

1. Production test.

2. Calculated results from production test.

3. Not tested. Based on characterization.

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CYV15G0100EQ

Document Number: 001-12520 Rev. ** Page 6 of 10

AC Electrical Characteristics

Parameter Description Test Conditions Min Typ Max Unit

–Serial Input Data Rate[1] –143 –1485 Mbps

VSDI Input Voltage Swing Single-ended, at the transmitter,

HD data rate 500[5] 1200 mV

VSDI Input Voltage Swing Single-ended, at the transmitter,

SD data rate 500[6] 1200 mV

ΔVSDO Output Voltage Swing[1] Differentialp-p, 50Ω load 450 700 950 mV

–Output Jitter for Various Cable

Lengths and Data Rates 270 Mbps

Belden 1694A: 0-175m

Canare L-5CFB: 0-175m

800 mV transmit amplitude

Equalizer pathological pattern

–0.2[1] –UI

1.485 Gbps

Belden 1694A: 0-70m

Canare L-5CFB: 0-70m

800 mV transmit amplitude

Equalizer pathological pattern

–0.25[1] –UI

–Output Rise/Fall Time[3, 4] 20% - 80%, HD data rate 80 120 220 ps

–Output Rise/Fall Time[3, 4] 20% - 80%, SD data rate 80 120 350 ps

–Mismatch in Rise/Fall Time[3, 4] – – – 30 ps

–Duty Cycle Distortion[3, 4] HD color bar pattern –20 –ps

–Overshoot[3, 4] – – – 10 %

–Input Return Loss[3] –-15 – – dB

–Input Resistance[3, 4] Single-ended –2.5 – kΩ

–Input Capacitance[3, 4] Single-ended – 1 – pF

–Output Resistance[3, 4] Single-ended –50 –Ω

Notes

4. Not tested. Guaranteed by design simulations.

5. Based on characterization across temperature and voltage with 70m of Belden 1694A cable, transmitting SMPTE Equalizer Pathological Test Pattern.

6. Based on characterization across temperature and voltage with 175m of Belden 1694A cable, transmitting SMPTE Equalizer Pathological Test Pattern.

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CYV15G0100EQ

Document Number: 001-12520 Rev. ** Page 7 of 10

Typical Performance Graphs

(Unless otherwise stated, VCC = 3.3V, TA = 25°C)

Figure 2. MCLADJ Input Voltage vs Belden 1694A Cable Length at SD-SDI and HD-SDI Data Rates

Figure 3. CLI Output Voltage Vs Belden 1694A Cable Length at SD-SDI and HD-SDI Data Rates

2.3

2.35

2.4

2.45

2.5

2.55

2.6

2.65

2.7

0 25 50 75 100 125 150 175

CABLE LENGTH (m)

VOLTAGE (V)

2.3

2.35

2.4

2.45

2.5

2.55

2.6

2.65

2.7

0 25 50 75 100 125 150 175

CABLE LENGTH (m)

VOLTAGE (V)

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CYV15G0100EQ

Document Number: 001-12520 Rev. ** Page 8 of 10

Typical Application Circuit

Figure 4. Interfacing CYV15G0100EQ to the HOTLink II SerDes

CLI

VCC

VEE

SDI

VEE

AGC+

AGC

−

BYPASS

MCLADJ

VEE

SDO

VEE

VCC

CYV15G0100EQ

+3.3V

0.01 μF0. 01 μF

+1 μF

RXLE

SDASEL

LPEN

INSEL

IN1+

IN1

−

FRAMCHAR

RFEN

RFMODE

DECMODE

RXCKSEL

RXMODE

RXRATE

RXCLKC+

RXCLK

−

RXCLK+

RXST0

RXST1

RXST2

RXOP

RXD0

RXD1

RXD2

RXD3

RXD4

RXD5

RXD6

RXD7

LFI

CYV15G0101DXB

BNC JACK

6.4n H

1 μF

C10

C11

C12

C15

C16

R15 R14

R16

75Ω

2 Z0

R18

CL I

75 Ω

37.4 Ω

CD/ MUT E

MC L A D J

CD/MUTE

1 μF

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CYV15G0100EQ

Document Number: 001-12520 Rev. ** Page 9 of 10

Ordering Information

Ordering Code Package Name Package Type Operating

Range

CYV15G0100EQ-SXC SZ16.15 Pb-free 16-Pin 150 Mil SOIC 0 to 70°C

Package Dimension

Figure 5. 16-Pin (150 Mil) SOIC S16.15

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Document Number: 001-12520 Rev. ** Revised October 25, 2007 Page 10 of 10

PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered

trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the

Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. HOTLink II is a trademark of Cypress

Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. All products and company names mentioned in this document may

be the trademarks of their respective holders.

CYV15G0100EQ

circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,

life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical

components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only inconjunction with a Cypress

integrated circuit as specified inthe applicable agreement. Any reproduction, modification, translation, compilation, or representation ofthis Source Codeexcept as specifiedabove is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document History Page

Document Title: CYV15G0100EQ Prosumer Video Cable Equalizer

Document Number: 001-12520

REV. ECN NO. ISSUE

DATE ORIG. OF

CHANGE DESCRIPTION OF CHANGE

** 1396423 SEE ECN UKK/AESA New datasheet

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