Xilinx VC707 Manual de usuario

April 2015

VC707 Built-In Self Test Flash

Application

XTP205

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Revision History

Date Version Description

04/30/14 12.0 Recompiled for 2015.1.

11/24/14 11.0 Recompiled for 2014.4. Fixed AR62666.

10/08/14 10.0 Recompiled for 2014.3. Added AR62666.

06/09/14 9.0 Recompiled for 2014.2.

04/16/14 8.0 Recompiled for 2014.1.

12/18/13 7.0 Recompiled for 2013.4.

10/23/13 6.0 Recompiled for 2013.3. Converted to IPI, added SGMII interface and LwIP.

06/19/13 5.0 Recompiled for 2013.2. AR55939, AR55738, AR55531, and AR55431 fixed.

04/03/13 4.0 Recompiled for 2013.1. Added AR55939, AR55738, AR55531, and AR55431.

02/22/13 3.1 Added AR53420.

12/18/12 3.0 Recompiled for 2012.4.

10/23/12 2.0 Recompiled for 2012.3. AR51180 fixed.

09/20/12 1.0 Initial version for 2012.2. Added AR51180. Added AR51758.

Overview

Xilinx VC707 Board

Software Requirements

VC707 Setup

VC707 BIST (Built-In Self Test)

Run the USB Design

Compile VC707 BIST Design

Program VC707 with BIST Design

Run the USB2 Design

Run the LwIP Ethernet Design

References

Note: This presentation applies to the VC707

VC707 BIST Design Description

Description

–The Built-In System Test (BIST) application uses an IPI MicroBlaze system to

verify board functionality. A UART based terminal program interface offers

users a menu of tests to run.

Block Design Source

–VC707 BIST Design Files (2015.1 C) ZIP file

–Available through http://www.xilinx.com/vc707

Note: Presentation applies to the VC707

VC707 BIST Design Description

Block Design IP

–Processor and Subsystems: MicroBlaze, MicroBlaze Debug Module (MDM),

Local Memory Bus, LMB BRAM Controller, Block Memory Generator, Proc Sys

Reset, AXI Interrupt Controller

–AXI Bus: AXI Interconnect, AXI Timer

–Memory: AXI BRAM Controller, MIG 7 Series, AXI DMA

–Peripherals: AXI USB2, AXI Ethernet, AXI EMC, AXI IIC, AXI GPIO, AXI UART

16550, XADC Wizard

–Other IP: Constant, Concat, gte2_top

•Vivado Design Suite Tcl Command Reference Guide (UG835)

•Designing IP Subsystems Using IP Integrator (UG994)

Note: Presentation applies to the VC707

Xilinx VC707 Board

Vivado Software Requirements

Xilinx Vivado Design Suite 2015.1, Design Edition + SDK

–Combined installer

Note: Presentation applies to the VC707

VC707 Setup

Connect a USB Type-A to Mini-B cable to the USB

UART connector on the VC707 board

–Connect this cable to your PC

VC707 Setup

Connect a USB Type-A to Micro-B cable to the USB

JTAG (Digilent) connector on the VC707 board

–Connect this cable to your PC

–Power on the VC707 board for UART Drivers Installation

VC707 Setup

Install USB UART Drivers

–Refer to UG1033 for details on installing the USB to UART Drivers

Note: Presentation applies to the VC707

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