Xilinx KCU105 Manual de usuario
KCU105 PCI Express
Control Plane TRD
User Guide
KUCon-TRD01
Vivado Design Suite
UG918 (v2017.2) July 18, 2017
PCI Express Control Plane TRD www.xilinx.com 2
UG918 (v2017.2) July 18, 2017
Revision History
The following table shows the revision history for this document.
Date Version Revision
07/18/2017 2017.2 Released with Vivado Design Suite 2017.2 with no changes from previous
version.
07/17/2017 2017.1 Released with Vivado Design Suite 2017.1. Updated Figure 3-2 through
Figure 3-5 and Figure 4-1 through Figure 4-6. Updated commands in Run the
Design in Chapter 3, step 2.
02/14/2017 2016.4 Released with Vivado Design Suite 2016.4 with no changes from previous
version.
10/05/2016 2016.3 Released with Vivado Design Suite 2016.3 with no changes from previous
version.
06/08/2016 2016.2 Released with Vivado Design Suite 2016.2 with no changes from previous
version.
04/14/2016 2016.1 Released with Vivado Design Suite 2016.1 with no changes from previous
version.
11/24/2015 2015.4 Released with Vivado Design Suite 2015.4 with no changes from previous
version.
10/05/2015 2015.3 Released with Vivado Design Suite 2015.3 with minor textual edits.
06/30/2015 2015.2 Released with Vivado Design Suite 2015.2 with no changes from previous
version.
05/05/2015 2015.1 Updated for Vivado Design Suite 2015.1. TRD ZIP file changed to
rdf0305-kcu105-trd01-2015-1.zip. Updated Information about resource
utilization for the base design and the user extension design in Tab l e 1 -1 and
Tabl e 1 -2. Added information about Windows 7 driver support of the reference
design, updating these: sections: Features, Computers, Software, and
Appendix A, Directory Structure. Updated Figure 5-3, Figure A-1, and Table A - 1
to include Windows information. The section Install TRD Drivers on the Host
Computer (Windows 7) was added to Chapter 2, Setup. The section Using the
QuestaSim/ModelSim Simulator was removed from Chapter 4, Implementing
and Simulating the Design, because QuestaSim simulation is not supported in
Vivado tool release 2015.1.
02/26/2015 2014.4.1 Initial Xilinx release.
Send Feedback
PCI Express Control Plane TRD www.xilinx.com 3
UG918 (v2017.2) July 18, 2017
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Introduction
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2: Setup
Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Preliminary Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 3: Bringing Up the Design
Set the Host System to Boot from the LiveDVD (Linux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Configure the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Run the Design on the Host Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Test the Reference Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Remove Drivers from the Host Computer
(Windows Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 4: Implementing and Simulating the Design
Implementing the Base Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Implementing the User Extension Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Simulating the Base Design Using Vivado Simulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Chapter 5: Targeted Reference Design Details and Modifications
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Reference Design Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Send Feedback
PCI Express Control Plane TRD www.xilinx.com 4
UG918 (v2017.2) July 18, 2017
Appendix A: Directory Structure
Appendix B: Recommended Practices and Troubleshooting in Windows
Recommended Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Send Feedback
PCI Express Control Plane TRD www.xilinx.com 5
UG918 (v2017.2) July 18, 2017
Chapter 1
Introduction
This document describes the features and functions of the PCI Express® Control Plane
targeted reference design (TRD). The TRD comprises a base design and a user extension
design. The user extension design adds custom logic on top of the base design. The
pre-built user extension design in this TRD adds another AXI block RAM controller to the
design and sets up ingress translations through BAR4 to access this memory space.
Overview
The TRD targets the Kintex® UltraScale™ XCKU040-2FFVA1156E FPGA running on the
KCU105 evaluation board. It demonstrates a control plane application using a PCI Express
Endpoint block in a x1 Gen1 configuration. Simple base address register (BAR)-mapped
read and write transactions are demonstrated using a kernel mode software driver
controlled by the Control & Monitoring graphical user interface (GUI). The top-level block
diagram of the TRD is shown in Figure 1-1.
X-Ref Target - Figure 1-1
Figure 1-1: KCU105 PCI Express Control Plane Targeted Reference Design
352&(6625
5RRW
&RPSOH[
$;,3&,H
%ULGJH
$;,6ODYH
$;,0DVWHU
3&,H
'ULYHU
.HUQHO
VSDFH
3&,H
[*HQ
/LQN 397021
5HJLVWHUV
3)%$5
6<6021
ELWVDW
0+]
*8,
*
7
+
,QWHJUDWHG3&,H%ORFN
3&,H,3
:UDSSHU
,QWHJUDWHGEORFNRQ)3*$
;LOLQ[LQKRXVH,3
&XVWRPORJLFLQ)3*$
6RIWZDUHUXQQLQJRQ
KRVWFRPSXWHU &RPSRQHQWRQKRVWFRPSXWHU
7KLUGSDUW\,3DQG)3*$
$;,,QWHUFRQQHFW
UG918_c1_01_021315
$;,%ORFN5$0
3)%$5
XCKU040-2FFVA1156E FPGA
KCU105 Evaluation Board
+RVW&RPSXWHU
Send Feedback
PCI Express Control Plane TRD www.xilinx.com 6
UG918 (v2017.2) July 18, 2017
Chapter 1: Introduction
An Expresso DMA Bridge Core from Northwest Logic (NWL) [Ref 1] is used to demonstrate
PCIe-to-AXI conversion of transactions. The downstream slaves include a power, voltage,
and temperature (PVT) module monitoring parameters from the FPGA system monitor and
AXI block RAM IP targeted to BARs.
Features
The TRD includes these features:
• PCIe x1 Gen1 Endpoint operating at 2.5 GigaTransfers per second (GT/s) per
lane/direction
°Single physical function with support for three 64-bit BARs
• DMA Bridge IP Core
°Ingress address translation capability
°AXI3 interface
• 64-bit kernel space drivers for Linux and Windows 7, which run on the host computer
• Control and monitoring graphical user interface (GUI)
Resource Utilization
Tabl e 1-1 and Table 1- 2 list the resources used by the base and user extension designs after
synthesis. Place and route can alter these numbers based on placements and routing paths.
These numbers are to be used as a rough estimate of resource utilization. These numbers
might vary based on the version of the TRD and the tools used to regenerate the design.
Table 1-1: Base Design Resource Utilization
Resource Type Available Used Usage (%)
CLB registers 484,800 43,896 9.05
CLB LUT 242,400 27,431 11.32
Block RAM 600 22 3.66
MMCME3_ADV 10 1 10
Global Clock Buffers 240 3 1.25
BUFG_GT 120 5 4.17
SYSMONE1 1 1 100
IOB 520 16 3.08
Send Feedback
PCI Express Control Plane TRD www.xilinx.com 7
UG918 (v2017.2) July 18, 2017
Chapter 1: Introduction
GTHE3_CHANNEL 20 1 5
GTHE3_COMMON 5 0 0
Table 1-2: User Extension Design Resource Utilization
Resource Type Available Used Usage (%)
CLB Registers 484,800 44,395 9.16
CLB LUTs 242,400 27,817 11.48
Block RAM 600 24 4
MMCME3_ADV 10 1 10
Global Clock Buffers 240 3 1.25
BUFG_GT 120 5 4.17
SYSMONE1 1 1 100
IOB 520 16 3.08
GTHE3_CHANNEL 20 1 5
GTHE3_COMMON 5 0 0
Table 1-1: Base Design Resource Utilization (Cont’d)
Resource Type Available Used Usage (%)
Send Feedback
PCI Express Control Plane TRD www.xilinx.com 8
UG918 (v2017.2) July 18, 2017
Chapter 2
Setup
This chapter identifies the hardware and software requirements, and the preliminary setup
procedures required prior to bringing up the targeted reference design.
Requirements
Hardware
Board and Peripherals
• KCU105 board with the Kintex® UltraScale™ XCKU040-2FFVA1156E FPGA
• USB cable, standard-A plug to micro-B plug (Digilent cable)
• Power supply: 100 VAC–240 VAC input, 12 VDC 5.0A output
• ATX power supply
• ATX power supply adapter
Computers
A control computer is required to run the Vivado® Design Suite and confige the on-board
FPGA. It can be a laptop or desktop computer with any operating system supported by
Vivado tools, such as Redhat Linux or Microsoft® Windows 7.
The reference design test configuration requires a host computer comprised of the chassis,
containing a motherboard with a PCI Express slot, monitor, keyboard, and mouse. A DVD
drive is also required if a Linux operating system is used. If a Windows 7 operating system
is used, the 64-bit Windows 7 OS and the Java SE Development Kit 7 must be installed.
Software
Vivado Design Suite 2017.2 is required. The Fedora 20 LiveDVD, on which the TRD software
and GUI run, is only required if a Linux operating system is used.
Send Feedback
PCI Express Control Plane TRD www.xilinx.com 9
UG918 (v2017.2) July 18, 2017
Chapter 2: Setup
Preliminary Setup
Complete these tasks before bringing up the design.
Install the Vivado Design Suite
Install Vivado Design Suite 2017.2 on the control computer. Follow the installation
instructions provided in Vivado Design Suite User Guide Release Notes, Installation, and
Licensing (UG973) [Ref 2].
Download the Targeted Reference Design Files
1. Download rdf0305-kcu105-trd01-2017-2.zip from the Xilinx Kintex UltraScale
FPGA KCU105 Evaluation Kit - Documentation & Designs website. This ZIP file contains
the hardware design, software drivers, and application GUI executables.
2. Extract the contents of the file to a working directory.
3. The extracted contents are located at <working_dir>/kcu105_control_plane.
The TRD directory structure is described in Appendix A, Directory Structure.
Install TRD Drivers on the Host Computer (Windows 7)
Note: This section provides steps to install KUCon-TRD drivers and is only applicable to a host
computer running Windows 7 64-bit OS. If running Linux, proceed to Set DIP Switches, page 11.
This section includes steps to set up and install KUCon-TRD drivers in a host computer
running the Windows 7 64-bit OS.
Disable Driver Signature Enforcement
Note: Windows only allows drivers with valid signatures obtained from trusted certificate
authorities to load in Windows 7 64-bit OS. Windows drivers provided for this reference design do
not have a valid signature. Therefore, you have to disable driver signature enforcement on the host
computer, as follows:
1. Power up the host system. Press F8 to go to the Advanced Boot Options menu.
2. Select the Disable Driver Signature Enforcement option as shown in Figure 2-1, and
press Enter.
Send Feedback
PCI Express Control Plane TRD www.xilinx.com 10
UG918 (v2017.2) July 18, 2017
Chapter 2: Setup
X-Ref Target - Figure 2-1
Figure 2-1: Disable Driver Signature Enforcement
UG918_c2_01_040315
Send Feedback
Otros manuales para KCU105
5
Tabla de contenidos
Otros manuales de Placa madre de Xilinx
Xilinx
Xilinx EZTag Manual de usuario
Xilinx
Xilinx ZC702 Manual de usuario
Xilinx
Xilinx ZC706 Manual de usuario
Xilinx
Xilinx Artix-7 FPGA AC701 Manual de usuario
Xilinx
Xilinx Zynq-7000 Instrucciones de instalación y funcionamiento
Xilinx
Xilinx SP601 Manual de usuario
Xilinx
Xilinx ML40 Series Manual de usuario
Xilinx
Xilinx ML605 Manual de instalación
Xilinx
Xilinx KC705 Manual de usuario
Xilinx
Xilinx SP605 Manual de instalación
Xilinx
Xilinx VCU118 Manual de usuario
Xilinx
Xilinx ML310 Manual de usuario
Xilinx
Xilinx SP605 Manual de usuario
Xilinx
Xilinx ML507 Manual de usuario
Xilinx
Xilinx ML310 Manual de usuario
Xilinx
Xilinx ML501MicroBlaze Manual del operador
Xilinx
Xilinx Virtex-4 ML461 Manual de usuario
Xilinx
Xilinx ML40 Series Manual de usuario
Xilinx
Xilinx ZCU106 Manual de usuario
Xilinx
Xilinx Spartan-3A DSP FPGA Series Manual de uso y cuidado
Manuales populares de Placa madre de otras marcas
Telit Wireless Solutions
Telit Wireless Solutions SL869-3DR Manual de usuario
Gigabyte
Gigabyte GA-9IVDT Manual de usuario
Texas Instruments
Texas Instruments ADS8372EVM Manual de usuario
Commell
Commell MS-C73 Manual de usuario
IBT Technologies
IBT Technologies MB860 Manual de usuario
Nvidia
Nvidia TEGRA DG-04927-001_V01 Manual de usuario
