Freescale Semiconductor MPC8260 PowerQUICC II Family Manual de usuario

MPC8260 PowerQUICC™ II

Family Reference Manual

Supports

MPC8250

MPC8255

MPC8260

MPC8264

MPC8265

MPC8266

MPC8260RM

Rev. 2, 12/2005

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Document Number: MPC8260RM

Rev. 2, 12/2005

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Part I—Overview I

Overview 1

G2 Core 2

Memory Map 3

Part II—Configuration and Reset II

System Interface Unit (SIU) 4

Reset 5

Part III—The Hardware Interface III

External Signals 6

60x Signals 7

The 60x Bus 8

PCI Bridge 9

Clocks and Power Control 10

Memory Controller 11

Secondary (L2) Cache Support 12

IEEE 1149.1 Test Access Port 13

Part IV—Communications Processor Module IV

Communications Processor Module Overview 14

Serial Interface with Time-Slot Assigner 15

CPM Multiplexing 16

Baud-Rate Generators (BRGs) 17

Timers 18

SDMA Channels and IDMA Emulation 19

Serial Communications Controllers (SCCs) 20

SCC UART Mode 21

SCC HDLC Mode 22

SCC BISYNC Mode 23

SCC Transparent Mode 24

SCC Ethernet Mode 25

SCC AppleTalk Mode 26

Serial Management Controllers (SMCs) 27

Multi-Channel Controllers (MCCs) 28

Fast Communications Controllers (FCCs) 29

ATM Controller and AAL0, AAL1, and AAL5 30

ATM AAL1 Circuit Emulation Service 31

ATM AAL2 32

Inverse Multiplexing for ATM (IMA) 33

ATM Transmission Convergence Layer 34

I Part I—Overview

1Overview

2G2 Core

3Memory Map

II Part II—Configuration and Reset

4System Interface Unit (SIU)

5Reset

III Part III—The Hardware Interface

6External Signals

760x Signals

8The 60x Bus

9PCI Bridge

10 Clocks and Power Control

11 Memory Controller

12 Secondary (L2) Cache Support

13 IEEE 1149.1 Test Access Port

IV Part IV—Communications Processor Module

14 Communications Processor Module Overview

15 Serial Interface with Time-Slot Assigner

16 CPM Multiplexing

17 Baud-Rate Generators (BRGs)

18 Timers

19 SDMA Channels and IDMA Emulation

20 Serial Communications Controllers (SCCs)

21 SCC UART Mode

22 SCC HDLC Mode

23 SCC BISYNC Mode

24 SCC Transparent Mode

25 SCC Ethernet Mode

26 SCC AppleTalk Mode

27 Serial Management Controllers (SMCs)

28 Multi-Channel Controllers (MCCs)

29 Fast Communications Controllers (FCCs)

30 ATM Controller and AAL0, AAL1, and AAL5

31 ATM AAL1 Circuit Emulation Service

32 AT M A A L 2

33 Inverse Multiplexing for ATM (IMA)

34 ATM Transmission Convergence Layer

Fast Ethernet Controller 35

FCC HDLC Controller 36

FCC Transparent Controller 37

Serial Peripheral Interface (SPI) 38

I2C Controller 39

Parallel I/O Ports 40

Reference Manual (Rev 1) Errata B

Glossary of Terms and Abbreviations GLO

Index IND

35 Fast Ethernet Controller

36 FCC HDLC Controller

37 FCC Transparent Controller

38 Serial Peripheral Interface (SPI)

39 I2C Controller

40 Parallel I/O Ports

ARegister Quick Reference Guide

BReference Manual (Rev 1) Errata

GLO Glossary of Terms and Abbreviations

IND Index

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

Freescale Semiconductor v

Contents

Paragraph

Number Title

Page

Number

About This Book

Reference Manual Revision History............................................................................ lxxvii

Before Using this Manual—Important Note ................................................................ lxxix

Audience....................................................................................................................... lxxix

Organization.................................................................................................................. lxxix

Suggested Reading....................................................................................................... lxxxii

Conventions ................................................................................................................lxxxiii

Acronyms and Abbreviations .....................................................................................lxxxiii

PowerPC Architecture Terminology Conventions...................................................... lxxxvi

Chapter 1

Overview

1.1 Features............................................................................................................................1-1

1.2 Architecture Overview..................................................................................................... 1-6

1.2.1 G2 Core........................................................................................................................1-7

1.2.2 System Interface Unit (SIU)........................................................................................ 1-8

1.2.3 Communications Processor Module (CPM)................................................................ 1-9

1.3 Software Compatibility Issues......................................................................................... 1-9

1.3.1 Signals........................................................................................................................1-10

1.4 Differences between MPC860 and PowerQUICC II.....................................................1-12

1.5 Serial Protocol Table...................................................................................................... 1-12

1.6 PowerQUICC II Configurations.................................................................................... 1-13

1.6.1 Pin Configurations..................................................................................................... 1-13

1.6.2 Serial Performance..................................................................................................... 1-13

1.7 Application Examples.................................................................................................... 1-14

1.7.1 Communication Systems ........................................................................................... 1-14

1.7.1.1 Remote Access Server........................................................................................... 1-14

1.7.1.2 Regional Office Router.......................................................................................... 1-16

1.7.1.3 LAN-to-WAN Bridge Router ................................................................................ 1-16

1.7.1.4 Cellular Base Station ............................................................................................. 1-17

1.7.1.5 Telecommunications Switch Controller ................................................................ 1-18

1.7.1.6 SONET Transmission Controller........................................................................... 1-18

1.7.2 Bus Configurations .................................................................................................... 1-19

1.7.2.1 Basic System.......................................................................................................... 1-19

1.7.2.2 High-Performance Communication....................................................................... 1-20

1.7.2.3 High-Performance System Microprocessor........................................................... 1-21

1.7.2.4 PCI......................................................................................................................... 1-21

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

vi Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

1.7.2.5 PCI with 155-Mbps ATM...................................................................................... 1-22

1.7.2.6 PowerQUICC II as PCI Agent............................................................................... 1-23

Chapter 2

G2 Core

2.1 Overview.......................................................................................................................... 2-1

2.2 G2 Processor Core Features ............................................................................................ 2-3

2.2.1 Instruction Unit............................................................................................................ 2-5

2.2.2 Instruction Queue and Dispatch Unit........................................................................... 2-5

2.2.3 Branch Processing Unit (BPU).................................................................................... 2-5

2.2.4 Independent Execution Units....................................................................................... 2-6

2.2.4.1 Integer Unit (IU)...................................................................................................... 2-6

2.2.4.2 Floating-Point Unit (FPU)....................................................................................... 2-6

2.2.4.3 Load/Store Unit (LSU) ............................................................................................ 2-6

2.2.4.4 System Register Unit (SRU).................................................................................... 2-7

2.2.5 Completion Unit .......................................................................................................... 2-7

2.2.6 Memory Subsystem Support........................................................................................2-7

2.2.6.1 Memory Management Units (MMUs)..................................................................... 2-7

2.2.6.2 Cache Units..............................................................................................................2-8

2.3 Programming Model........................................................................................................ 2-8

2.3.1 Register Set.................................................................................................................. 2-8

2.3.1.1 PowerPC Register Set.............................................................................................. 2-9

2.3.1.2 PowerQUICC II-Specific Registers....................................................................... 2-11

2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0) ................................ 2-11

2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1) ................................ 2-14

2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2) ................................ 2-14

2.3.1.2.4 Processor Version Register (PVR)..................................................................... 2-15

2.3.2 PowerPC Instruction Set and Addressing Modes......................................................2-15

2.3.2.1 Calculating Effective Addresses............................................................................ 2-15

2.3.2.2 PowerPC Instruction Set........................................................................................ 2-16

2.3.2.3 PowerQUICC II Implementation-Specific Instruction Set.................................... 2-17

2.4 Cache Implementation................................................................................................... 2-17

2.4.1 PowerPC Cache Model.............................................................................................. 2-18

2.4.2 PowerQUICC II Implementation-Specific Cache Implementation...........................2-18

2.4.2.1 Data Cache............................................................................................................. 2-18

2.4.2.2 Instruction Cache................................................................................................... 2-20

2.4.2.3 Cache Locking....................................................................................................... 2-20

2.4.2.3.1 Entire Cache Locking ........................................................................................ 2-20

2.4.2.3.2 Way Locking...................................................................................................... 2-20

2.5 Exception Model............................................................................................................2-21

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

Freescale Semiconductor vii

Contents

Paragraph

Number Title

Page

Number

2.5.1 PowerPC Exception Model........................................................................................ 2-21

2.5.2 PowerQUICC II Implementation-Specific Exception Model....................................2-22

2.5.3 Exception Priorities.................................................................................................... 2-25

2.6 Memory Management.................................................................................................... 2-25

2.6.1 PowerPC MMU Model.............................................................................................. 2-25

2.6.2 PowerQUICC II Implementation-Specific MMU Features.......................................2-26

2.7 Instruction Timing.......................................................................................................... 2-27

2.8 Differences between the PowerQUICC II’s G2 Core and the

MPC603e Microprocessor......................................................................................... 2-28

Chapter 3

Memory Map

Chapter 4

System Interface Unit (SIU)

4.1 System Configuration and Protection.............................................................................. 4-2

4.1.1 Bus Monitor................................................................................................................. 4-3

4.1.2 Timers Clock................................................................................................................4-3

4.1.3 Time Counter (TMCNT).............................................................................................. 4-4

4.1.4 Periodic Interrupt Timer (PIT)..................................................................................... 4-5

4.1.5 Software Watchdog Timer ........................................................................................... 4-6

4.2 Interrupt Controller.......................................................................................................... 4-7

4.2.1 Interrupt Configuration................................................................................................ 4-8

4.2.1.1 Machine Check Interrupt......................................................................................... 4-9

4.2.1.2 INT Interrupt............................................................................................................4-9

4.2.2 Interrupt Source Priorities............................................................................................ 4-9

4.2.2.1 SCC, FCC, and MCC Relative Priority................................................................. 4-12

4.2.2.2 PIT, TMCNT, PCI, and IRQ Relative Priority ...................................................... 4-13

4.2.2.3 Highest Priority Interrupt....................................................................................... 4-13

4.2.3 Masking Interrupt Sources......................................................................................... 4-13

4.2.4 Interrupt Vector Generation and Calculation............................................................. 4-14

4.2.4.1 Port C External Interrupts...................................................................................... 4-16

4.3 Programming Model...................................................................................................... 4-17

4.3.1 Interrupt Controller Registers.................................................................................... 4-17

4.3.1.1 SIU Interrupt Configuration Register (SICR)........................................................ 4-17

4.3.1.2 SIU Interrupt Priority Register (SIPRR)................................................................ 4-18

4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L).............................4-19

4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L) ................................ 4-21

4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)........................................4-22

4.3.1.6 SIU Interrupt Vector Register (SIVEC)................................................................. 4-24

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

viii Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

4.3.1.7 SIU External Interrupt Control Register (SIEXR).................................................4-25

4.3.2 System Configuration and Protection Registers........................................................ 4-26

4.3.2.1 Bus Configuration Register (BCR)........................................................................ 4-26

4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR)...........................................4-29

4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL).........................4-30

4.3.2.4 Local Bus Arbiter Configuration Register (LCL_ACR) ....................................... 4-31

4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL).............. 4-32

4.3.2.6 SIU Module Configuration Register (SIUMCR)...................................................4-33

4.3.2.7 Internal Memory Map Register (IMMR)............................................................... 4-36

4.3.2.8 System Protection Control Register (SYPCR)......................................................4-37

4.3.2.9 Software Service Register (SWSR)....................................................................... 4-38

4.3.2.10 60x Bus Transfer Error Status and Control Register 1 (TESCR1)........................ 4-38

4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2)........................ 4-40

4.3.2.12 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)................. 4-42

4.3.2.13 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)................. 4-43

4.3.2.14 Time Counter Status and Control Register (TMCNTSC)...................................... 4-44

4.3.2.15 Time Counter Register (TMCNT)......................................................................... 4-44

4.3.2.16 Time Counter Alarm Register (TMCNTAL).........................................................4-45

4.3.3 Periodic Interrupt Registers ....................................................................................... 4-46

4.3.3.1 Periodic Interrupt Status and Control Register (PISCR).......................................4-46

4.3.3.2 Periodic Interrupt Timer Count Register (PITC)...................................................4-46

4.3.3.3 Periodic Interrupt Timer Register (PITR).............................................................. 4-47

4.3.4 PCI Control Registers................................................................................................ 4-48

4.3.4.1 PCI Base Register (PCIBRx)................................................................................. 4-48

4.3.4.2 PCI Mask Register (PCIMSKx) ............................................................................ 4-49

4.4 SIU Pin Multiplexing..................................................................................................... 4-49

Chapter 5

Reset

5.1 Reset Causes .................................................................................................................... 5-1

5.1.1 Reset Actions............................................................................................................... 5-2

5.1.2 Power-On Reset Flow.................................................................................................. 5-2

5.1.3 HRESET Flow............................................................................................................. 5-3

5.1.4 SRESET Flow..............................................................................................................5-3

5.2 Reset Status Register (RSR) ............................................................................................ 5-4

5.3 Reset Mode Register (RMR) ........................................................................................... 5-5

5.4 Reset Configuration ......................................................................................................... 5-6

5.4.1 Hard Reset Configuration Word .................................................................................. 5-8

5.4.2 Hard Reset Configuration Examples ......................................................................... 5-10

5.4.2.1 Single PowerQUICC II with Default Configuration ............................................. 5-10

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