Freescale Semiconductor PowerQUICC III MPC8555E Manual de instrucciones

Freescale Semiconductor

Application Note

This document provides bring-up guidelines for designs

based on the MPC8555E and the MPC8541E devices from

the PowerQUICC III family of integrated communications

processors (collectively referred to throughout this

document as PowerQUICC III). This document can also be

useful in debugging newly designed systems by highlighting

the aspects of a design that merit special attention during

initial system startup.

1 Getting Started

This section outlines recommendations to simplify the first

phase of design. Before designing a system with a

PowerQUICC III device, it is recommended that you

familiarize yourself with the available documentation,

software, microcodes, models, and tools.

Contents

1. Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4. Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5. Power-On Reset/Reset Configurations . . . . . . . . . . . 13

6. Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PowerQUICC III MPC8555E and

MPC8541E Bring-Up Guidelines

by Freescale Semiconductor, Inc.

Document Number: AN2805

Rev. 5, 05/2013

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

2Freescale Semiconductor

Getting Started

1.1 References

Some of the references below may be available only under a non-disclosure agreement (NDA). To request

access to these documents, contact your local field applications engineer or sales representative.

• Collateral

—MPC8555E/MPC8541E PowerQUICC III Integrated Communications Processor Reference

Manual (MPC8555ERM)

— MPC8555E / MPC8541E Device Errata (MPC8555ECE)

—MPC8555E Integrated Processor Hardware Specifications (MPC8555EC)

—MPC8541E Integrated Processor Hardware Specifications (MPC8541EC)

• Available Tools

— CPM Performance Tool

— Boot Sequencer Generator Tool

— Pin Mux Tool

— UPM Programming Tool

•Models

—IBIS

— BSDL, Rev 1.1 silicon

1.2 Device Errata

The device errata documents (MPC8555ECE, MPC8541ECE) describe the latest fixes and workarounds

for the PowerQUICC III family of devices. You should thoroughly research these errata documents before

starting a design with the respective PowerQUICC III device.

1.3 CommunicationsProcessorModule(CPM)PerformanceandBus

Utilization Tool

The PowerQUICC III CPM runs by time-sharing multiple communication protocols. To estimate the CPM

load factor for a particular combination of protocols, use the CPM Performance Evaluator tool, which is

available on the MPC8555E/MPC8541E device web site. At startup, thetoolinitializes all parameters with

default values that may not be the optimal values for your design. For example, the tool initializes with

transmit and receive rates of ‘0’. These values must be changed according to the needs of the application.

1.4 Boot Sequencer Tool

The PowerQUICC III features the boot sequencer to allow configuration of any memory-mapped register

before power-on reset (POR) completes. The register data to be changed is stored in an I2C EEPROM. The

PowerQUICC III requires a particular data format for register changes as outlined in the MPC8555ERM.

The boot sequencer tool is a C code file. When compiled and given a sample data file, it generates the

appropriate raw data format as outlined in the MPC8555ERM—that is, an s-record file that can be used to

program the EEPROM.

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

Freescale Semiconductor 3

Power

1.5 Pin Mux Tool (MPC8555 only)

The on-chip serial communications peripherals use four 32-bit parallel ports to exchange data with the

physical interfaces. On each pin of the parallel ports, several signals are multiplexed. If none of the signals

available on a certain pin are necessary in a certain application, the pin can be used for a general purpose

I/O. To verify the availability of the I/O functions chosen through pin multiplexing, designers are

encouraged to use the MPC8555 Parallel Ports Pin Mux tool. After selecting the signals required by your

application, this utility assists in defining the pin configuration of each parallel port. A report can then be

generated that includes all your selections and C-initialization code for the registers associated with the

parallel ports. The Pin Mux tool is available on the MPC8555E device web site.

1.6 UPM Programming Tool

The UPM Programming Tool features a GUI for a user-friendly programming interface. It allows

programming of all three PowerQUICC III UPM machines. The GUI consists of a wave editor, table

editor, and report generator. You can edit directly the waveform or the RAM array. At the end of

programming, the report generator prints out the UPM ram array that can be used in a C-program. The

UPM Programming Tool is available on the MPC8555E or MPC8541E device web site.

1.7 Available Training

Our third-party partners are part of an extensive Design Alliance Program. Our current training partners

are listed on our external web site under the Design Alliance Program. In addition, training material from

past Smart Network Developer’s Forums is available. These training materials are a valuable resource in

understanding the PowerQUICC III.

2Power

This section provides design considerations for the PowerQUICC III power supplies, as well as power

sequencing. For information on AC and DC electrical specifications and thermal characteristics for the

PowerQUICC III, refer to the MPC8555EEC and the MPC8541EEC. For power sequencing

recommendations refer to Section 2.3, “Power Sequencing.”

2.1 Power Supply

The PowerQUICC III has a core voltage VDD that operates at a lower voltage than the I/O voltages GVDD,

LVDD, and OVDD. It is recommended that the core voltage VDD of the PowerQUICC III be supplied

through a variable switching supply or regulator to allow for future compatibility with possible core

voltage changes on future silicon revisions. The core voltage, 1.2 V (±5%), is supplied across VDD and

GND.

The I/O blocks of the PowerQUICC III are supplied with 2.5 V (±5%) across GVDD and GND, 2.5 V

(±5%) or 3.3 V (±5%) across LVDD and GND, and 3.3 V (±5%) across OVDD and GND. Typically, these

are supplied by simple linear regulators. This increases the complexity of the system because multiple

voltage supplies and PCB power planes are required for the design. No external signals on PowerQUICC

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

4Freescale Semiconductor

Power

III are 5-V-tolerant. All input signals need to meet the G/L/OVIN DC specification of the respective I/O

block. See Table 1.

2.2 Power Consumption

The MPC8555EEC and the MPC8541EEC hardware specifications provide estimated power dissipation

for various frequency configurations of the core complex bus (CCB) clock and the e500 core frequencies.

Suitable thermal management is required to ensure that the junction temperature does not exceed the

maximum specified value. The numbers provided in the hardware specification include dissipation for all

blocks except the PLL supplies and the I/Os. Both must be added to the typical number to determine

accurately whether a heat sink or other form of chip cooling mechanism is required.

2.3 Power Sequencing

One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp

up at different rates. These rates depend on the power supply, the type of load on each power supply, and

the way different voltages are derived. The MPC8555E and MPC8541E require the power rails to be

applied in a specific sequence to ensure proper device operation. The requirements for power-up are as

follows:

1. VDD, AVDD

2. GVDD, LVDD, OVDD (I/O supplies)

Items on the same line have no ordering requirements with respect to one another. Items on separate lines

must be ordered sequentially so that voltage rails on a previous step reach 90 percent of their value before

the voltage rails on the current step reach 10 percent of theirs. If the items on line 2 must precede items on

line 1, take care to ensure that the delay does not exceed 50 mS and that the power sequence is not

performed more than once per day in a production environment.

NOTE

To guarantee MCKE low during power-up, GVDD should be the last power

supplytocomeup. If thereisnoconcern aboutanyofthe DDR signalsbeing

in an indeterminate state during power-up, then the sequencing is not

required.

Table 1. Power Supplies

Type Name Block (V)

Core VDD —1.2

PLL AVDD Core PLL, Platform PLL, CPM PLL, PCI1, PCI2 1.2

I/O GVDD DDR 2.5

I/O LVDD TSEC 2.5 / 3.3

I/O OVDD CPM, LBIU, DMA, MII-mgt, PIC1, PCI2, I2C3.3

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

Freescale Semiconductor 5

Power

NOTE

From a system standpoint, if the I/O power supplies ramp prior to the VDD

core supply, then the port pins on the MPC8555E and MPC8541E CPMs

may drive a logic-one or -zero during power-up.

Table 2 lists the current maximum ratings for the power supplies. Supplies must not exceed these absolute

maximum ratings. However, during normal operation, use of the Recommended Operating Conditions

table in the hardware specification is recommended. Any information in the relevant hardware

specification supersedes information in Table 2.

2.4 Power Planes

Each VDD pin should be provided with a low-impedance path to the board power supply. Similarly, each

ground pin should be provided with a low-impedance path to ground. The power supply pins drive distinct

groups of logic on-chip. The capacitor leads and associated printed circuit traces connecting to chip VDD

and ground should be kept to less than half an inch per capacitor lead.

2.5 Decoupling

Due to large address and data buses and high operating frequencies, the PowerQUICC III can generate

transient power surges and high-frequency noise in its power supply, especially while driving large

capacitive loads. This noise must be prevented from reaching other components in the PowerQUICC III

system, and the PowerQUICC III itself requires a clean, tightly regulated source of power. Therefore, you

should place at least one decoupling capacitor at each VDD, GVDD, LVDD, OVDD, and pins of the

PowerQUICC III. These decoupling capacitors should receive their power from separate VDD, GVDD,

LVDD, OVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance.

Capacitors may be placed directly under the device using a standard escape pattern. Others may surround

thepart.Thesecapacitorsshould have avalueof0.01 or 0.1 µF. Tominimize lead inductance,onlyceramic

SMT (surface mount technology) capacitors should be used. In addition, several bulk storage capacitors

should be distributed around the PCB, feeding the VDD, GVDD, LVDD, and OVDD planes, to enable quick

recharging of the smaller chip capacitors. These bulk capacitors should have a low equivalent series

resistance (ESR) rating to ensure the quick response time necessary. They should also be connected to the

power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330

µF. Simulation is strongly recommended to minimize noise on the power supplies before proceeding into

the PCB design and manufacturing stage of development.

Table 2. Maximum Voltage Ratings

Type Name Block (V) (Vmax)

Core Vdd — 1.2 1.32

PLL AVdd Core PLL, Platform PLL, CPM PLL, PCI1, PCI2 1.2 1.32

I/O GVdd DDR 2.5 3.63

I/O LVdd TSEC 2.5 / 3.3 2.75 / 3.63

I/O OVdd CPM, LBIU, DMA, MII-mgt, PIC1,PCI2, I2C3.3 3.63

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

6Freescale Semiconductor

Clocking

2.6 PLL Power Supply Filtering

Each PowerQUICC III PLL is provided with power through independent power supply pins for the

MPC8555E, and MPC8541E (AVDD1, AVDD2, AVDD3, AVDD4, and AVDD5). The AVDD level should

always be equivalent to VDD, and preferably these voltages are derived directly from VDD through a

low-frequency filter as shown in Figure 1.

Figure 1. PLL Power Supply Filter Circuit

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is three

independent filter circuits, one to each of the three AVDD pins. Providing independent filters to each PLL

reduces the opportunity to cause noise injection from one PLL to the other. This circuit is intended to filter

noise in the PLL resonant frequency range, from 500 kHz to 10 MHz. It should be built with surface mount

capacitors with minimum effective series inductance (ESL). Each circuit should be placed as closely as

possible to the specific AVDD pin supplied to minimize noise coupled from nearby circuits. It should be

possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 783

FC-PBGA footprint, without the inductance of vias. If possible, a separate plane for each PLL filtering

circuit is recommended.

3 Clocking

3.1 System Clock

The system clock SYSCLK input is the primary clock source for all Synchronous blocks on the

PowerQUICC III and must always be provided. The SYSCLK input is multiplied by a phase-lock loop

(PLL) to generate the core complex bus (CCB) clock. The CCB clock is used by the L2 cache, CPM and

DMA. It is divided by two to generate the DDR clocks MCK[0:5]. It is divided by 2/4/8 (in the

LCRR[CLKDIV] register) to generate local bus clocks LCLK[0:2]. It is also multiplied by a second PLL

(by the power-on reset setting LALE, LGPL2) to generate the e500 core clock. As there are no default

settingsforthe two PowerQUICCIIIPLLs,power-on reset configurationofthemwithin the system design

is mandatory.

The PCI interface has two clock modes, Synchronous mode, and Asynchronous mode. The default clock

mode (Synchronous) uses the SYSCLK. In Asynchronous mode each PCI (PCI1, PCI2) interface can be

configured to use separate PCI clock input unrelated to the SYSCLK input. The PCI clock modes are

configured during POR by TSEC2_TXD1, and TSEC2_TXD0 signals. See Figure 2 and Table 3.

VDD AVDD

10 Ω

2.2 µF 2.2 µF

GND

Low ESL surface mount capacitors

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

Freescale Semiconductor 7

Clocking

Figure 2. Clock Subsystem Block Diagram

Table 3. Clocking Quick Reference

Functional Block Clock Derivation

Core (including L1) CCB [2, 2.5, 3, 3.5]

DDR CCB / 2

I2C CCB / (I2CFDR ratio)

L2 cache, CPM CCB

Local Bus CCB / [2,4,8]

Core PLL

Platform PLL

DLL

LSYNC_IN

LSYNC_OUT

LCLK0

LCLK1

core_clk

e500 Core

CCB_clk to Rest of the Device

SYSCLK

CCB_clk

cfg_sys_pll[0:3]

cfg_core_pll[0:1] 2

LBC

PCI1 PLL

PCI2 PLL

PCI 2

PCI 1

PCI1_CLK

cfg_pci1_clk

cfg_pci2_clk

PCI2_CLK

DRAM MCK[0:5]

MCK[0:5]

6DDR

Controller

Clock

Control

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

8Freescale Semiconductor

Clocking

3.2 Clocking Example

Let us assume that we want to maximize the frequenciesofcertainkeyinterfaces. Wecan use the following

inputs:

• SYSCLK = 66 MHz

• CCB multiplier = 5 (cfg_sys_pll)

• Core multiplier = 2.5 (cfg_core_pll)

• Local bus divider = 2 (LCRR[CLKDIV])

The resulting frequencies for the following interfaces are:

• Core = SYSCLK * cfg_sys_pll * cfg_core_pll = 833 MHz

• CPM = SYSCLK * cfg_sys_pll = 333 MHz

• DDR (MCKn) = SYSCLK * cfg_sys_pll/2 = 167MHz = 333 MHz data rate

• PCI = SYSCLK = 66 MHz

• Local Bus (LCLKn) = SYSCLK * cfg_sys_pll / CLKLDIV = 167 MHz

These are the current maximum frequencies. Check the relevant product web site for updated options.

3.3 Core Clock

The frequency of the core is determined at POR through the LALE and the LGPL2 pins. Below are the

options for configuring the core clock as a multiple of the CCB clock. This information can be found in

the MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual

(MPC8555ERM).

3.4 DDR SDRAM Clock Outputs

The DDR SDRAM clock outputs MCK[0:5] and MCK[0:5] are derived from the CCB clock. No

configuration pins or register settings are required to generate the MCK/MCKn frequencies because they

are by default one-half the CCB clock frequency.

PCI1, PCI2 SYSCLK, or PCI_CLK

TSEC 125MHz from PHY or External (certain modes)

Table 4. Core Clock POR Configuration

LALE, LGPL2 Core: CCB

00 2:1

01 5:2 (2.5:1)

10 3:1

11 7:2 (3.5:1)

Table 3. Clocking Quick Reference (continued)

Functional Block Clock Derivation

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

Freescale Semiconductor 9

Debug

3.5 I2C Clock

The I2C clock rate is determined by a ratio set in the I2CFDR register. Refer to the MPC8555ERM.

3.6 L2 Cache and CPM Clocks

The clock rate for the L2 Cache and the CPM is the same as the CCB clock frequency.

3.7 Local Bus Clock Outputs

The local bus clock outputs LCLK[0:2] are derived from the CCB clock. By default the LCLKn frequency

is CCB clock frequency divided by eight. However, by appropriately setting the System Clock Divider

parameter in the Clock Ratio Register (LCRR[CLKDIV]), the LCLKn frequency can be configured as

shown in Table 5.

3.8 PCI Clock Input

There are two modes for PCI clock input—synchronous mode and asynchronous mode. In synchronous

mode the input clock for the PCI interfaces on the MPC8555E and the MPC8541E is, by default, the

system clock (SYSCLK input). In asynchronous mode each PCI (PCI1, PCI2) interface can be configured

touseaseparatePCIclockinput unrelated to the SYSCLKinput.ThePCI clock mode is configured during

POR by TSEC2_TXD1, and TSEC2_TXD0 signals.

3.9 TSEC Reference Clock Input

This signal is not used for MII mode. When any other mode is used in the TSEC interface, the gigabit

transmit 125 MHz reference clock EC_GTX_CLK125 must be supplied. This signal must be generated

externally with a crystal or oscillator, or it can sometimes be provided by the PHY. In GMII, RGMII, RTBI

or TBI mode, EC_GTX_CLK125 is a 125 MHz input into the TSEC and is used to generate all

125-MHz-related signals and clocks.

4 Debug

This section describes the PowerQUICC III reset sequence and recommendations for the system.

Table 5. Local Bus Clock Divider Options

LCRR[CLKDIV] LCLKn Frequency

0010 CCB Clock / 2

0100 CCB Clock / 4

1000 (Default) CCB Clock / 8

All other values Reserved

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

10 Freescale Semiconductor

Debug

4.1 TRST

TRST is the reset pin for the JTAG/COP interface. It must be held at a low level during the assertion of

HRESET to reset all logic completely on the PowerQUICC III. For compatibility with third-party tools,

TRST and HRESET must be able to assert independently (see the example in Figure 3).

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