Freescale Semiconductor MCF5480 Manual de usuario

MCF548x Reference Manual

Devices Supported:

MCF5485 MCF5482

MCF5484 MCF5481

MCF5483 MCF5480

Document Number: MCF5485RM

Rev. 3

01/2006

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MCF5485RM

Rev. 3

01/2006

Overview

Signal Descriptions

ColdFire Core

Enhanced Multiply-Accumulate Unit (EMAC)

Memory Management Unit (MMU)

Floating-Point Unit (FPU)

Debug Support

System Integration Unit (SIU)

Local Memory

Edge Port Module (EPORT)

Index

Interrupt Controller (INTC)

General Purpose I/O (GPIO)

PCI Bus Arbiter (PCIARB)

General Purpose Timers (GPT)

Slice Timers (SLT)

Internal Clocks and Bus Architecture 10

PCI Bus Controller (PCI) 19

FlexBus

SDRAM Controller (SDRAMC)

System SRAM 16

Integrated Secuity Engine (SEC)

FlexCAN

IEEE 1149.1 Test Access Port (JTAG)

DMA Serial Peripheral Interface (DSPI)

I2C interface 27

Comm Timer Module (CTM)

Programmable Serial Controller (PSC)

Multichannel DMA (MCD) 24

Mechanical Data

USB 2.0 Device Controller

Fast Ethernet Controller (FEC)

IND

Overview

Signal Descriptions

ColdFire Core

Enhanced Multiply-Accumulate Unit (EMAC)

Memory Management Unit (MMU)

Floating-Point Unit (FPU)

Debug Support

System Integration Unit (SIU)

Local Memory

Edge Port Module (EPORT)

Index

Interrupt Controller (INTC)

General Purpose I/O (GPIO)

PCI Bus Arbiter (PCIARB)

General Purpose Timers (GPT)

Slice Timers (SLT)

Internal Clocks and Bus Architecture

PCI Bus Controller (PCI)

FlexBus

SDRAM Controller (SDRAMC)

System SRAM

Integrated Secuity Engine (SEC)

FlexCAN

IEEE 1149.1 Test Access Port (JTAG)

DMA Serial Peripheral Interface (DSPI)

I2C interface

Comm Timer Module (CTM)

Programmable Serial Controller (PSC)

Multichannel DMA (MCD)

Mechanical Data

USB 2.0 Device Controller

Fast Ethernet Controller (FEC)

IND

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor v

Contents

Paragraph

Number Title Page

Number

Chapter 1

Overview

1.1 MCF548x Family Overview ........................................................................................... 1-1

1.2 MCF548x Block Diagram .............................................................................................. 1-2

1.3 MCF548x Family Products ............................................................................................. 1-3

1.4 MCF548x Family Features ............................................................................................. 1-3

1.4.1 ColdFire V4e Core Overview ..................................................................................... 1-5

1.4.2 Debug Module (BDM) ................................................................................................ 1-6

1.4.3 JTAG ........................................................................................................................... 1-6

1.4.4 On-Chip Memories ..................................................................................................... 1-7

1.4.4.1 Caches ..................................................................................................................... 1-7

1.4.4.2 System SRAM ........................................................................................................ 1-7

1.4.5 PLL and Chip Clocking Options ................................................................................ 1-7

1.4.6 Communications I/O Subsystem ................................................................................ 1-8

1.4.6.1 DMA Controller ...................................................................................................... 1-8

1.4.6.2 10/100 Fast Ethernet Controller (FEC) ................................................................... 1-8

1.4.6.3 USB 2.0 Device (Universal Serial Bus) ................................................................. 1-8

1.4.6.4 Programmable Serial Controllers (PSCs) ............................................................... 1-9

1.4.6.5 I2C (Inter-Integrated Circuit) ................................................................................. 1-9

1.4.6.6 DMA Serial Peripheral Interface (DSPI) ................................................................ 1-9

1.4.6.7 Controller Area Network (CAN) .......................................................................... 1-10

1.4.7 DDR SDRAM Memory Controller ........................................................................... 1-10

1.4.8 Peripheral Component Interconnect (PCI) ............................................................... 1-10

1.4.9 Flexible Local Bus (FlexBus) ................................................................................... 1-10

1.4.10 Security Encryption Controller (SEC) ...................................................................... 1-11

1.4.11 System Integration Unit (SIU) .................................................................................. 1-11

1.4.11.1 Timers ................................................................................................................... 1-11

1.4.11.2 Interrupt Controller ............................................................................................... 1-12

1.4.11.3 General Purpose I/O ............................................................................................. 1-12

Chapter 2

Signal Descriptions

2.1 Introduction ..................................................................................................................... 2-1

2.1.1 Block Diagram ............................................................................................................ 2-1

2.2 MCF548x External Signals ........................................................................................... 2-16

2.2.1 FlexBus Signals ........................................................................................................ 2-16

2.2.1.1 Address/Data Bus (AD[31:0]) .............................................................................. 2-16

2.2.1.2 Chip Select (FBCS[5:0]) ....................................................................................... 2-17

2.2.1.3 Address Latch Enable (ALE) ................................................................................ 2-17

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vi Freescale Semiconductor

Contents

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2.2.1.4 Read/Write (R/W) ................................................................................................. 2-17

2.2.1.5 Transfer Burst (TBST) .......................................................................................... 2-17

2.2.1.6 Transfer Size (TSIZ[1:0]) ..................................................................................... 2-17

2.2.1.7 Byte Selects (BE/BWE[3:0]) ................................................................................ 2-18

2.2.1.8 Output Enable (OE) .............................................................................................. 2-18

2.2.1.9 Transfer Acknowledge (TA) ................................................................................. 2-18

2.2.2 SDRAM Controller Signals ...................................................................................... 2-18

2.2.2.1 SDRAM Data Bus (SDDATA[31:0]) ................................................................... 2-18

2.2.2.2 SDRAM Address Bus (SDADDR[12:0]) ............................................................. 2-18

2.2.2.3 SDRAM Bank Addresses (SDBA[1:0]) ............................................................... 2-19

2.2.2.4 SDRAM Row Address Strobe (RAS) ................................................................... 2-19

2.2.2.5 SDRAM Column Address Strobe (CAS) ............................................................. 2-19

2.2.2.6 SDRAM Chip Selects (SDCS[3:0]) ...................................................................... 2-19

2.2.2.7 SDRAM Write Data Byte Mask (SDDM[3:0]) .................................................... 2-19

2.2.2.8 SDRAM Data Strobe (SDDQS[3:0]) .................................................................... 2-19

2.2.2.9 SDRAM Clock (SDCLK[1:0]) ............................................................................. 2-19

2.2.2.10 Inverted SDRAM Clock (SDCLK[1:0]) ............................................................... 2-19

2.2.2.11 SDRAM Write Enable (SDWE) ........................................................................... 2-19

2.2.2.12 SDRAM Clock Enable (SDCKE) ......................................................................... 2-19

2.2.2.13 SDR SDRAM Data Strobe (SDRDQS) ................................................................ 2-19

2.2.2.14 SDRAM Reference Voltage (VREF) ................................................................... 2-20

2.2.3 PCI Controller Signals .............................................................................................. 2-20

2.2.3.1 PCI Address/Data Bus (PCIAD[31:0]) ................................................................. 2-20

2.2.3.2 Command/Byte Enables (PCICXBE[3:0]) ........................................................... 2-20

2.2.3.3 Device Select (PCIDEVSEL) ............................................................................... 2-20

2.2.3.4 Frame (PCIFRM) .................................................................................................. 2-20

2.2.3.5 Initialization Device Select (PCIIDSEL) .............................................................. 2-20

2.2.3.6 Initiator Ready (PCIIRDY) ................................................................................... 2-20

2.2.3.7 Parity (PCIPAR) ................................................................................................... 2-20

2.2.3.8 Parity Error (PCIPERR) ....................................................................................... 2-20

2.2.3.9 Reset (PCIRESET) ............................................................................................... 2-21

2.2.3.10 System Error (PCISERR) ..................................................................................... 2-21

2.2.3.11 Stop (PCISTOP) ................................................................................................... 2-21

2.2.3.12 Target Ready (PCITRDY) .................................................................................... 2-21

2.2.3.13 External Bus Grant (PCIBG[4:1]) ........................................................................ 2-21

2.2.3.14 External Bus Grant/Request Output (PCIBG0/PCIREQOUT) ............................ 2-21

2.2.3.15 External Bus Request (PCIBR[4:0]) ..................................................................... 2-21

2.2.3.16 External Request/Grant Input (PCIBR0/PCIGNTIN) .......................................... 2-21

2.2.4 Interrupt Control Signals .......................................................................................... 2-21

2.2.4.1 Interrupt Request (IRQ[7:1]) ................................................................................ 2-21

2.2.5 Clock and Reset Signals ........................................................................................... 2-22

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor vii

Contents

Paragraph

Number Title Page

Number

2.2.5.1 Reset In (RSTI) ..................................................................................................... 2-22

2.2.5.2 Reset Out (RSTO) ................................................................................................. 2-22

2.2.5.3 Clock In (CLKIN) ................................................................................................. 2-22

2.2.6 Reset Configuration Pins .......................................................................................... 2-22

2.2.6.1 AD[12:8]—CLKIN to SDCLK Ratio (CLKCONFIG[4:0]) ................................ 2-22

2.2.6.2 AD5—FlexBus Size Configuration (FBSIZE) ..................................................... 2-23

2.2.6.3 AD4—32-bit FlexBus Configuration (FBMODE) ............................................... 2-23

2.2.6.4 AD3—Byte Enable Configuration (BECONFIG) ................................................ 2-23

2.2.6.5 AD2—Auto Acknowledge Configuration (AACONFIG) .................................... 2-24

2.2.6.6 AD[1:0]—Port Size Configuration (PSCONFIG) ................................................ 2-24

2.2.7 Ethernet Module Signals ........................................................................................... 2-24

2.2.7.1 Management Data (E0MDIO, E1MDIO) ............................................................. 2-24

2.2.7.2 Management Data Clock (E0MDC, E1MDC) ...................................................... 2-25

2.2.7.3 Transmit Clock (E0TXCLK, E1TXCLK) ............................................................ 2-25

2.2.7.4 Transmit Enable (E0TXEN, E1TXEN) ................................................................ 2-25

2.2.7.5 Transmit Data 0 (E0TXD0, E1TXD0) ................................................................. 2-25

2.2.7.6 Collision (E0COL, E1COL) ................................................................................. 2-25

2.2.7.7 Receive Clock (E0RXCLK, E1RXCLK) ............................................................. 2-25

2.2.7.8 Receive Data Valid (E0RXDV, E1RXDV) .......................................................... 2-25

2.2.7.9 Receive Data 0 (E0RXD0, E1RXD0) .................................................................. 2-25

2.2.7.10 Carrier Receive Sense (E0CRS, E1CRS) ............................................................. 2-25

2.2.7.11 Transmit Data 1–3 (E0TXD[3:1], E1TXD[3:1]) .................................................. 2-25

2.2.7.12 Transmit Error (E0TXER, E1TXER) ................................................................... 2-26

2.2.7.13 Receive Data 1–3 (E0RXD[3:1], E1RXD[3:1]) ................................................... 2-26

2.2.7.14 Receive Error (E0RXER, E1RXER) .................................................................... 2-26

2.2.8 Universal Serial Bus (USB) ...................................................................................... 2-26

2.2.8.1 USB Differential Data (USBD+, USBD–) ........................................................... 2-26

2.2.8.2 USBVBUS ............................................................................................................ 2-26

2.2.8.3 USBRBIAS ........................................................................................................... 2-26

2.2.8.4 USBCLKIN .......................................................................................................... 2-26

2.2.8.5 USBCLKOUT ...................................................................................................... 2-26

2.2.9 DMA Serial Peripheral Interface (DSPI) Signals ..................................................... 2-26

2.2.9.1 DSPI Synchronous Serial Data Output (DSPISOUT) .......................................... 2-26

2.2.9.2 DSPI Synchronous Serial Data Input (DSPISIN) ................................................. 2-27

2.2.9.3 DSPI Serial Clock (DSPISCK) ............................................................................. 2-27

2.2.9.4 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS) ................................... 2-27

2.2.9.5 DSPI Chip Selects (DSPICS[2:3]) ........................................................................ 2-27

2.2.9.6 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS) 2-27

2.2.10 FlexCAN Signals ...................................................................................................... 2-27

2.2.10.1 FlexCAN Transmit (CANTX0, CANTX1) .......................................................... 2-27

2.2.10.2 FlexCAN Receive (CANRX0, CANRX1) ........................................................... 2-27

MCF548x Reference Manual, Rev. 3

viii Freescale Semiconductor

Contents

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2.2.11 I2C I/O Signals .......................................................................................................... 2-27

2.2.11.1 Serial Clock (SCL) ............................................................................................... 2-28

2.2.11.2 Serial Data (SDA) ................................................................................................. 2-28

2.2.12 PSC Module Signals ................................................................................................. 2-28

2.2.12.1 Transmit Serial Data Output (PSC0TXD, PSC1TXD, PSC2TXD, PSC3TXD) .. 2-28

2.2.12.2 Receive Serial Data Input (PSC0RXD, PSC1RXD, PSC2RXD, PSC3RXD) ..... 2-28

2.2.12.3 Clear-to-Send (PSCnCTS/PSCBCLK) ................................................................. 2-28

2.2.12.4 Request-to-Send (PSCnRTS/PSCFSYNC) ........................................................... 2-28

2.2.13 DMA Controller Module Signals ............................................................................. 2-28

2.2.13.1 DMA Request (DREQ[1:0]) ................................................................................. 2-28

2.2.13.2 DMA Acknowledge (DACK[1:0]) ....................................................................... 2-28

2.2.14 Timer Module Signals .............................................................................................. 2-29

2.2.14.1 Timer Inputs (TIN[3:0]) ....................................................................................... 2-29

2.2.14.2 Timer Outputs (TOUT[3:0]) ................................................................................. 2-29

2.2.15 Debug Support Signals ............................................................................................. 2-29

2.2.15.1 Processor Clock Output (PSTCLK) ...................................................................... 2-29

2.2.15.2 Processor Status Debug Data (PSTDDATA[7:0]) ............................................... 2-29

2.2.15.3 Development Serial Clock/Test Reset (DSCLK/TRST) ...................................... 2-29

2.2.15.4 Breakpoint/Test Mode Select (BKPT/TMS) ........................................................ 2-30

2.2.15.5 Development Serial Input/Test Data Input (DSI/TDI) ......................................... 2-30

2.2.15.6 Development Serial Output/Test Data Output (DSO/TDO) ................................. 2-30

2.2.15.7 Test Clock (TCK) ................................................................................................. 2-30

2.2.16 Test Signals ............................................................................................................... 2-30

2.2.16.1 Test Mode (MTMOD[3:0]) .................................................................................. 2-30

2.2.17 Power and Reference Pins ........................................................................................ 2-31

2.2.17.1 Positive Pad Supply (EVDD) ............................................................................... 2-31

2.2.17.2 Positive Core Supply (IVDD) ............................................................................... 2-31

2.2.17.3 Ground (VSS) ....................................................................................................... 2-31

2.2.17.4 USB Power (USBVDD) ....................................................................................... 2-31

2.2.17.5 USB Oscillator Power (USB_OSCVDD) ............................................................. 2-31

2.2.17.6 USB PHY Power (USB_PHYVDD) .................................................................... 2-31

2.2.17.7 USB Oscillator Analog Power (USB_OSCAVDD) ............................................. 2-31

2.2.17.8 USB PLL Analog Power (USB_PLLVDD) ......................................................... 2-31

2.2.17.9 SDRAM Memory Supply (SDVDD) .................................................................... 2-31

2.2.17.10 PLL Analog Power (PLLVDD) ............................................................................ 2-31

2.2.17.11 PLL Analog Ground (PLLVSS) ........................................................................... 2-31

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor ix

Contents

Paragraph

Number Title Page

Number

Chapter 3

ColdFire Core

3.1 Core Overview ................................................................................................................ 3-1

3.2 Features ........................................................................................................................... 3-1

3.2.1 Enhanced Pipelines ..................................................................................................... 3-2

3.2.1.1 Instruction Fetch Pipeline (IFP) .............................................................................. 3-3

3.2.1.2 Operand Execution Pipeline (OEP) ........................................................................ 3-4

3.2.1.3 Harvard Memory Architecture ............................................................................... 3-6

3.2.2 Debug Module Enhancements .................................................................................... 3-6

3.3 Programming Model ....................................................................................................... 3-7

3.3.1 User Programming Model .......................................................................................... 3-9

3.3.1.1 Data Registers (D0–D7) ......................................................................................... 3-9

3.3.1.2 Address Registers (A0–A6) .................................................................................... 3-9

3.3.2 User Stack Pointer (A7) ............................................................................................. 3-9

3.3.2.1 Program Counter (PC) ............................................................................................ 3-9

3.3.2.2 Condition Code Register (CCR) ............................................................................. 3-9

3.3.3 EMAC Programming Model .................................................................................... 3-10

3.3.4 FPU Programming Model ......................................................................................... 3-10

3.3.5 Supervisor Programming Model ............................................................................... 3-11

3.3.5.1 Status Register (SR) .............................................................................................. 3-12

3.3.5.2 Vector Base Register (VBR) ................................................................................ 3-12

3.3.5.3 Cache Control Register (CACR) .......................................................................... 3-13

3.3.5.4 Access Control Registers (ACR0–ACR3) ............................................................ 3-13

3.3.5.5 RAM Base Address Registers (RAMBAR0 and RAMBAR1) ............................ 3-13

3.3.5.6 Module Base Address Register (MBAR) ............................................................. 3-13

3.3.6 Programming Model Table ....................................................................................... 3-13

3.4 Data Format Summary .................................................................................................. 3-15

3.4.1 Data Organization in Registers ................................................................................. 3-15

3.4.1.1 Integer Data Format Organization in Registers .................................................... 3-15

3.4.1.2 Integer Data Format Organization in Memory ..................................................... 3-16

3.4.2 EMAC Data Representation ..................................................................................... 3-17

3.4.2.1 Floating-Point Data Formats and Types ............................................................... 3-17

3.5 Addressing Mode Summary ......................................................................................... 3-18

3.6 Instruction Set Summary .............................................................................................. 3-19

3.6.1 Additions to the Instruction Set Architecture ........................................................... 3-19

3.6.2 Instruction Set Summary .......................................................................................... 3-22

3.7 Instruction Execution Timing ....................................................................................... 3-27

3.7.1 MOVE Instruction Execution Timing ...................................................................... 3-28

3.7.2 One-Operand Instruction Execution Timing ............................................................ 3-30

3.7.3 Two-Operand Instruction Execution Timing ............................................................ 3-31

MCF548x Reference Manual, Rev. 3

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Contents

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3.7.4 Miscellaneous Instruction Execution Timing ........................................................... 3-32

3.7.5 Branch Instruction Execution Timing ....................................................................... 3-33

3.7.6 EMAC Instruction Execution Times ........................................................................ 3-34

3.7.7 FPU Instruction Execution Times ............................................................................. 3-35

3.8 Exception Processing Overview ................................................................................... 3-36

3.8.1 Exception Stack Frame Definition ............................................................................ 3-38

3.8.2 Processor Exceptions ................................................................................................ 3-39

3.9 Precise Faults ................................................................................................................ 3-42

Chapter 4

Enhanced Multiply-Accumulate Unit (EMAC)

4.1 Introduction ..................................................................................................................... 4-1

4.1.1 MAC Overview ........................................................................................................... 4-2

4.1.2 General Operation ....................................................................................................... 4-2

4.2 Memory Map/Register Definition .................................................................................. 4-5

4.2.1 MAC Status Register (MACSR) ................................................................................. 4-5

4.2.1.1 Fractional Operation Mode ..................................................................................... 4-8

4.2.2 Mask Register (MASK) ............................................................................................ 4-10

4.3 EMAC Instruction Set Summary .................................................................................. 4-11

4.3.1 EMAC Instruction Execution Timing ....................................................................... 4-11

4.3.2 Data Representation .................................................................................................. 4-12

4.3.3 EMAC Opcodes ........................................................................................................ 4-13

Chapter 5

Memory Management Unit (MMU)

5.1 Features ........................................................................................................................... 5-1

5.2 Virtual Memory Management Architecture ................................................................... 5-1

5.2.1 MMU Architecture Features ....................................................................................... 5-1

5.2.2 MMU Architecture Location ...................................................................................... 5-2

5.2.3 MMU Architecture Implementation ........................................................................... 5-3

5.2.3.1 Precise Faults ..........................................................................................................5-4

5.2.3.2 MMU Access .......................................................................................................... 5-4

5.2.3.3 Virtual Mode ........................................................................................................... 5-4

5.2.3.4 Virtual Memory References ................................................................................... 5-4

5.2.3.5 Instruction and Data Cache Addresses ................................................................... 5-4

5.2.3.6 Supervisor/User Stack Pointers .............................................................................. 5-5

5.2.3.7 Access Error Stack Frame ...................................................................................... 5-5

5.2.3.8 Expanded Control Register Space .......................................................................... 5-5

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