Freescale Semiconductor MC9S08PT60 Manual de usuario

MC9S08PT60 Reference Manual

Supports: MC9S08PT60(A) and MC9S08PT32(A)

Document Number: MC9S08PT60RM

Rev 4, 08/2014

MC9S08PT60 Reference Manual, Rev. 4, 08/2014

2 Freescale Semiconductor, Inc.

Contents

Section number Title Page

Chapter 1

Device Overview

1.1 Introduction.....................................................................................................................................................................35

1.2 MCU block diagram....................................................................................................................................................... 36

1.3 System clock distribution................................................................................................................................................38

Chapter 2

Pins and connections

2.1 Device pin assignment.................................................................................................................................................... 41

2.2 Pin functions................................................................................................................................................................... 45

2.2.1 Power (VDD, VSS)..........................................................................................................................................45

2.2.2 Analog power supply and reference pins (VDDA/VREFH and VSSA/VREFL)............................................46

2.2.3 Oscillator (XTAL, EXTAL)............................................................................................................................ 47

2.2.4 External reset pin (RESET) and interrupt pin (IRQ)....................................................................................... 48

2.2.5 Background/mode select (BKGD/MS)............................................................................................................ 49

2.2.6 Port A input/output (I/O) pins (PTA7–PTA0)................................................................................................. 50

2.2.7 Port B input/output (I/O) pins (PTB7–PTB0)..................................................................................................50

2.2.8 Port C input/output (I/O) pins (PTC7–PTC0)..................................................................................................50

2.2.9 Port D input/output (I/O) pins (PTD7–PTD0)................................................................................................. 50

2.2.10 Port E input/Output (I/O) pins (PTE7–PTE0)..................................................................................................51

2.2.11 Port F input/output (I/O) pins (PTF7–PTF0)................................................................................................... 51

2.2.12 Port G input/output (I/O) pins (PTG3–PTG0)................................................................................................. 51

2.2.13 Port H input/output (I/O) pins (PTH7–PTH6, PTH2–PTH0)..........................................................................51

2.2.14 True open drain pins (PTA3–PTA2)................................................................................................................51

2.2.15 High current drive pins (PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, PTH1)........................................52

2.2.16 Peripheral pinouts............................................................................................................................................ 52

Chapter 3

Power management

3.1 Introduction.....................................................................................................................................................................55

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3.2 Features...........................................................................................................................................................................55

3.2.1 Run mode......................................................................................................................................................... 55

3.2.2 Wait mode........................................................................................................................................................56

3.2.3 Stop3 mode...................................................................................................................................................... 56

3.2.4 Active BDM enabled in stop3 mode................................................................................................................56

3.2.5 LVD enabled in stop mode.............................................................................................................................. 57

3.2.6 Power modes behaviors................................................................................................................................... 57

3.3 Low voltage detect (LVD) system..................................................................................................................................58

3.3.1 Power-on reset (POR) operation......................................................................................................................59

3.3.2 LVD reset operation.........................................................................................................................................59

3.3.3 Low-voltage warning (LVW).......................................................................................................................... 59

3.4 Bandgap reference.......................................................................................................................................................... 60

3.5 Power management control bits and registers................................................................................................................ 60

3.5.1 System Power Management Status and Control 1 Register (PMC_SPMSC1)................................................60

3.5.2 System Power Management Status and Control 2 Register (PMC_SPMSC2)................................................62

Chapter 4

Memory map

4.1 Memory map...................................................................................................................................................................63

4.2 Reset and interrupt vector assignments...........................................................................................................................64

4.3 Register addresses and bit assignments.......................................................................................................................... 65

4.4 Random-access memory (RAM).................................................................................................................................... 77

4.5 Flash and EEPROM........................................................................................................................................................77

4.5.1 Overview..........................................................................................................................................................77

4.5.2 Function descriptions....................................................................................................................................... 79

4.5.2.1 Modes of operation........................................................................................................................ 79

4.5.2.2 Flash and EEPROM memory map.................................................................................................80

4.5.2.3 Flash and EEPROM initialization after system reset.....................................................................80

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4.5.2.4 Flash and EEPROM command operations.....................................................................................81

4.5.2.5 Flash and EEPROM interrupts.......................................................................................................86

4.5.2.6 Protection....................................................................................................................................... 87

4.5.2.7 Security.......................................................................................................................................... 91

4.5.2.8 Flash and EEPROM commands.....................................................................................................93

4.5.2.9 Flash and EEPROM command summary...................................................................................... 95

4.6 Flash and EEPROM registers descriptions.....................................................................................................................109

4.6.1 Flash Clock Divider Register (NVM_FCLKDIV)...........................................................................................109

4.6.2 Flash Security Register (NVM_FSEC)............................................................................................................110

4.6.3 Flash CCOB Index Register (NVM_FCCOBIX)............................................................................................ 111

4.6.4 Flash Configuration Register (NVM_FCNFG)............................................................................................... 111

4.6.5 Flash Error Configuration Register (NVM_FERCNFG).................................................................................112

4.6.6 Flash Status Register (NVM_FSTAT).............................................................................................................113

4.6.7 Flash Error Status Register (NVM_FERSTAT).............................................................................................. 114

4.6.8 Flash Protection Register (NVM_FPROT)......................................................................................................115

4.6.9 EEPROM Protection Register (NVM_EEPROT)............................................................................................116

4.6.10 Flash Common Command Object Register:High (NVM_FCCOBHI)............................................................118

4.6.11 Flash Common Command Object Register: Low (NVM_FCCOBLO)...........................................................118

4.6.12 Flash Option Register (NVM_FOPT)..............................................................................................................118

Chapter 5

Interrupt

5.1 Interrupts.........................................................................................................................................................................121

5.1.1 Interrupt stack frame........................................................................................................................................ 122

5.1.2 Interrupt vectors, sources, and local masks......................................................................................................123

5.1.3 Hardware nested interrupt................................................................................................................................126

5.1.3.1 Interrupt priority level register.......................................................................................................127

5.1.3.2 Interrupt priority level comparator set........................................................................................... 128

5.1.3.3 Interrupt priority mask update and restore mechanism..................................................................128

5.1.3.4 Integration and application of the IPC........................................................................................... 129

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5.2 IRQ..................................................................................................................................................................................129

5.2.1 Features............................................................................................................................................................ 130

5.2.1.1 Pin configuration options...............................................................................................................130

5.2.1.2 Edge and level sensitivity.............................................................................................................. 131

5.3 Interrupt pin request register...........................................................................................................................................131

5.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC).........................................................................132

5.4 Interrupt priority control register.................................................................................................................................... 133

5.4.1 IPC Status and Control Register (IPC_SC)......................................................................................................134

5.4.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)........................................................................ 135

5.4.3 Interrupt Level Setting Registers n (IPC_ILRSn)............................................................................................135

Chapter 6

System control

6.1 System device identification (SDID)..............................................................................................................................137

6.2 Universally unique identification (UUID)......................................................................................................................137

6.3 Reset and system initialization........................................................................................................................................137

6.4 System options................................................................................................................................................................138

6.4.1 BKGD pin enable.............................................................................................................................................138

6.4.2 RESET pin enable............................................................................................................................................138

6.4.3 SCI0 pin reassignment..................................................................................................................................... 138

6.4.4 SPI0 pin reassignment......................................................................................................................................139

6.4.5 IIC pins reassignments.....................................................................................................................................139

6.4.6 FTM2 channels pin reassignment.................................................................................................................... 139

6.4.7 Bus clock output pin enable.............................................................................................................................139

6.5 System interconnection...................................................................................................................................................140

6.5.1 ACMP output selection....................................................................................................................................140

6.5.2 SCI0 TxD modulation......................................................................................................................................140

6.5.3 SCI0 RxD capture............................................................................................................................................ 141

6.5.4 SCI0 RxD filter................................................................................................................................................ 141

6.5.5 RTC capture..................................................................................................................................................... 142

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6.5.6 FTM2 software synchronization...................................................................................................................... 142

6.5.7 ADC hardware trigger......................................................................................................................................142

6.6 System Control Registers................................................................................................................................................143

6.6.1 System Reset Status Register (SYS_SRS).......................................................................................................143

6.6.2 System Background Debug Force Reset Register (SYS_SBDFR)..................................................................145

6.6.3 System Device Identification Register: High (SYS_SDIDH)......................................................................... 146

6.6.4 System Device Identification Register: Low (SYS_SDIDL).......................................................................... 146

6.6.5 System Options Register 1 (SYS_SOPT1)...................................................................................................... 147

6.6.6 System Options Register 2 (SYS_SOPT2)...................................................................................................... 148

6.6.7 System Options Register 3 (SYS_SOPT3)...................................................................................................... 150

6.6.8 System Options Register 4 (SYS_SOPT4)...................................................................................................... 150

6.6.9 Illegal Address Register: High (SYS_ILLAH)................................................................................................151

6.6.10 Illegal Address Register: Low (SYS_ILLAL).................................................................................................152

6.6.11 Universally Unique Identifier Register 1 (SYS_UUID1)................................................................................152

6.6.12 Universally Unique Identifier Register 2 (SYS_UUID2)................................................................................153

6.6.13 Universally Unique Identifier Register 3 (SYS_UUID3)................................................................................153

6.6.14 Universally Unique Identifier Register 4 (SYS_UUID4)................................................................................154

6.6.15 Universally Unique Identifier Register 5 (SYS_UUID5)................................................................................154

6.6.16 Universally Unique Identifier Register 6 (SYS_UUID6)................................................................................155

6.6.17 Universally Unique Identifier Register 7 (SYS_UUID7)................................................................................155

6.6.18 Universally Unique Identifier Register 8 (SYS_UUID8)................................................................................156

Chapter 7

Parallel input/output

7.1 Introduction.....................................................................................................................................................................157

7.2 Port data and data direction.............................................................................................................................................159

7.3 Internal pullup enable..................................................................................................................................................... 160

7.4 Input glitch filter setting..................................................................................................................................................160

7.5 High current drive...........................................................................................................................................................161

7.6 Pin behavior in stop mode...............................................................................................................................................161

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7.7 Port data registers............................................................................................................................................................161

7.7.1 Port A Data Register (PORT_PTAD)..............................................................................................................162

7.7.2 Port B Data Register (PORT_PTBD).............................................................................................................. 163

7.7.3 Port C Data Register (PORT_PTCD).............................................................................................................. 163

7.7.4 Port D Data Register (PORT_PTDD)..............................................................................................................164

7.7.5 Port E Data Register (PORT_PTED)...............................................................................................................164

7.7.6 Port F Data Register (PORT_PTFD)............................................................................................................... 165

7.7.7 Port G Data Register (PORT_PTGD)..............................................................................................................165

7.7.8 Port H Data Register (PORT_PTHD)..............................................................................................................166

7.7.9 Port High Drive Enable Register (PORT_HDRVE)........................................................................................167

7.7.10 Port A Output Enable Register (PORT_PTAOE)............................................................................................168

7.7.11 Port B Output Enable Register (PORT_PTBOE)............................................................................................ 169

7.7.12 Port C Output Enable Register (PORT_PTCOE)............................................................................................ 170

7.7.13 Port D Output Enable Register (PORT_PTDOE)............................................................................................172

7.7.14 Port E Output Enable Register (PORT_PTEOE).............................................................................................173

7.7.15 Port F Output Enable Register (PORT_PTFOE)............................................................................................. 174

7.7.16 Port G Output Enable Register (PORT_PTGOE)............................................................................................175

7.7.17 Port H Output Enable Register (PORT_PTHOE)............................................................................................176

7.7.18 Port A Input Enable Register (PORT_PTAIE)................................................................................................177

7.7.19 Port B Input Enable Register (PORT_PTBIE)................................................................................................ 178

7.7.20 Port C Input Enable Register (PORT_PTCIE)................................................................................................ 179

7.7.21 Port D Input Enable Register (PORT_PTDIE)................................................................................................181

7.7.22 Port E Input Enable Register (PORT_PTEIE).................................................................................................182

7.7.23 Port F Input Enable Register (PORT_PTFIE)................................................................................................. 183

7.7.24 Port G Input Enable Register (PORT_PTGIE)................................................................................................184

7.7.25 Port H Input Enable Register (PORT_PTHIE)................................................................................................185

7.7.26 Port Filter Register 0 (PORT_IOFLT0)...........................................................................................................186

7.7.27 Port Filter Register 1 (PORT_IOFLT1)...........................................................................................................187

7.7.28 Port Filter Register 2 (PORT_IOFLT2)...........................................................................................................188

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7.7.29 Port Clock Division Register (PORT_FCLKDIV).......................................................................................... 189

7.7.30 Port A Pullup Enable Register (PORT_PTAPE)............................................................................................. 190

7.7.31 Port B Pullup Enable Register (PORT_PTBPE)..............................................................................................191

7.7.32 Port C Pullup Enable Register (PORT_PTCPE)..............................................................................................192

7.7.33 Port D Pullup Enable Register (PORT_PTDPE)............................................................................................. 194

7.7.34 Port E Pullup Enable Register (PORT_PTEPE)..............................................................................................195

7.7.35 Port F Pullup Enable Register (PORT_PTFPE).............................................................................................. 196

7.7.36 Port G Pullup Enable Register (PORT_PTGPE)............................................................................................. 198

7.7.37 Port H Pullup Enable Register (PORT_PTHPE)............................................................................................. 199

Chapter 8

Clock management

8.1 Clock module..................................................................................................................................................................201

8.2 Internal clock source (ICS)............................................................................................................................................. 203

8.2.1 Function description.........................................................................................................................................203

8.2.1.1 Bus frequency divider.................................................................................................................... 204

8.2.1.2 Low power bit usage......................................................................................................................204

8.2.1.3 Internal reference clock (ICSIRCLK)............................................................................................204

8.2.1.4 Fixed frequency clock (ICSFFCLK)..............................................................................................205

8.2.1.5 BDC clock......................................................................................................................................206

8.2.2 Modes of operation.......................................................................................................................................... 206

8.2.2.1 FLL engaged internal (FEI)........................................................................................................... 207

8.2.2.2 FLL engaged external (FEE)..........................................................................................................208

8.2.2.3 FLL bypassed internal (FBI)..........................................................................................................208

8.2.2.4 FLL bypassed internal low power (FBILP)................................................................................... 208

8.2.2.5 FLL bypassed external (FBE)........................................................................................................209

8.2.2.6 FLL bypassed external low power (FBELP)................................................................................. 209

8.2.2.7 Stop (STOP)...................................................................................................................................210

8.2.3 FLL lock and clock monitor.............................................................................................................................211

8.2.3.1 FLL clock lock...............................................................................................................................211

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8.2.3.2 External reference clock monitor...................................................................................................211

8.3 Initialization / application information........................................................................................................................... 211

8.3.1 Initializing FEI mode....................................................................................................................................... 212

8.3.2 Initializing FBI mode.......................................................................................................................................212

8.3.3 Initializing FEE mode...................................................................................................................................... 212

8.3.4 Initializing FBE mode......................................................................................................................................213

8.3.5 External oscillator (OSC).................................................................................................................................213

8.3.5.1 Bypass mode.................................................................................................................................. 214

8.3.5.2 Low-power configuration.............................................................................................................. 214

8.3.5.3 High-gain configuration.................................................................................................................215

8.3.5.4 Initializing external oscillator for peripherals................................................................................215

8.4 1 kHz low-power oscillator (LPO)................................................................................................................................. 216

8.5 Peripheral clock gating................................................................................................................................................... 216

8.6 ICS control registers....................................................................................................................................................... 216

8.6.1 ICS Control Register 1 (ICS_C1).................................................................................................................... 217

8.6.2 ICS Control Register 2 (ICS_C2).................................................................................................................... 218

8.6.3 ICS Control Register 3 (ICS_C3).................................................................................................................... 219

8.6.4 ICS Control Register 4 (ICS_C4).................................................................................................................... 219

8.6.5 ICS Status Register (ICS_S)............................................................................................................................ 220

8.6.6 OSC Status and Control Register (ICS_OSCSC)............................................................................................ 221

8.7 System clock gating control registers............................................................................................................................. 222

8.7.1 System Clock Gating Control 1 Register (SCG_C1).......................................................................................223

8.7.2 System Clock Gating Control 2 Register (SCG_C2).......................................................................................224

8.7.3 System Clock Gating Control 3 Register (SCG_C3).......................................................................................225

8.7.4 System Clock Gating Control 4 Register (SCG_C4).......................................................................................226

Chapter 9

Chip configurations

9.1 Introduction.....................................................................................................................................................................229

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