Freescale Semiconductor MPC8349E PowerQUICC II Pro Manual de usuario

Freescale Semiconductor

Technical Data

The MPC8349E PowerQUICC™ II Pro is a next generation

PowerQUICC II integrated host processor. The MPC8349E

contains a PowerPC™ processor core built on Power

Architecture™ technology with system logic for

networking, storage, and general-purpose embedded

applications. For functional characteristics of the processor,

refer to the MPC8349E PowerQUICC™ II Pro Integrated

Host Processor Reference Manual.

To locate published errata or updates for this document,refer

to the MPC8349E product summary page on our website

listed on the back cover of this document or, contact your

local Freescale sales office.

NOTE

The information in this document is accurate for

revision 1.1 silicon and earlier. For information on

revision 3.0silicon and later versions(for orderable

part numbers ending in A or B), see the

MPC8349EA PowerQUICC™ II Pro Integrated

Host Processor Hardware Specifications.

See Section 23.1, “Part Numbers Fully Addressed

by This Document,” for silicon revision level

determination.

Document Number: MPC8349EEC

Rev. 10, 07/2007

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13

6. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8. Ethernet: Three-Speed Ethernet, MII Management . 21

9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

12. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

16. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

18. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 54

19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

21. System Design Information . . . . . . . . . . . . . . . . . . . 79

22. Document Revision History . . . . . . . . . . . . . . . . . . . 83

23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 85

MPC8349E PowerQUICC™ II Pro

Integrated Host Processor Hardware

Specifications

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

2FreescaleSemiconductor

Overview

1Overview

This section provides a high-level overview of the MPC8349E features. Figure 1 shows the major

functional units within the MPC8349E.

Figure 1. MPC8349E Block Diagram

Major features of the MPC8349E are as follows:

• Embedded PowerPC e300 processor core; operates at up to 667 MHz

— High-performance, superscalar processor core

— Floating-point, integer, load/store, system register, and branch processing units

— 32-Kbyte instruction cache, 32-Kbyte data cache

— Lockable portion of L1 cache

— Dynamic power management

— Software-compatible with the other Freescale processor families that implement Power

Architecture technology

• Double data rate, DDR SDRAM memory controller

— Programmable timing for DDR-1 SDRAM

— 32- or 64-bit data interface, up to 333-MHz data rate

— Four banks of memory, each up to 1 Gbyte

— DRAM chip configurations from 64 Mbit to 1 Gbit with x8/x16 data ports

— Full error checking and correction (ECC) support

— Page mode support (up to 16 simultaneous open pages)

TSEC

Coherent System Bus

PCI1

10/100/1Gb MII, GMII, TBI,

RTBI, RGMII

SPI

Serial

IRQs

ROM

I2CI2C Interfaces TSEC

DDR

Memory Controller

Local Bus Controller

Programmable Interrupt

Controller

DUART

e300 Core

DMA Controller

Serial Peripheral

Interface

32-KbyteL1

Instruction

Cache

32-Kbyte

L1 Data

Cache

Sequencer

SEQ

64/32b PCI Controller

PCI2

0/32b PCI Controller

Security Engine

Arbiter Bus

Monitor

USB Hi-Speed

Host Device

General Purpose I/O

USB0

USB1

GPIO

SDRAM

DDR

SDRAM

DMA

MII, GMII, TBI,

RTBI, RGMII

10/100/1Gb

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor 3

Overview

— Contiguous or discontiguous memory mapping

— Read-modify-write support

— Sleep mode for self-refresh SDRAM

— Auto refresh

— On-the-fly power management using CKE

— Registered DIMM support

— 2.5-V SSTL2 compatible I/O

• Dual three-speed (10/100/1000) Ethernet controllers (TSECs)

— Dual controllers designed to comply with IEEE 802.3®, 802.3u®, 820.3x®, 802.3z®,

802.3ac® standards

— Ethernet physical interfaces:

– 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex

– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex

— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100

programming models

— 9.6-Kbyte jumbo frame support

— RMON statistics support

— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module

— MII management interface for control and status

— Programmable CRC generation and checking

• Dual PCI interfaces

— Designed to comply with PCI Specification Revision 2.2

— Data bus width options:

– Dual 32-bit data PCI interfaces operating at up to 66 MHz

– Single 64-bit data PCI interface operating at up to 66 MHz

— PCI 3.3-V compatible

— PCI host bridge capabilities on both interfaces

— PCI agent mode on PCI1 interface

— PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses and support for delayed read transactions

— Posting of processor-to-PCI and PCI-to-memory writes

— On-chip arbitration supporting five masters on PCI1, three masters on PCI2

— Accesses to all PCI address spaces

— Parity supported

— Selectable hardware-enforced coherency

— Address translation units for address mapping between host and peripheral

— Dual address cycle for target

— Internal configuration registers accessible from PCI

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

4FreescaleSemiconductor

Overview

• Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,

IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four

crypto-channels, a controller, and a set of crypto execution units (EUs):

— Public key execution unit (PKEU) :

– RSA and Diffie-Hellman algorithms

– Programmable field size up to 2048 bits

– Elliptic curve cryptography

– F2m and F(p) modes

– Programmable field size up to 511 bits

— Data encryption standard (DES) execution unit (DEU)

– DES and 3DES algorithms

– Two key (K1, K2) or three key (K1, K2, K3) for 3DES

– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rijndael symmetric-key cipher

– Key lengths of 128, 192, and 256 bits

– ECB, CBC, CCM, and counter (CTR) modes

— ARC four execution unit (AFEU)

– Stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

— Message digest execution unit (MDEU)

– SHA with 160- or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Random number generator (RNG)

— Four crypto-channels, each supporting multi-command descriptor chains

– Staticand/or dynamic assignment of crypto-executionunits through anintegrated controller

– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

• Universal serial bus (USB) dual role controller

— USB on-the-go mode with both device and host functionality

— Complies with USB specification Rev. 2.0

— Can operate as a stand-alone USB device

– One upstream facing port

– Six programmable USB endpoints

— Can operate as a stand-alone USB host controller

– USB root hub with one downstream-facing port

– Enhanced host controller interface (EHCI) compatible

– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor 5

Overview

— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)

• Universal serial bus (USB) multi-port host controller

— Can operate as a stand-alone USB host controller

– USB root hub with one or two downstream-facing ports

– Enhanced host controller interface (EHCI) compatible

– Complies with USB Specification Rev. 2.0

— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

— Direct connection to a high-speed device without an external hub

— External PHY with serial and low-pin count (ULPI) interfaces

• Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 133 MHz

— Four chip selects support four external slaves

— Up to eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller

— Three protocol engines on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user-programmable machines (UPMs)

– Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

• Programmable interrupt controller (PIC)

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for 8 external and 35 internal discrete interrupt sources

— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources

— Programmable highest priority request

— Four groups of interrupts with programmable priority

— External and internal interrupts directed to host processor

— Redirects interrupts to external INTA pin in core disable mode.

— Unique vector number for each interrupt source

• Dual industry-standard I2C interfaces

— Two-wire interface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

— System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded

hardware

• DMA controller

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

6FreescaleSemiconductor

Overview

— Four independent virtual channels

— Concurrent execution across multiple channels with programmable bandwidth control

— All channels accessible to local core and remote PCI masters

— Misaligned transfer capability

— Data chaining and direct mode

— Interrupt on completed segment and chain

• DUART

— Two 4-wire interfaces (RxD, TxD, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

• Serial peripheral interface (SPI) for master or slave

• General-purpose parallel I/O (GPIO)

— 64 parallel I/O pins multiplexed on various chip interfaces

• System timers

— Periodic interrupt timer

— Real-time clock

— Software watchdog timer

— Eight general-purpose timers

• Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan

• Integrated PCI bus and SDRAM clock generation

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor 7

Electrical Characteristics

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8349E. The MPC8349E is currently targeted to these specifications. Some of these specifications are

independent of theI/O cell, but areincluded for amore complete reference. These are not purely I/Obuffer

design specifications.

2.1 Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1 Absolute Maximum Ratings

Table 1 provides the absolute maximum ratings.

Table 1. Absolute Maximum Ratings1

Characteristic Symbol Max Value Unit Notes

Core supply voltage VDD –0.3 to 1.32 V

PLL supply voltage AVDD –0.3 to 1.32 V

DDR DRAM I/O voltage GVDD –0.3 to 3.63 V

Three-speed Ethernet I/O, MII management voltage LVDD –0.3 to 3.63 V

PCI, local bus, DUART, system control and power management, I2C,

and JTAG I/O voltage OVDD –0.3 to 3.63 V

Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 5

DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 5

Three-speed Ethernet signals LVIN –0.3 to (LVDD + 0.3) V 4, 5

Localbus,DUART, CLKIN,systemcontroland

power management, I2C, and JTAG signals OVIN –0.3 to (OVDD + 0.3) V 3, 5

PCI OVIN –0.3 to (OVDD + 0.3) V 6

Storage temperature range TSTG –55 to 150 °C

Notes:

1Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4Caution:LVIN must not exceed LVDD by more than 0.3 V. This limit can be exceededfor a maximum of20 msduring power-on

reset and power-down sequences.

5(M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

6OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as

shown in Figure 3.

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

8FreescaleSemiconductor

Electrical Characteristics

2.1.2 Power Supply Voltage Specification

Table 2 provides the recommended operating conditions for the MPC8349E. Note that the values in

Table 2 are the recommended and tested operating conditions. Proper device operation outside these

conditions is not guaranteed.

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8349E.

Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD

Table 2. Recommended Operating Conditions

Characteristic Symbol Recommended

Value Unit Notes

Core supply voltage VDD 1.2 V ± 60 mV V 1

PLL supply voltage AVDD 1.2 V ± 60 mV V 1

DDR DRAM I/O supply voltage GVDD 2.5 V ± 125 mV V

Three-speed Ethernet I/O supply voltage LVDD1 3.3 V ± 330 mV

2.5 V ± 125 mV V

Three-speed Ethernet I/O supply voltage LVDD2 3.3 V ± 330 mV

2.5 V ± 125 mV V

PCI, local bus, DUART, system control and power

management, I2C, and JTAG I/O voltage OVDD 3.3 V ± 330 mV V

Note:

1GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or

negative direction.

GND

GND – 0.3 V

GND – 0.7 V Not to Exceed 10%

G/L/OVDD + 20%

G/L/OVDD

G/L/OVDD + 5%

of tinterface1

1. tinterface refers to the clock period associated with the bus clock interface.

VIH

VIL

Note:

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor 9

Electrical Characteristics

Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8349E for the 3.3-V

signals, respectively.

Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling

2.1.3 Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

2.2 Power Sequencing

MPC8349E doesnot require the core supplyvoltage and I/O supplyvoltages to beapplied in anyparticular

order. Note that during the power ramp up, before the power supplies are stable, there may be a period of

time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O

pins are three-stated. To minimize the time that I/O pins are actively driven, it is recommended to apply

core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up.

Table 3. Output Drive Capability

Driver Type Output Impedance

(Ω)Supply

Voltage

Local bus interface utilities signals 40 OVDD = 3.3 V

PCI signals (not including PCI output clocks) 25

PCI output clocks (including PCI_SYNC_OUT) 40

DDR signal 18 GVDD = 2.5 V

TSEC/10/100 signals 40 LVDD = 2.5/3.3 V

DUART, system control, I2C, JTAG, USB 40 OVDD = 3.3 V

GPIO signals 40 OVDD = 3.3 V,

LVDD = 2.5/3.3 V

Undervoltage

Waveform

Overvoltage

Waveform

11 ns

(Min) +7.1 V

7.1 V p-to-p

(Min)

4 ns

(Max)

–3.5 V

7.1 V p-to-p

(Min)

62.5 ns+3.6 V

0 V

4 ns

(Max)

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

10 FreescaleSemiconductor

Power Characteristics

3 Power Characteristics

The estimated typical power dissipation for the MPC8349E device is shown in Table 4.

Table 4. MPC8349E Power Dissipation1

1The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 5.

Core

Frequency

(MHz)

CSB

Frequency

(MHz) Typical at TJ= 65 Typical2, 3

2Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of TJ = 105°C, and a Dhrystone benchmark

application.

3Thermal solutions may need to design to a value higher than typical power based on the end application, TAtarget, and I/O

power.

Maximum4

4Maximum power isbasedon a voltageofVDD = 1.2 V, worst caseprocess, ajunctiontemperatureof TJ=105°C, and an artificial

smoke test.

Unit

TBGA 333 333 2.0 3.0 3.2 W

166 1.8 2.8 2.9 W

400 266 2.1 3.0 3.3 W

133 1.9 2.9 3.1 W

450 300 2.3 3.2 3.5 W

150 2.1 3.0 3.2 W

500 333 2.4 3.3 3.6 W

166 2.2 3.1 3.4 W

533 266 2.4 3.3 3.6 W

133 2.2 3.1 3.4 W

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