Cypress Semiconductor MoBL CY62128E Manual de usuario

MoBL®CY62128E

1-Mbit (128K x 8) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05485 Rev. *F Revised August 4, 2008

Features

■Very high speed: 45 ns

■Temperature ranges

❐Industrial: –40°C to +85°C

❐Automotive-A: –40°C to +85°C

❐Automotive-E: –40°C to +125°C

■Voltage range: 4.5V to 5.5V

■Pin compatible with CY62128B

■Ultra low standby power

❐Typical standby current: 1 μA

❐Maximum standby current: 4 μA (Industrial)

■Ultra low active power

❐Typical active current: 1.3 mA at f = 1 MHz

■Easy memory expansion with CE1, CE2, and OE features

■Automatic power down when deselected

■CMOS for optimum speed and power

■Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and

32-pin TSOP I packages

Functional Description

The CY62128E[1] is a high performance CMOS static RAM

organized as 128K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL®) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption when addresses are not toggling. Placing the

device into standby mode reduces power consumption by more

than 99 percent when deselected (CE1 HIGH or CE2LOW). The

eight input and output pins (IO0through IO7) are placed in a high

impedance state when the device is deselected (CE1 HIGH or

CE2LOW), the outputs are disabled (OE HIGH), or a write

operation is in progress (CE1 LOW and CE2HIGH and WE LOW)

To write to the device, take Chip Enable (CE1 LOW and CE2

HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO

pins (IO0through IO7) is then written into the location specified

on the address pins (A0through A16).

To read from the device, take Chip Enable (CE1 LOW and CE2

HIGH) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the IO pins.

IO0

IO7

IO1

IO2

IO3

IO4

IO5

IO6

A12

SENSE AMPS

POWER

DOWN

A13

A14

A15

A16

ROW DECODER

COLUMN DECODER

128K x 8

ARRAY

INPUT BUFFER

A10

A11

CE1

CE2

Logic Block Diagram

Note

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

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MoBL®CY62128E

Document #: 38-05485 Rev. *F Page 2 of 12

Pin Configuration[2]

Product Portfolio

Product Range VCC Range (V) Speed

(ns)

Power Dissipation

Operating ICC (mA)

Standby ISB2 (µA)

f = 1MHz f = fmax

Min Typ[3] Max Typ[3] Max Typ[3] Max Typ[3] Max

CY62128ELL Ind’l/Auto-A 4.5 5.0 5.5 45 [4] 1.3 2 11 16 1 4

CY62128ELL Auto-E 4.5 5.0 5.5 55 1.3 4 11 35 1 30

A16

A14

A12

VCC

A13

STSOP

Top View

(not to scale)

IO2

IO1

GND

IO7

IO4

IO5

IO6

IO0

CE1

A11

A59

CE2

A15

A10

IO3

A16

A14

A12

VCC

A13

TSOP I

Top View

(not to scale)

IO2

IO1

GND

IO7

IO4

IO5

IO6

IO0

CE1

A11

A517

CE2

A15

A10

IO3

32-Pin SOIC

Top View

VSS

VCC

CE1

Notes

2. NC pins are not connected on the die.

3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.

4. When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times of 55 ns (tAA, tACE) and 25 ns (tDOE) are guaranteed.

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MoBL®CY62128E

Document #: 38-05485 Rev. *F Page 3 of 12

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Supply Voltage to Ground

Potential............................... –0.5V to 6.0V (VCC(max) + 0.5V)

DC Voltage Applied to Outputs

in High-Z State[5, 6] .............. –0.5V to 6.0V (VCC(max) + 0.5V)

DC Input Voltage[5, 6] ........... –0.5V to 6.0V (VCC(max) + 0.5V)

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage........................................... > 2001V

(MIL-STD-883, Method 3015)

Latch up Current.....................................................> 200 mA

Operating Range

Device Range Ambient

Temperature VCC[7]

CY62128ELL Ind’l/Auto-A –40°C to +85°C 4.5V to 5.5V

Auto-E –40°C to +125°C

Electrical Characteristics (Over the Operating Range)

Parameter Description Test Conditions 45 ns (Ind’l/Auto-A) 55 ns (Auto-E) Unit

Min Typ[3] Max Min Typ[3] Max

VOH Output HIGH

Voltage

IOH = –1 mA 2.4 2.4 V

VOL Output LOW

Voltage

IOL = 2.1 mA 0.4 0.4 V

VIH Input HIGH Voltage VCC = 4.5V to 5.5V 2.2 VCC + 0.5 2.2 VCC + 0.5 V

VIL Input LOW voltage VCC = 4.5V to 5.5V –0.5 0.8 –0.5 0.8 V

IIX Input Leakage

Current

GND < VI< VCC –1 +1 –4 +4 μA

IOZ Output Leakage

Current

GND < VO <VCC, Output Disabled –1 +1 –4 +4 μA

ICC VCC Operating

Supply Current

f = fmax = 1/tRC VCC = VCC(max)

IOUT = 0 mA

CMOS levels

11 16 11 35 mA

f = 1 MHz 1.3 2 1.3 4

ISB2 [8] Automatic CE

Power down

Current—CMOS

Inputs

CE1> VCC – 0.2V or CE2< 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V,

f = 0, VCC = VCC(max)

14 130μA

Capacitance (For all Packages) [9]

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = VCC(typ)

10 pF

COUT Output Capacitance 10 pF

Notes

5. VIL(min) = –2.0V for pulse durations less than 20 ns.

6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.

7. Full device AC operation assumes a 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization.

8. Only chip enables (CE1and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.

9. Tested initially and after any design or process changes that may affect these parameters.

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MoBL®CY62128E

Document #: 38-05485 Rev. *F Page 4 of 12

AC Test Loads and Waveform

Thermal Resistance[9]

Parameter Description Test Conditions SOIC

Package

STSOP

Package

TSOP

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Still Air, soldered on a 3 × 4.5 inch,

two-layer printed circuit board

48.67 32.56 33.01 °C/W

ΘJC Thermal Resistance

(Junction to Case)

25.86 3.59 3.42 °C/W

3.0V

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

Rise Time = 1 V/ns Fall Time = 1 V/ns

OUTPUT V

Equivalent to: THEVENIN EQUIVALENT

ALL INPUT PULSES

RTH

Parameters Value Unit

R1 1800 Ω

R2 990 Ω

RTH 639 Ω

VTH 1.77 V

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min Typ[3] Max Unit

VDR VCC for Data Retention 2 V

ICCDR [8] Data Retention Current VCC= VDR, CE1> VCC − 0.2V or CE2< 0.2V,

VIN > VCC - 0.2V or VIN < 0.2V

Ind’l/Auto-A 4 μA

Auto-E 30 μA

tCDR [9] Chip Deselect to Data

Retention Time

0ns

tR [10] Operation Recovery

Time

tRC ns

Data Retention Waveform[11]

VCC(min)

tCDR

VDR >2.0V

DATA RETENTION MODE

VCC

Notes

10. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.

11. CE is the logical combination of CE1and CE2. When CE1is LOW and CE2 is HIGH, CE is LOW; when CE1is HIGH or CE2is LOW, CE is HIGH.

Notes

10. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.

11. CE is the logical combination of CE1and CE2. When CE1is LOW and CE2 is HIGH, CE is LOW; when CE1is HIGH or CE2is LOW, CE is HIGH.

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Document #: 38-05485 Rev. *F Page 5 of 12

Switching Characteristics (Over the Operating Range)[12]

Parameter Description 45 ns (Ind’l/Auto-A) 55 ns (Auto-E) Unit

Min Max Min Max

Read Cycle

tRC Read Cycle Time 45 55 ns

tAA Address to Data Valid 45 55 ns

tOHA Data Hold from Address Change 10 10 ns

tACE CE1LOW and CE2HIGH to Data Valid 45 55 ns

tDOE OE LOW to Data Valid 22 25 ns

tLZOE OE LOW to Low-Z[13] 55ns

tHZOE OE HIGH to High-Z[13, 14] 18 20 ns

tLZCE CE1LOW and CE2HIGH to Low-Z[13] 10 10 ns

tHZCE CE1HIGH or CE2LOW to High-Z[13, 14] 18 20 ns

tPU CE1LOW and CE2HIGH to Power Up 0 0ns

tPD CE1HIGH or CE2LOW to Power Down 45 55 ns

Write Cycle[15]

tWC Write Cycle Time 45 55 ns

tSCE CE1LOW and CE2HIGH to Write End 35 40 ns

tAW Address Setup to Write End 35 40 ns

tHA Address Hold from Write End 0 0ns

tSA Address Setup to Write Start 0 0 ns

tPWE WE Pulse Width 35 40 ns

tSD Data Setup to Write End 25 25 ns

tHD Data Hold from Write End 0 0 ns

tHZWE WE LOW to High-Z[13, 14] 18 20 ns

tLZWE WE HIGH to Low-Z[13] 10 10 ns

Notes

12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse

levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the “” on page 4.

13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

14. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.

15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can

terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

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Document #: 38-05485 Rev. *F Page 6 of 12

Switching Waveforms

Figure 1. Read Cycle 1 (Address Transition Controlled) [16, 17]

Figure 2. Read Cycle No. 2 (OE Controlled) [11, 17, 18]

Figure 3. Write Cycle No. 1 (WE Controlled) [11, 15, 19, 20]

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tHZCE

tPD

IMPEDANCE

ICC

ISB

HIGH

ADDRESS

DATA OUT

VCC

SUPPLY

CURRENT

DATA VALID

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

ADDRESS

DATA IO

NOTE

Notes:

16. The device is continuously selected. OE, CE1= VIL, CE2= VIH.

17. WE is HIGH for read cycle.

18. Address valid before or similar to CE1transition LOW and CE2transition HIGH.

19. Data IO is high impedance if OE = VIH.

20. If CE1goes HIGH or CE2goes LOW simultaneously with WE HIGH, the output remains in high impedance state.

21. During this period, the IOs are in output state and input signals must not be applied.

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MoBL®CY62128E

Document #: 38-05485 Rev. *F Page 7 of 12

Figure 4. Write Cycle No. 2 (CE1 or CE2 Controlled) [11, 15, 19, 20]

Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW) [11, 20]

Truth Table

CE1CE2WE OE Inputs/Outputs Mode Power

H X X X High-Z Deselect/Power down Standby (ISB)

X L X X High-Z Deselect/Power down Standby (ISB)

L H H L Data Out Read Active (ICC)

L H L X Data In Write Active (ICC)

L H H H High-Z Selected, Outputs Disabled Active (ICC)

Switching Waveforms (continued)

tWC

DATA VALID

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

ADDRESS

DATA IO

DATA VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

ADDRESS

DATA IO

NOTE

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MoBL®CY62128E

Document #: 38-05485 Rev. *F Page 8 of 12

Package Diagrams

Figure 6. 32-pin (450 Mil) Molded SOIC (51-85081)

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

45 CY62128ELL-45SXI 51-85081 32-pin 450-Mil SOIC (Pb-free) Industrial

CY62128ELL-45ZAXI 51-85094 32-pin STSOP (Pb-free)

CY62128ELL-45ZXI 51-85056 32-pin TSOP Type I (Pb-free)

45 CY62128ELL-45SXA 51-85081 32-pin 450-Mil SOIC (Pb-free) Automotive-A

CY62128ELL-45ZXA 51-85056 32-pin TSOP Type I (Pb-free)

55 CY62128ELL-55SXE 51-85081 32-pin 450-Mil SOIC (Pb-free) Automotive-E

CY62128ELL-55ZAXE 51-85094 32-pin STSOP (Pb-free)

Contact your local Cypress sales representative for availability of these parts.

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MoBL®CY62128E

Document #: 38-05485 Rev. *F Page 9 of 12

Figure 7. 32-pin Shrunk Thin Small Outline Package (8 x 13.4 mm) (51-85094)

51-85094-*D

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Document #: 38-05485 Rev. *F Page 10 of 12

Figure 8. 32-pin Thin Small Outline Package Type I (8 x 20 mm) (51-85056)

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