Cypress Semiconductor Perform CY7C132 Manual de usuario

2K x 8 Dual-Port Static RAM

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-06031 Rev. *E Revised March 24, 2009

Features

■Truedual-portedmemorycellsthatenablesimultaneousreads

of the same memory location

■2K x 8 organization

■0.65 micron CMOS for optimum speed and power

■High speed access: 15 ns

■Low operating power: ICC = 110 mA (maximum)

■Fully asynchronous operation

■Automatic power down

■MasterCY7C132/CY7C136/CY7C136A[1]easilyexpandsdata

bus width to 16 or more bits using slave CY7C142/CY7C146

■BUSY output flag on CY7C132/CY7C136/CY7C136A;

BUSY input on CY7C142/CY7C146

■INT flag for port to port communication (52-Pin PLCC/PQFP

versions)

■CY7C136, CY7C136A, and CY7C146 available in 52-pin

PLCC and 52-pin PQFP packages

■Pb-free packages available

Functional Description

TheCY7C132,CY7C136,CY7C136A, CY7C142, and CY7C146

are high speed CMOS 2K x 8 dual-port static RAMs. Two ports

are provided to permit independent access to any location in

memory. The CY7C132, CY7C136, and CY7C136A can be used

as either a standalone 8-bit dual-port static RAM or as a

MASTER dual-port RAM, in conjunction with the

CY7C142/CY7C146 SLAVE dual-port device. They are used in

systems that require 16-bit or greater word widths. This is the

solutiontoapplications thatrequiresharedorbuffereddata,such

as cache memory for DSP, bit-slice, or multiprocessor designs.

Each port has independent control pins; chip enable (CE), write

enable (R/W), and output enable (OE). BUSY flags are provided

on each port. In addition, an interrupt flag (INT) is provided on

each port of the 52-pin PLCC version. BUSY signals that the port

is trying to access the same location currently being accessed

by the other port. On the PLCC version, INT is an interrupt flag

indicating that data is placed in an unique location (7FF for the

left port and 7FE for the right port).

An automatic power down feature is controlled independently on

each port by the chip enable (CE) pins.

R/WL

BUSYL

CEL

OEL

A10L

A0L A0R

A10R

R/WR

CER

OER

CER

OER

CEL

OEL

R/WLR/WR

I/O7L

I/O0L

I/O7R

I/O0R

BUSYR

INTLINTR

ARBITRATION

LOGIC

(7C132/7C136 ONLY)

AND

INTERRUPTLOGIC

(7C136/7C146ONLY)

CONTROL

I/O CONTROL

I/O

MEMORY

ARRAY ADDRESS

DECODER

ADDRESS

DECODER

[2]

[3] [3]

[2]

Logic Block Diagram

Notes

1. CY7C136 and CY7C136A are functionally identical.

2. CY7C132/CY7C136/CY7C136A (Master): BUSY is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input.

3. Open drain outputs; pull up resistor required.

[+] Feedback

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Document #: 38-06031 Rev. *E Page 2 of 15

Pinouts

Figure 1. 52-Pin PLCC (Top View) Figure 2. 52-Pin PQFP (Top View)

Selection Guide

Specification 7C136-15[4]

7C146-15

7C132-25 [4]

7C136-25

7C142-25

7C146-25

7C132-30

7C136-30

7C142-30

7C146-30

7C132-35

7C136-35

7C142-35

7C146-35

7C132-45

7C136-45

7C142-45

7C146-45

7C132-55

7C136-55

7C136A-55

7C142-55

7C146-55

Unit

Maximum Access Time 15 25 30 35 45 55 ns

Maximum Operating Current Com’l/Ind 190 170 170 120 120 110 mA

Maximum Standby Current Com’l/Ind 75 65 65 45 45 35 mA

Shaded areas contain preliminary information.

VCC

OER

A0R

2122 23 24 25 26 27 28 29 30 31 32 33

7 6 5 4 3 2 52 51 50 49 48 47

A1R

A2R

A3R

A4R

A5R

A6R

A7R

A8R

A9R

I/O7R

A1L

A2L

A3L

A4L

A5L

A6L

A7L

A8L

A9L

I/O0L

I/O1L

I/O2L

I/O3L

I/O

GND

BUSY

INT

R/W

BUSY

INT

CER

7C136/7C136A

7C146

10L

A10R

1415 16 17 18 19 20 21 22 23 24 25 26

52 51 50 49 48 47 45 44 43 42 41 40

VCC

BUSY

INT

R/W

BUSY

INT

CER

OER

A0R

A1R

A2R

A3R

A4R

A5R

A6R

A7R

A8R

A9R

I/O7R

A1L

A2L

A3L

A4L

A5L

A6L

A7L

A8L

A9L

I/O0L

I/O1L

I/O2L

I/O3L

I/O

GND

7C136/7C136A

7C146

10L

A10R

Note:

4. 15 ns and 25 ns version available in PQFP and PLCC packages only.

[+] Feedback

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Document #: 38-06031 Rev. *E Page 3 of 15

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ..................................... −65°C to +150°C

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Supply Voltage to Ground Potential

(Pin 48 to Pin 24).................................................−0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State.....................................................−0.5V to +7.0V

DC Input Voltage................................................. −3.5V to +7.0V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch up Current.................................................... >200mA

Operating Range

Range Ambient Temperature VCC

Commercial 0°C to +70°C 5V ± 10%

Industrial –40°C to +85°C 5V ± 10%

Notes

5. BUSY and INT pins only.

6. Duration of the short circuit should not exceed 30 seconds.

7. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V.

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions 7C136-15[4]

7C146-15

7C132-30[4]

7C136-25, 30

7C142-30

7C146-25, 30

7C132-35,45

7C136-35,45

7C142-35,45

7C146-35,45

7C132-55

7C136-55

7C136A-55

7C142-55

7C146-55 Unit

Min Max Min Max Min Max Min Max

VOH Output HIGH

voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 2.4 V

VOL Output LOW

voltage IOL = 4.0 mA 0.4 0.4 0.4 0.4 V

IOL = 16.0 mA[5] 0.5 0.5 0.5 0.5

VIH Input HIGH

voltage 2.2 2.2 2.2 2.2 V

VIL Input LOW

voltage 0.8 0.8 0.8 0.8 V

IIX Input load current GND < VI<VCC –5 +5 −5+5−5+5−5+5μA

IOZ Output leakage

current GND < VO<VCC,Output Disabled –5 +5 −5+5−5+5−5+5μA

IOS Output short

circuit current[6] VCC = Max., VOUT = GND –350 −350 −350 −350 mA

ICC VCC Operating

Supply Current CE = VIL, Outputs Open,

f = fMAX[7] Com’l/

Ind’l 190 170 120 110 mA

ISB1 Standby current

both ports, TTL

Inputs

CELand CER> VIH,

f = fMAX[7] Com’l/

Ind’l 75 65 45 35 mA

ISB2 Standby Current

One Port,

TTL Inputs

CELor CER> VIH,

Active Port Outputs Open,

f = fMAX[7]

Com’l/

Ind’l 135 115 90 75 mA

ISB3 Standby Current

Both Ports,

CMOS Inputs

Both Ports CELand

CER >VCC – 0.2V, VIN > VCC – 0.2V

or VIN < 0.2V, f = 0

Com’l/

Ind’l 15 15 15 15 mA

ISB4 Standby Current

One Port,

CMOS Inputs

One Port CELor CER> VCC – 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V,

Active Port Outputs Open, f = fMAX[7]

Com’l/

Ind’l 125 105 85 70 mA

Shaded areas contain preliminary information.

[+] Feedback

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Document #: 38-06031 Rev. *E Page 4 of 15

Capacitance

This parameter is guaranteed but not tested.

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz, VCC = 5.0V 15 pF

COUT Output Capacitance 10 pF

Figure 3. AC Test Loads and Waveforms

3.0V

OUTPUT

R1 893Ω

347Ω

30 pF

INCLUDING

JIG AND

SCOPE

GND 90% 90%

10%

<5ns <5ns

OUTPUT

R1 893Ω

347Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT 1.4V

Equivalent to: THÉVENIN EQUIVALENT

281Ω

30 pF

BUSY

INT

BUSY Output Load

(CY7C132/CY7C136 Only)

10%

ALL INPUT PULSES

250Ω

Switching Characteristics

Over the Operating Range (Speeds -15, -25, -30) [8]

Parameter Description 7C136-15 [4]

7C146-15

7C132-25 [4]

7C136-25

7C142-25

7C146-25

7C132-30

7C136-30

7C142-30

7C146-30 Unit

Min Max Min Max Min Max

Read Cycle

tRC Read Cycle Time 15 25 30 ns

tAA Address to Data Valid [9] 15 25 30 ns

tOHA Data Hold from Address Change 000ns

tACE CE LOW to Data Valid [9] 15 25 30 ns

tDOE OE LOW to Data Valid [9] 10 15 20 ns

tLZOE OE LOW to Low Z [7, 10] 333ns

tHZOE OE HIGH to High Z [7, 10, 11] 10 15 15 ns

tLZCE CE LOW to Low Z [7, 10] 355ns

tHZCE CE HIGH to High Z [7, 10, 11] 10 15 15 ns

tPU CE LOW to Power Up [7] 000ns

tPD CE HIGH to Power Down [7] 15 25 25 ns

Shaded areas contain preliminary information.

Notes

8. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH,

and 30 pF load capacitance.

9. AC test conditions use VOH = 1.6V and VOL = 1.4V.

10.At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.

11. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL= 5pF as in (b) of AC Test Loads and Waveforms.Transition is measured ± 500 mV from steady state

voltage.

[+] Feedback

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Document #: 38-06031 Rev. *E Page 5 of 15

Write Cycle[12]

tWC Write Cycle Time 15 25 30 ns

tSCE CE LOW to Write End 12 20 25 ns

tAW Address Setup to Write End 12 20 25 ns

tHA Address Hold from Write End 222ns

tSA Address Setup to Write Start 000ns

tPWE R/W Pulse Width 12 15 25 ns

tSD Data Setup to Write End 10 15 15 ns

tHD Data Hold from Write End 000ns

tHZWE R/W LOW to High Z [7] 10 15 15 ns

tLZWE R/W HIGH to Low Z [7] 000ns

Busy/Interrupt Timing

tBLA BUSY LOW from Address Match 15 20 20 ns

tBHA BUSY HIGH from Address Mismatch[13] 15 20 20 ns

tBLC BUSY LOW from CE LOW 15 20 20 ns

tBHC BUSY HIGH from CE HIGH[13] 15 20 20 ns

tPS Port Set Up for Priority 555ns

tWB R/W LOW after BUSY LOW[14] 000ns

tWH R/W HIGH after BUSY HIGH 13 20 30 ns

tBDD BUSY HIGH to Valid Data 15 25 30 ns

tDDD Write Data Valid to Read Data Valid Note 15 Note 15 Note 15 ns

tWDD Write Pulse to Data Delay Note 15 Note 15 Note 15 ns

Interrupt Timing [16]

tWINS R/W to INTERRUPT Set Time 15 25 25 ns

tEINS CE to INTERRUPT Set Time 15 25 25 ns

tINS Address to INTERRUPT Set Time 15 25 25 ns

tOINR OE to INTERRUPT Reset Time[13] 15 25 25 ns

tEINR CE to INTERRUPT Reset Time[13] 15 25 25 ns

tINR Address to INTERRUPT Reset Time[13] 15 25 25 ns

Shaded areas contain preliminary information.

Switching Characteristics

Over the Operating Range (Speeds -15, -25, -30) [8] (continued)

Parameter Description 7C136-15 [4]

7C146-15

7C132-25 [4]

7C136-25

7C142-25

7C146-25

7C132-30

7C136-30

7C142-30

7C146-30 Unit

Min Max Min Max Min Max

Notes

12.The internal write time of the memory is defined by theoverlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate

a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.

13.These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.

14.CY7C142/CY7C146 only.

15.A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:

BUSY on Port B goes HIGH.

Port B’s address toggled.

CE for Port B is toggled.

R/W for Port B is toggled during valid read.

16.52-pin PLCC and PQFP versions only.

[+] Feedback

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Document #: 38-06031 Rev. *E Page 6 of 15

Switching Characteristics

Over the Operating Range (Speeds -35, -45, -55) [8]

Parameter Description

7C132-35

7C136-35

7C142-35

7C146-35

7C132-45

7C136-45

7C142-45

7C146-45

7C132-55

7C136-55

7C136A-55

7C142-55

7C146-55 Unit

Min Max Min Max Min Max

Read Cycle

tRC Read Cycle Time 35 45 55 ns

tAA Address to Data Valid[9] 35 45 55 ns

tOHA Data Hold from Address Change 0 0 0 ns

tACE CE LOW to Data Valid[9] 35 45 55 ns

tDOE OE LOW to Data Valid[9] 20 25 25 ns

tLZOE OE LOW to Low Z[7, 10] 333ns

tHZOE OE HIGH to High Z[7, 10, 11] 20 20 25 ns

tLZCE CE LOW to Low Z[7, 10] 555ns

tHZCE CE HIGH to High Z[7, 10, 11] 20 20 25 ns

tPU CE LOW to Power Up[7] 000ns

tPD CE HIGH to Power Down[7] 35 35 35 ns

Write Cycle[12]

tWC Write Cycle Time 35 45 55 ns

tSCE CE LOW to Write End 30 35 40 ns

tAW Address Setup to Write End 30 35 40 ns

tHA Address Hold from Write End 2 2 2 ns

tSA Address Setup to Write Start 0 0 0 ns

tPWE R/W Pulse Width 25 30 30 ns

tSD Data Setup to Write End 15 20 20 ns

tHD Data Hold from Write End 0 0 0 ns

tHZWE R/W LOW to High Z [7] 20 20 25 ns

tLZWE R/W HIGH to Low Z [7] 000ns

Busy/Interrupt Timing

tBLA BUSY LOW from Address Match 20 25 30 ns

tBHA BUSY HIGH from Address Mismatch[13] 20 25 30 ns

tBLC BUSY LOW from CE LOW 20 25 30 ns

tBHC BUSY HIGH from CE HIGH[13] 20 25 30 ns

tPS Port Set Up for Priority 5 5 5 ns

tWB R/W LOW after BUSY LOW[14] 000ns

tWH R/W HIGH after BUSY HIGH 30 35 35 ns

tBDD BUSY HIGH to Valid Data 35 45 45 ns

tDDD Write Data Valid to Read Data Valid Note 15 Note 15 Note 15 ns

tWDD Write Pulse to Data Delay Note 15 Note 15 Note 15 ns

[+] Feedback

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Document #: 38-06031 Rev. *E Page 7 of 15

Interrupt Timing [16]

tWINS R/W to INTERRUPT Set Time 25 35 45 ns

tEINS CE to INTERRUPT Set Time 25 35 45 ns

tINS Address to INTERRUPT Set Time 25 35 45 ns

tOINR OE to INTERRUPT Reset Time[13] 25 35 45 ns

tEINR CE to INTERRUPT Reset Time[13] 25 35 45 ns

tINR Address to INTERRUPT Reset Time[13] 25 35 45 ns

Switching Characteristics

Over the Operating Range (Speeds -35, -45, -55) [8] (continued)

Parameter Description

7C132-35

7C136-35

7C142-35

7C146-35

7C132-45

7C136-45

7C142-45

7C146-45

7C132-55

7C136-55

7C136A-55

7C142-55

7C146-55 Unit

Min Max Min Max Min Max

Switching Waveforms

Figure 4. Read Cycle No. 1 (Either Port-Address Access) [17, 18]

Figure 5. Read Cycle No. 2 (Either Port-CE/OE )[17, 19]

tRC

tAA

tOHA

DATA VALIDPREVIOUS DATA VALID

DATA OUT

ADDRESS

tACE

tLZOE tDOE tHZOE

tHZCE

DATA VALID

DATA OUT

tLZCE

tPU

ICC

ISB

tPD

Notes

17.R/W is HIGH for read cycle.

18.Device is continuously selected, CE = VIL and OE = VIL.

19.Address valid prior to or coincident with CE transition LOW.

[+] Feedback

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Document #: 38-06031 Rev. *E Page 8 of 15

Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A)

Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port) [12, 20]

Switching Waveforms (continued)

tBHA

tBDD

VALID

tDDD

tWDD

ADDRESS MATCH

R/WR

ADDRESSR

DINR

ADDRESSL

BUSYL

DOUTL

tPS

tBLA

tRC

tPWE

VALID

tAW

tWC

DATA VALID

HIGH IMPEDANCE

tSCE

tSA tPWE

tHD

tSD

tHA

tHZOE

R/W

ADDRESS

DOUT

DATAIN

Note

20.If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance

and for data to be placed on the bus for the required tSD.

[+] Feedback

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Document #: 38-06031 Rev. *E Page 9 of 15

Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[12, 21]

Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)

Switching Waveforms (continued)

tAW

tWC

tSCE

tSA tPWE

tHD

tSD

tHZWE

tHA

HIGH IMPEDANCE

R/W

ADDRESS

DOUT

DATAIN

tLZWE

DATA VALID

ADDRESS MATCH

tPS

CEL Valid First:

tBLC tBHC

ADDRESS MATCH

tPS

tBLC tBHC

BUSYL

CER

CEL

ADDRESSL,R

BUSYR

CEL

CER

ADDRESSL,R

CER Valid First:

Note

21.If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.

[+] Feedback

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Document #: 38-06031 Rev. *E Page 10 of 15

Figure 10. Busy Timing Diagram No. 2 (Address Arbitration)

Figure 11. Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)

Switching Waveforms (continued)

Left Address Valid First:

ADDRESS MATCH

tPS

ADDRESSL

BUSYR

ADDRESS MISMATCH

tRCor tWC

tBLA tBHA

ADDRESSR

ADDRESS MATCH ADDRESS MISMATCH

tPS

ADDRESSL

BUSYL

tRCor tWC

tBLA tBHA

ADDRESSR

Right Address Valid First:

tPWE

tWB tWH

BUSY

R/W

[+] Feedback

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