NXP Semiconductors UM11650 Manual de usuario
UM11650
KIT-TPLSNIFEVB tool
Rev. 2 — 23 June 2023 User manual
Document information
Information Content
Keywords TPL, ETPL, electrical transport protocol link, decoder, TPL sniffer
Abstract This document helps users understand how to use the KIT-TPLSNIFEVB to acquire ETPL
communications.
NXP Semiconductors UM11650
KIT-TPLSNIFEVB tool
Rev Date Description
2 20230623 •Updated vocabulary throughout the document
•Updated mentions of software decoder available throughout the document
1 20210804 initial version
Revision history
IMPORTANT NOTICE
For engineering development or evaluation purposes only
NXP provides the product under the following conditions:
This evaluation kit is for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES
ONLY.
It is provided as a sample IC pre-soldered to a printed-circuit board to make it easier to access inputs,
outputs and supply terminals. This evaluation board may be used with any development system or
other source of I/O signals by connecting it to the host MCU computer board via off-the-shelf cables.
This evaluation board is not a Reference Design and is not intended to represent a final design
recommendation for any particular application. Final device in an application heavily depends on
proper printed-circuit board layout and heat sinking design as well as attention to supply filtering,
transient suppression, and I/O signal quality.
The product provided may not be complete in terms of required design, marketing, and or
manufacturing related protective considerations, including product safety measures typically found
in the end device incorporating the product. Due to the open construction of the product, it is the
responsibility of the user to take all appropriate precautions for electric discharge. In order to minimize
risks associated with the customers’ applications, adequate design and operating safeguards must be
provided by the customer to minimize inherent or procedural hazards. For any safety concerns, contact
NXP sales and technical support services.
UM11650 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
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KIT-TPLSNIFEVB tool
1 Introduction
The KIT-TPLSNIFEVB, also called transport protocol link (TPL) sniffer is working with a logic analyzer
(preferably a Saleae logic analyzer) and its software to help analyze electrical transport protocol link (ETPL)
signals.
Figure 1. KIT-TPLSNIFEVB
Placed in any ETPL bus, it non-intrusively listens to all messages and monitors the frame traffic on the bus (the
TPL sniffer works in listen mode only). The corresponding received data [in serial peripheral interface (SPI)
format] is available on the analyzer output connector (see Figure 6), to be connected to a logic analyzer and its
software which provides further analysis of such data.
Additionally, plug-ins and extensions for the Saleae logic analyzer software are available to decode TPL frames.
Visit http://www.nxp.com/KIT-TPLSNIFEVB for additional details.
UM11650 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 2 — 23 June 2023
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NXP Semiconductors UM11650
KIT-TPLSNIFEVB tool
aaa-042711
HARDWARE
SETUP
HARDWARE
SETUP
OPTIONAL
POWER
BANK
HARDWARE
SETUP
Hardware setup without TPL sniffer:
HARDWARE
SETUP
TPL sniffer
KIT-TPLSNIFEVB
COMPUTER
LOGIC
ANALYZER
Two-twisted-wire
ETPL cable
Two-twisted-wire
ETPL cable
Two-twisted-wire
ETPL cable (optional in case
of daisy chain)
ETPL bus
ETPL bus
USB cable
or
With optional:
- Saleae Logic Analyzer Software
- NXP TPL decoder extensions
Micro-USB
port
8-pin connectors cable
Figure 2. TPL sniffer toolchain
Note: This product has not undergone formal EU electromagnetic compatibility (EMC) assessment. As a
component used in a research environment, it is the responsibility of the user to ensure the finished assembly
does not cause undue interference when used and cannot be CE marked unless assessed.
2 Finding kit resources and information on the NXP website
NXP Semiconductors provides online resources for this tool and its supported devices on its website. The
information page for the KIT-TPLSNIFEVB tool provides overview information, documentation, software
and tools, parametrics, ordering information and a Getting Started tab. The Getting Started tab provides
quick‑reference information applicable to using the KIT-TPLSNIFEVB tool, including the downloadable assets
referenced in this document.
2.1 Collaborate in the NXP community
The NXP community is for sharing ideas and tips, ask and answer technical questions, and receive input on just
about any embedded design topic.
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KIT-TPLSNIFEVB tool
3 Getting ready
3.1 Kit contents
•Assembled and tested TPL sniffer dongle in anti-static bag
•A logic analyzer connection cable with 8-pin headers
•An ETPL bus connection twisted cable with 2-pin headers
Figure 3. Kit contents
3.2 Additional hardware and software
The TPL sniffer requires only a 5.0 V with 50 mA (average) and 150 mA (peak) power supply through a USB
Micro-B connector (for example, a power bank, or a USB cable connected to a computer).
To analyze the data sourced from the TPL sniffer a logic analyzer (for example, Saleae logic analyzer) is
required along with its software.
Optionally, plug-ins and extensions to add to the Saleae logic analyzer software have been developed in order
to decode TPL frames. For additional details, go to http://www.nxp.com/KIT-TPLSNIFEVB.
4 Getting to know the hardware
4.1 KIT-TPLSNIFEVB features
•Internal galvanic isolation between the ETPL function and rest of the circuits
•Connection to any point of the monitored ETPL bus
•Minimal loading of the ETPL line
•Logic analyzer connection, with a provided cable pin-to-pin compatible with the Saleae Logic 8 and Logic Pro
8/16 analyzer series
•Powered through a USB connector by a 5.0 V source, typically a USB power bank, or a USB cable connected
to a computer
•Integrated keep-alive function to avoid power bank self shut-off
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KIT-TPLSNIFEVB tool
4.2 Block diagram
aaa-042712
TPL
MC33664
The TPL sniffer interfaces the TPL bus
with transformer isolation
TPL frames are received and sent in SPI
format by the MC33664 and buffered by the
cable driver
Internal power supplies generate the required 3.3 V and 5 V
and implement a pulsed load to provide the power bank
keep-alive function
TPL_IN
TPL_OUT
CABLE
DRIVER
CHARGE
PUMP LDO
Galvanic isolation
MICRO-USBCONN
4x2
PULSED
LOAD
5 V
3.3 V
C
O
NN
2x1CONN 2
x1
Figure 4. TPL sniffer block diagram
4.3 Schematics
The schematics for the KIT-TPLSNIFEVB tool are available at http://www.nxp.com/KIT-TPLSNIFEVB.
5 Configuring the hardware
The TPL sniffer exposes a set of connectors on two sides. One side is dedicated to the ETPL bus connection
and on the other side all other connectors are present. The two sides are galvanically isolated from each other:
the ETPL bus connectors are isolated from all other accessible points on the housing.
5.1 Connecting to the ETPL bus
As shown in Figure 4, the ETPL connectors are on one side of the housing and are marked TPL_IN and
TPL_OUT with a polarity indication + and −. The correct polarity of the connection is mandatory for the proper
functioning of the sniffer and, in most cases, also for the system to be sniffed.
Conversely, the terms IN and OUT are conventional and the two connectors are electrically in parallel inside
the TPL sniffer. They are physically duplicated to make it easier to connect the wires in certain use cases. If
there is a daisy chain, the original ETPL bus is cut and the two ends must be plugged onto the receptacles of
the TPL sniffer shown in Figure 5. In other cases, for example, when the ETPL bus has only one differential
end available for connection to the TPL sniffer, there is no difference between the TPL_IN and TPL_OUT
connectors, as long as the polarity is respected.
As a rule, if a stub is created from the original ETPL bus, its length should be as short as possible.
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NXP Semiconductors UM11650
KIT-TPLSNIFEVB tool
Note: The two ETPL interface connectors are named J1 and J2 in the schematic diagram.
Figure 5. ETPL bus connectors
5.1.1 Optional ETPL bus loading
The TPL sniffer is designed to add minimal load to the ETPL bus by default. Therefore, it does not add any
termination impedance and the differential load seen from the bus is that of an input impedance of the MC33664
reflected on the high-voltage side by the 1 : 1 ratio T1 isolation transformer.
If an interface other than the default one is desired, some settings are possible on the printed-circuit board
(PCB):
•The two jumpers JP1 and JP2 on the bottom side, should be closed (with a drop of solder) if a standard 150 Ω
termination is desired.
•Additional component footprints are available on the top side of the PCB to accommodate different loads on
the ETPL bus interface. These footprints are R13 [default do not populate (DNP)] and R14 and R15 (default
0 Ω).
Note: If the board must be modified and then powered without housing, proceed with caution.
5.2 Power and data connections
The side of the case opposite the ETPL connectors has all the other available connectors of the TPL sniffer.
•The GND banana plug: used to connect, if necessary, the GND of the TPL sniffer to another potential. It is
labeled J5 in the schematics.
In some cases of use, the whole system including, for example, the TPL sniffer, the power supply, the logic
analyzer, and the associated PC, could be an electrically floating block. This connector allows the ground
potential of the system (the TPL sniffer and anything else that has its ground connected to the TPL sniffer
ground) to be set to any other convenient potential: the protective earth or the vehicle chassis ground (KL31).
•The data-out 8-pin connector: buffered SPI signals to be routed to the logic analyzer. It is labeled J3 in the
schematics. See Section 5.2.1 "Connecting to the logic analyzer" for more details.
•The power on LED indicator
•The USB Micro-B connector: to connect to a 5.0 V source. It is labeled J4 in the schematics.
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KIT-TPLSNIFEVB tool
Figure 6. Power and data connectors
5.2.1 Connecting to the logic analyzer
The data output connector (J3) is an 8-pin 4 × 2 male connector used as an interface to the logic analyzer, to
transfer TPL messages converted to SPI format.
The signals are all unidirectional and their direction is from the TPL sniffer (output) to the logic analyzer (input).
The TPL sniffer is designed such that the cable connection to the logic analyzer can be relatively long, with a
maximum length of 2 m. The connection is also designed to be without loss of signal integrity and therefore
maintaining the logic and timing information.
This statement is only true if the following two rules are both satisfied:
•The cable used for the connection must have a characteristic impedance of 100 Ω. This impedance is the
impedance normally found on standard IDC ribbon cables.
•The logic analyzer side of the cable should only be loaded with high-impedance terminations. These
terminations can be a high-Z input from an oscilloscope, for example, 15 pF || 1 MΩ, or 5 pF || 10 MΩ (better),
or digital inputs from a logic analyzer (for example, 10 pF || 2 MΩ).
Failure to follow these rules does not guarantee proper operation of the TPL sniffer, unless the cable length is
considerably short (< 15 cm). In this case, reflections in the cable can be neglected.
For signal integrity and electromagnetic interference (EMI) reduction, the data lines are interleaved with the
ground potential with the pinout described in Table 1.
The TPL sniffer data output lines and the ETPL inputs are internally protected by electrostatic discharge (ESD)
suppression devices. Nevertheless, standard electrostatic precautions should be taken when handling and
using the TPL sniffer.
The pin assignment for the data output connector is described in Table 1.
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NXP Semiconductors UM11650
KIT-TPLSNIFEVB tool
Pin Signal Description
1 INTB SPI interrupt signal
2 GND ground
3 RXCLK SPI bus clock
4 GND ground
5 RXDATA SPI bus data
6 GND ground
7 RXCSB SPI chip select
8 GND ground
Table 1. Analyzer connector (J3) pin assignment
Figure 7. Analyzer connector pinout
The supplied 8-pin connection cable should be plugged into the ANALYZER connector with the blue wires on
top (NXP logo side) and the black wires on the bottom.
5.2.1.1 Interfacing with the Saleae logic analyzer
The supplied 8-pin connectors cable is fitting the Saleae Logic 8 and Logic Pro 8/16 analyzer series input
connectors. To connect to the Saleae logic analyzer, the cable should be plugged with the blue wires on top
(Saleae logo side) and the black wires on the bottom.
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KIT-TPLSNIFEVB tool
Figure 8. Saleae logic analyzer
Saleae provides a software interface with its product to help decode the acquired signals. To learn more, visit
the Saleae website.
Plug-ins and extensions for the Saleae logic analyzer software are available to decode TPL frames. Visit http://
www.nxp.com/KIT-TPLSNIFEVB for more details.
5.2.2 Powering the TPL sniffer
The TPL sniffer can be powered through the USB Micro-B connector (J4, labeled PWR) by a 5.0 V source with
50 mA (average) and 150 mA (peak). This power supply can typically be a USB power bank, or a USB cable
connected to a computer.
5.2.2.1 Power bank keep-alive function
The purpose of the keep-alive feature is to avoid the activation of the automatic shutdown feature found on most
consumer USB power banks. Such a shutdown would likely occur due to the limited power consumption of the
TPL sniffer circuit alone, in the 10 mA to 20 mA range. Therefore, the sniffer activates an additional 150 mA of
internal power consumption with a period of 5.8 seconds and a duty cycle of 20 % (all figures are approximate).
This behavior simulates a load large enough to keep most power banks energized.
If the power-on LED indicator goes out shortly after the TPL sniffer is first powered up with a power bank,
consider trying another power bank model.
6 Hardware specifications
Description Value
Power supply voltage 5.0 V (± 10 %)
Power consumption < 50 mA (averaged over 20 seconds)
Table 2. Electrical characteristics
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