NXP Semiconductors MCXN 4 Series Guía

UG10092

MCXNx4x Hardware Design Guide

Rev. 1 — 19 January 2024 User guide

Document information

Information Content

Keywords UG10092, MCXNx4x, MCX N, MCX N Series, MCX N94x, MCX N54x, High-Performance

MCU, eIQ Neutron NPU, EdgeLock Secure Enclave, Dual-Core MCU, 150 MHz MCU, Artificial

Intelligence, Machine Learning, Advanced Security MCU, Secure MCU, Neural Processing Unit,

Low-Power MCU, General Purpose MCU, Arm Cortex-M33 MCU

Abstract This document aims to help hardware engineers design and test their MCXNx4x MCU-based

designs.

NXP Semiconductors UG10092

MCXNx4x Hardware Design Guide

1 Introduction

This document aims to help hardware engineers design and test their MCXNx4x MCU-based designs. It

provides information about board layout recommendations and design checklists to ensure first-pass success

and avoid board bring-up problems. For the relevant device-specific hardware documentation, see MCX N

Series Microcontrollers.

2 Architecture overview

Before designing your system, it is essential to understand the architecture so that the schematic process is

performed correctly, see Figure 1.

Analog domain

VDD_ANA

VDD_BAT

VDD

_CO

VDD

aaa-053995

LDO_CORE

VDD

_US

USB FS PHY

Core domain System domain

VOUT_SYS

1.8/2.5 V

VDD_LDO_SYS

USB HS PHY

LDO_SYS

VDD_DCDC

DCDC_LX

DCDC_CORE

Retention

RAM

VBAT domain

VBAT

switch

Dig.

Anal.

RAM

LDO Switch

VDD

GPIO

Port 0/1

GPIO

VDD_P2

GPIO

Port 2

GPIO

VDD_P3

GPIO

Port 3

GPIO

VDD_P4

GPIO

Port 4

GPIO

Port 5

GPIO

Figure 1. MCXNx4x hardware architecture block diagram

The design process typically begins with power for the device, as it is one of the most critical aspects of the

design. MCXNx4x was designed to allow for flexibility in the power schema for the device. There are eight

independent power domains to consider. Each power domain has its own operating ranges and restrictions, see

Table 1.

Power domain Voltage range Package pin Remarks

Core 1.71 V – 3.60 V VDD_DCDC or VDD_

LDO_CORE

This value applies to both DCDC and core LDO.

System 1.71 V – 1.98 V

2.25 V – 2.75 V

VDD_LDO_SYS

(VDD_DCDC in HLQFP)

Onboard regulators do accept 1.71 V – 3.6 V.

The extended voltage range of 2.25 V - 2.75 V is for fuse

programming only.

VDD 1.71 V – 3.60 V VDD It also powers VDD_P2 in the HLQFP package.

Table 1. Power domain operating requirements

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NXP Semiconductors UG10092

MCXNx4x Hardware Design Guide

Power domain Voltage range Package pin Remarks

VDD_P2 1.71 V – 3.60 V

1.14 V – 1.32 V

VDD_P2

(VDD in HLQFP)

The extended voltage range of 1.14 V – 1.32 V is

allowed, provided this rail ramps after the system

domain.

The extended voltage range of 1.14 V – 1.32 V is not

allowed in the HLQFP package because it is powered by

the VDD pin.

VDD_P3 1.71 V – 3.60 V

1.14 V – 1.32 V

VDD_P3 The extended voltage range allowed, provided this rail

ramps after the system domain.

VDD_P4/VDD_

ANA

1.71 V – 3.60 V VDD_P4 and VDD_ANA VDD_P4 and VDD_ANA must be tied together.

VDD_BAT 1.71 V – 3.60 V VDD_BAT This rail is required and must ramp before or with the

system domain.

USB 3.00 V – 3.60 V VDD_USB This rail is optional if USB is not used in the application.

If USB is not used, this rail must be grounded.

Table 1. Power domain operating requirements...continued

3 Power configurations

Two basic power configurations are allowed for the MCXNx4x:

•Single supply configuration

•Mixed supply configuration

3.1 Single supply configuration

In this configuration, a single power source between 1.71 V - 3.6 V supplies power to the entire system, see

Figure 2.

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NXP Semiconductors UG10092

MCXNx4x Hardware Design Guide

Analog domain

VDD_ANA

VDD_BAT

VDD_

aaa-054003

LDO_CORE

DD_

USB FS PHY

Core domain System domain

VOUT_SYS

1.8/2.5 V

VDD_LDO_SYS

USB HS PHY

LDO_SYS

VDD_DCDC

1.71 - 3.6 V

DCDC_LX

DCDC_CORE

Retention

RAM

VBAT domain

VBAT

switch

Dig.

Anal.

RAM

LDO Switch

Port 0/1

Port 2

Port 3

Port 4

Port 5

Figure 2. Single supply power configuration

The connections highlighted in the red box in Figure 2, shown as dashed lines in this configuration, have

options available:

•Either the VDD_DCDC or the VDD_LDO_CORE can be powered, but it is optional to power both simultaneously.

–If using the DCDC, VDD_DCDC must be powered, and VDD_LDO_CORE is connected directly to VDD_CORE.

Also, the DCDC_LX pin must be connected to the VDD_CORE pin through the DCDC inductor. The inductor

and specifics are explained later in this document.

Note: NXP recommends using the DCDC as the core regulator. it is more efficient than the LDO regulator.

–If using the core LDO, VDD_LDO_CORE must be powered, and both VDD_DCDC and DCDC_LX must be

grounded through a 10 k ohm resistor, the same resistor must be used for both pins.

Note: Designs that reduce BoM costs or save physical space must use the core LDO.

•The main source powers VDD_BAT, or an always-on source, such as a backup battery, may power it.

•VDD_USB may be omitted if it is not being used in the application. If not used, it must be connected to the

ground.

In the single supply configuration, sources less than 2.75 V cannot blow fuses. It must be considered in

the design phase of your project. Supplies of 1.95 V or less must power the VOUT_SYS pin directly and tie

VDD_LDO_SYS to VOUT_SYS.

3.2 Mixed supply configuration

In this configuration, at least two different voltage supplies power the system. Both must still be between 1.71 V

– 3.6 V, see Figure 3.

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NXP Semiconductors UG10092

MCXNx4x Hardware Design Guide

Analog domain

VDD_ANA

VDD_BAT

DD_

_CO

aaa-054007

LDO_CORE

DD_

USB

USB FS PHY

Core domain System domain

VOUT_SYS

1.8/2.5 V

VDD_LDO_SYS

USB HS PHY

LDO_SYS

VDD_DCDC

DCDC_LX

DCDC_CORE

Retention

RAM

VBAT domain

VBAT

switch

Dig.

Anal.

RAM

LDO Switch

Port 0/1

Port 2

Port 3

Port 4

Port 5

Supply A

Supply B

Figure 3. Mixed supply power configuration

The connections highlighted in the red box in Figure 3, shown as dashed lines in this configuration, have

options available. It is assumed that Supply A is a ~3.3 V supply highlighted in green, while Supply B is

approximately ~1.8 V highlighted in blue, as shown in Figure 3. These supplies could be different, as in the

case of a 1.8 V system that needs to interface to legacy 3.3 V devices or a 1.8 V system that requires a higher

analog voltage for performance reasons, but these are common supply voltages. Some notes concerning this

configuration:

•If using the DCDC, the lower voltage should be selected. The DCDC is more efficient at lower voltages. The

same thumb rule applies to the core LDO. The VDD_CORE must ramp after VDD. Designers must ensure that

these conditions are met.

•Either source can supply VDD_BAT but should power up before or with VDD_SYS. Designers must ensure that

these conditions are met.

•Secondary IOs VDD_P2, VDD_P3, and VDD_P4 must ramp after VDD_SYS unless they are shorted with the

VDD.

4 Bulk and decoupling capacitance

Bulk and decoupling capacitors must be used for proper chip operation. Bulk capacitors are used for local

power supply to the pin, and decoupling capacitors are used to prevent noise from entering the MCU by

shortening it to the ground. Selecting decoupling capacitors that exhibit low reactance in the frequency ranges

of interest is essential.

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NXP Semiconductors UG10092

MCXNx4x Hardware Design Guide

In general, NXP recommends that each power pin have one decoupling capacitor of 0.1 µF and each power

domain have one bulk capacitor of 1 µF. The decoupling and bulk capacitors must be placed as close to their

respective MCU pins as possible. The minimum recommended bulk and decoupling capacitors are listed

in Table 2 and are based on the assumption that no devices operate in the system with a higher operating

frequency than the MCX device.

Power domain Recommendation Remarks

VDD_LDO_CORE 1x 0.1 µF If the core LDO is not being used, this capacitor can be omitted.

It is also not applicable for the HLQFP package.

VDD_CORE 1x 3.7 µF - 10 µF (4.7 µF is

recommended)

2x 0.1 µF

If the DCDC is used to power the core, the bulk capacitor (1x

3.7-10 µF) must be excluded.

VDD_LDO_SYS 1x 1.0 µF If the LDO system is not being used, this capacitor can be

omitted.

It is also not applicable for the HLQFP package.

VDD_SYS 1x 1.0 µF - 4.0 µF -

VDD 1x 1 µF

3x 0.1 µF

VDD_P2 1x 1 µF

2x 0.1 µF

This row is not applicable to the HLQFP package.

VDD_P3 1x 1 µF

3x 0.1 µF

VDD_P4 1x 1 µF

2x 0.1 µF

VDD_ANA - It must be tied to VDD_P4 through a filtering inductor. As such,

this net uses VDD_P4 bulk and decoupling capacitance.

VDD_BAT 1x 0.1 µF -

VDD_USB 1x 0.1 µF If USB is not being used, it can be omitted.

VREFH 1x 1 µF -

VDD_DCDC 1x 10 µF

1x 6 – 30 µF

If the DCDC is not used, both of these capacitors can be omitted.

Otherwise, the 10 µF capacitor must be placed on the input to the

DCDC, while the 6 µF - 30 µF capacitor must be placed on the

output close to the VDD_CORE pin.

Table 2. Minimum recommended bulk and decoupling capacitors for VFBGA package

5 Package details, route-out, and special considerations

The MCXNx4x device is available in two packages:

•184-pin VFBGA

•100-pin HLQFP

This section discusses the package dimensions, specifications, recommended general layout, recommended

route-out, and PCB stack-up.

5.1 184-pin VFBGA package

This section provides details about the 184-pin VFBGA package outline, placement, routing, and PCB stack-up.

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NXP Semiconductors UG10092

MCXNx4x Hardware Design Guide

5.1.1 Package outline

This section provides the details about the outline of the 84-pin VFBGA package, see Figure 4.

aaa-054008

Package drawing:

SOT2172-1

184VFBGA

9 x 9 x 0.86 mm

0.5 mm

Figure 4. 184-pin VFBGA package drawing

5.1.2 VFBGA placement

The key peripheral placement of the VFBGA package is shown Figure 5.

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NXP Semiconductors UG10092

MCXNx4x Hardware Design Guide

P1_8A

aaa-054009

P1_7 P1_4 P0_25

ENET

XTAL48M

FlexSPI_A

DCDC

USB

XTAL32K

FlexSPI_B

uSDHC

Analog

functions

P0_21 P0_17 P0_9 P0_5 P0_1 P0_0

P1_9 P1_6 P1_5 P1_3 P0_24 P0_23 P0_22 P0_16 P0_11 P0_10 P0_4 P0_3 P0_2 P3_0

1 2 3 4 6 8 10 12 14 16 17

P1_10 P1_2 P1_1 P1_0 P0_ 20 P0_19 P0_18 P0_8 P0_7 P0_6 P3_1

P1_13 P1_12 P1_11 P1_14 VSS P0_31 P0_12 VSSVSS P3_7 P3_2 P3_3 P3_6

P1_15 VSS

P1_19

P0_30 P0_28 P0_27 P0_14 VSS P3_8

P1_30 P1_31 RESE

T_B P1_17 P1_16 P0_ 29 P0_26 P0_13 P3_4 P3_9 P3_11 P3_10

VSS P1_18 VDD VDD_

P3 P3_5P0_15 P3_12

P2_1 P2_0 P2_2 VSS VDD VDD VSS VDD_

VDD_

P3 VSS P3_15 P3_13 P3_14

P2_3 VSS VSS VSS VSS P3_16

P2_5 P2_6 P2_4 P1_20

VDO_

LDO_

CORE

VDD_

P2 VSS VDO_

CORE P5_5 P5_6 P3_17 P3_18 P3_19

P2_7 P1_22 P1_21 VDO_

VDO_

CORE P5_8P5_7 P3_21

P2_9 P2_8 P2_10 P1_23 P4_4 P4_5 P5_2 P5_4 P5_9 P3_23 P3_ 22 P3_20

P2_11 VDO_

P4 P4_14P4_6 P4_18 P5_3 VSS VDD_

SYS

P4_0 P4_1 ANA_0 VDO_

VSS_

USB1_

MVSS VSS

VDD_

LDO_

SYS

VSS_

DCDC

DCDC_

ANA_1 VDO_

ANA

VREF

LP4_16 P4_17 P4_19 VDD_

USB

USB1_

VDD_

DCDC

P4_ 2 ANA_4 ANA_5 P4_7 P4_12 P4_13 P4_15 P4_ 20 P4_ 21 P4_22 USB0

USB0

DP VSS VDD_

BAT

P4_3 ANA_6 ANA_7 ANA_1

ANA_1

ANA_

22 P4_ 23 USB1_

VBUS P5_0 P5_1

5 7 9 11 13 15

P4_0

P4_1

ANA_0

VDO_

VSS_

USB

ANA_1

VDO_

ANA

VREF

P4_16

P4_17

P4_19

P4_ 2

ANA_4

ANA_5

P4_7

P4_12

P4_13

P4_15

P4_ 20

P4_

P4_3

ANA_6

ANA_7

ANA_1

ANA_

P2_1

P2_0

P2_2

P2_3

P2_5

P2_6

P2_4

P2_7

P2_9

P2_8

P2_10

P1_30

P1_31

P1_8

P1_7

P1_4

P1_9

P1_6

P1_5

P1_3

P1_10

P1_2

P1_1

P1_13

P1_12

P1_11

P1_14

P3_7

P3_2

P3_3

P3_6

P3_8

P3_4

P3_9

P3_11

P3_10

P3_5

P3_12

P3_15

P3_13

P3_14

VSS

P3_16

VDD_

USB

USB1_

VDD_

DCDC

P4_22

USB0

VSS

P5_0

P5_1

VSS_

DCDC

DCDC_

Figure 5. Key peripheral placement for VFBGA package

5.1.2.1 Bulk and decoupling capacitor placement

Like other high-speed BGA devices, decoupling and bulk capacitors must be placed on the bottom side of the

PCB, directly underneath the device. It is recommended to use the smallest package type allowed by budget

and manufacturing constraints for both capacitor types. These capacitors must be mounted as close to the

power vias as possible. It minimizes the inductance and ensures high-speed transient current demand by the

processor.

An example layout is shown in Figure 6.

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NXP Semiconductors UG10092

MCXNx4x Hardware Design Guide

Figure 6. Example decoupling and bulk capacitor layout for VFBGA package

5.1.3 VFBGA routing

The MCXNx4x VFBGA is designed to allow for routing all 184-pins externally in a four-layer design using 4 mil

trace widths and Via-In-Pad (VIP) technology. The recommended route-out is shown in Figure 7.

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NXP Semiconductors UG10092

MCXNx4x Hardware Design Guide

L3 L4

Figure 7. Recommended VFBGA escape routing

5.1.4 PCB stack-up for VFBGA

As per NXP recommendations, MCXNx4x VFBGA is designed to be routed on a minimum of four layers. Less

may be possible, but it may require special toolings and/or a nonoptimal design. It may also not be possible to

route out all of the connections. Two examples of a four-layer stack-up are shown in Figure 8 and Figure 9.

Signal

aaa-054010

GND

PWR

Signal

>> 2x

Figure 8. Example four-layer stack-up #1

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