Freescale Semiconductor MC9S12DJ128E Manual de usuario

HCS12

Microcontrollers

freescale.com

MC9S12DT128

Device User Guide

Covers MC9S12DT128E, MC9S12DG128E,

MC9S12DJ128E, MC9S12DG128, MC9S12DJ128,

MC9S12DB128,MC9S12A128,SC515846,SC515847,

SC515848, SC515849, SC101161DT, SC101161DG,

SC101161DJ, SC102202, SC102203, SC102204,

SC102205

9S12DT128DGV2/D

V02.16

12 APR 2008

Device User Guide — 9S12DT128DGV2/D V02.16

2Freescale Semiconductor

Revision History

Version

Number Revision

Date Effective

Date Author Description of Changes

V01.00 18 Jun

2001 18 June

2001 Initial version (parent doc v2.03 dug for dp256).

V01.01 23 July

2001 23 July

2001 Updated version after review

V01.02 23 Sep

2001 23 Sep

2001

Changed Partname, added pierce mode, updated electrical

characteristics

some minor corrections

V01.03 12 Oct

2001 12 Oct

2001 Replaced Star12 by HCS12

V01.04 27 Feb

2002 27 Feb

2002

Updated electrical spec after MC-Qualiﬁcation (IOL/IOH), Data for

Pierce, NVM reliability

New document numbering. Corrected Typos

V01.05 4 Mar

2002 4 Mar

2002 Increased VDD to 2.35V, removed min. oscillator startup

Removed Document order number except from Cover Sheet

V01.06 8 July

2002 22 July

2002

Added:

Pull-up columns to signal table,

example for PLL Filter calculation,

Thermal values for junction to board and package,

BGND pin pull-up

Part Order Information

Global Register Table

Chip Conﬁguration Summary

Modiﬁed:

Reduced Wait and Run IDD values

Mode of Operation chapter

changed leakage current for ADC inputs down to +-1uA

Corrected:

Interrupt vector table enable register inconsistencies

PCB layout for 80QFP VREGEN position

V02.00 11 Jan

2002 11 Jan

2002

NEW MASKSET

Changed part number from DTB128 to DT128

Functional Changes:

ROMCTL changes in Emulation Mode

80 Pin Byteﬂight package Option available

Flash with 2 Bit Backdoor Key Enable

Additional CAN0 routing to PJ7,6

Improved BDM with sync and acknowledge capabilities

New Part ID number

Improvements:

Signiﬁcantly improved NVM reliability data

Corrections:

Interrupt vector Table

V02.01 01 Feb

2002 01 Feb

2002 Updated Block User Guide versions in preface

Updated Appendix A Electrical Characteristics

Device User Guide — 9S12DT128DGV2/D V02.16

Freescale Semiconductor 3

V02.02 08 Mar

2002 08 Mar

2002

Changed XCLKS to PE7 in Table 2-2

Updated device part numbers in Figure 2-1

Updated BDM clock in Figure 3-1

Removed SIM description in overview & nUPOSC spec in Table A-15

Updated electrical spec of VDD & VDDPLL (Table A-4), IOL/IOH

(Table A-6), CINS (Table A-9), CIN (Table A-6 & A-15),

Updated interrupt pulse timing variables in Table A-6

Updated device part numbers in Figure 2-1

Added document numbers on cover page and Table 0-2

V02.03 14 Mar

2002 14 Mar

2002

Cleaned up Fig. 1-1, 2-1

Updated Section 1.5 descriptions

Corrected PE assignment in Table 2-2, Fig. 2-5,6,7.

Corrected NVM sizes in Sections 16, 17

Added IREF spec for 1ATD in Table A-8

Added Blank Check in A.3.1.5 and Table A-11

Updated CRG spec in Table A-15

V02.04 16 Aug

2002 16 Aug

2002

Added:

Pull-up columns to signal table,

Example for PLL Filter calculation,

Thermal values for junction to board and package,

BGND pin pull-up

Part Order Information

Global Register Table

Chip Conﬁguration Summary

Device speciﬁc info on CRG

Modiﬁed:

Reduced Wait and Run IDD values

Mode of Operation chapter

Changed leakage current for ADC inputs down to +-1uA

Minor modiﬁcation of PLL frequency/ voltage gain values

Corrected:

Pin names/functions on 80 pin packages

Interrupt vector table enable register inconsistencies

PCB layout for 80QFP VREGEN position

V02.05 12 Sep

2002 12 Sep

2002 Corrected:

V02.06 06 Nov

2002 06 Nov

2002

Removed document order no. from Revision History pages

Renamed "Preface" section to "Derivative Differences and

Document references". Added details for derivatives missing

CAN0/1/4, BDLC, IIC and/or Byteﬂight

Added 2L40K mask set in section 1.6

Added OSC User Guide in Preface, “Document References”

Added oscillator clock connection to BDM in S12_CORE in ﬁg 3-1

Corrected several register and bit names in “Local Enable” column

of Table 5.1 Interrupt Vector Locations

Section HCS12 Core Block Description: mentioned alternate clock

of BDM to be equivalent to oscillator clock

Added new section: “Oscillator (OSC) Block Description”

Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz

Version

Number Revision

Date Effective

Date Author Description of Changes

Device User Guide — 9S12DT128DGV2/D V02.16

4Freescale Semiconductor

V02.07 29 Jan

2003 29 Jan

2003

Added 3L40K mask set in section 1.6

Corrected register entries in section 1.5.1 “Detailed Memory Map”

Updated description for ROMCTL in section 2.3.31

Updated section 4.3.3 “Unsecuring the Microcontroller”

Corrected and updated device-speciﬁc information for OSC

(section 8.1) & Byteﬂight (section 15.1)

Updated footnote in Table A-4 “Operating Conditions”

Changed reference of VDDM to VDDR in section A.1.8

Removed footnote on input leakage current in Table A-6 “5V I/O

Characteristics”

V02.08 26 Feb

2003 26 Feb

2003

Added part numbers MC9S12DT128E, MC9S12DG128E, and

MC9S12DJ128E in “Preface” and related part number references

Removed mask sets 0L40K and 2L40K from Table 1-3

V02.09 15 Oct

2003 15 Oct

2003

Replaced references to HCS12 Core Guide by the individual

HCS12 Block guides in Table 0-2, section 1.5.1, and section 6;

updated Fig.3-1 “Clock Connections” to show the individual HCS12

blocks

Corrected PIM module name and document order number in Table

0-2 “Document References”

Corrected ECT pulse accumulators description in section 1.2

“Features”

Corrected KWP5 pin name in Fig 2-1 112LQFP pin assignments

Corrected pull resistor CTRL/reset states for PE7 and PE4-PE0 in

Table 2.1 “Signal Properties”

Mentioned “S12LRAE” bootloader in Flash section 17

Corrected footnote on clamp of TEST pin under Table A-1

“Absolute Maximum Ratings”

Corrected minimum bus frequency to 0.25MHz in Table A-4

“Operating Conditions”

Replaced “burst programming” by “row programming” in A.3 “NVM,

Flash and EEPROM”

Corrected blank check time for EEPROM in Table A-11 “NVM

Timing Characteristics”

Corrected operating frequency in Table A-18 “SPI Master/Slave

Mode Timing Characteristics

V02.10 6 Feb

2004 6 Feb

2004

Added A128 information in “Derivative Differences”, 2.1 “Device

Pinout”, 2.2 “Signal Properties Summary”, Fig 23-2 & Fig 23-4

Added lead-free package option (PVE) in Table 0-2 “Derivative

Differences for MC9S12DB128” and Fig 0-1 “Order Partnumber

Example”

Added an “AEC qualiﬁed” row in the “Derivative Differences” tables

0-1 & 0-2.

V02.11 3 May

2004 3 May

2004

Added part numbers SC515846, SC515847, SC515848, and

SC515849 in “Derivative Differences” tables 0-1 & 0-2, section 2,

and section 23.

Corrected and added maskset 4L40K in tables 0-1 & 0-2 and

section 1.6.

Corrected BDLC module availability in DB128 80QFP part in

“Derivative Differences” table 0-2.

Version

Number Revision

Date Effective

Date Author Description of Changes

Device User Guide — 9S12DT128DGV2/D V02.16

Freescale Semiconductor 5

V02.12 06 Dec

2004 06 Dec

2004

Added maskset 0L94R

Added items VIH,EXTAL, VIL,EXTAL, & VHYS,EXTAL in table A-15

“Oscillator characteristics”

Removed item “Oscillator” from table A-4 “Operating Conditions” as

it is already covered in table “Oscillator Characteristics”

V02.13 04 Mar

2005 04 Mar

2005 Amended feature list of A128 in Table 0-1 “Derivative Differences”

V02.14 28 Apr

2005 28 Apr

2005

Updated cover page

Added part numbers SC101161DT, SC101161DG, SC101161DJ,

SC102202, SC102203, SC102204, & SC102205

Added masksets 5L40K &1L59W

Changed TJavg to 85°C in table A-12 “NVM Reliability” & added

footnote concerning data retention

V02.15 05 Oct

2005 05 Oct

2005 Updated “NVM Reliability” table A-12 format with added data.

Added ﬁgure A-2 “Typical Endurance vs Temperature”

V02.16 12 Apr

2008 12 Apr

2008 Added maskset 2L94R

Version

Number Revision

Date Effective

Date Author Description of Changes

Device User Guide — 9S12DT128DGV2/D V02.16

6Freescale Semiconductor

Device User Guide — 9S12DT128DGV2/D V02.16

Freescale Semiconductor

Table of Contents

Section 1 Introduction

1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.5 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.5.1 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.6 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Section 2 Signal Description

2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.3.3 TEST — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.3.4 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . 64

2.3.6 PAD[15] / AN1[7] / ETRIG1 — Port AD Input Pin [15] . . . . . . . . . . . . . . . . . . . . . 65

2.3.7 PAD[14:8] / AN1[6:0] — Port AD Input Pins [14:8]. . . . . . . . . . . . . . . . . . . . . . . . 65

2.3.8 PAD[7] / AN0[7] / ETRIG0 — Port AD Input Pin [7] . . . . . . . . . . . . . . . . . . . . . . . 65

2.3.9 PAD[6:0] / AN0[6:0] — Port AD Input Pins [6:0]. . . . . . . . . . . . . . . . . . . . . . . . . . 65

2.3.10 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 65

2.3.11 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 65

2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

2.3.13 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.3.14 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.3.15 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.3.16 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.3.17 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.3.18 PE1 / IRQ — Port E Input Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.3.19 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.3.20 PH7 / KWH7 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Device User Guide — 9S12DT128DGV2/D V02.16

8Freescale Semiconductor

2.3.21 PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

2.3.22 PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

2.3.23 PH4 / KWH4 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

2.3.24 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

2.3.25 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

2.3.26 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

2.3.27 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

2.3.28 PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 — PORT J I/O Pin 7. . . . . . . . . . . . . . . 68

2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 — PORT J I/O Pin 6 . . . . . . . . . . . . . . 69

2.3.30 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

2.3.31 PK7 / ECS / ROMCTL — Port K I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

2.3.32 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 69

2.3.33 PM7 / BF_PSLM / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . 69

2.3.34 PM6 / BF_PERR / RXCAN4 — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . 69

2.3.35 PM5 / BF_PROK / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . 69

2.3.36 PM4 / BF_PSYN / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4. . . . . . . . . . 70

2.3.37 PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . 70

2.3.38 PM2 / RX_BF / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2. . . . . . . . . . . . 70

2.3.39 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

2.3.40 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

2.3.41 PP7 / KWP7 / PWM7 — Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

2.3.42 PP6 / KWP6 / PWM6 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

2.3.43 PP5 / KWP5 / PWM5 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

2.3.44 PP4 / KWP4 / PWM4 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

2.3.45 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . 71

2.3.46 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . 71

2.3.47 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . 71

2.3.48 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . 71

2.3.49 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

2.3.50 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

2.3.51 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

2.3.52 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

2.3.53 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

2.3.54 PS2 / RXD1 — Port S I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

2.3.55 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

2.3.56 PS0 / RXD0 — Port S I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Device User Guide — 9S12DT128DGV2/D V02.16

Freescale Semiconductor

2.3.57 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . 73

2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins. . . . . . . . . . . . 73

2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 74

2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 74

2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL. . . . . . . . . . . . . . . . . . . . . . . . 74

2.4.7 VREGEN — On Chip Voltage Regulator Enable. . . . . . . . . . . . . . . . . . . . . . . . . 74

Section 3 System Clock Description

3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Section 4 Modes of Operation

4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.2 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Section 5 Resets and Interrupts

5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Section 6 HCS12 Core Block Description

6.1 CPU Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Device User Guide — 9S12DT128DGV2/D V02.16

10 Freescale Semiconductor

6.1.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.2 HCS12 Module Mapping Control (MMC) Block Description. . . . . . . . . . . . . . . . . . . 85

6.2.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . 85

6.3.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.4 HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.5 HCS12 Background Debug Module (BDM) Block Description. . . . . . . . . . . . . . . . . 86

6.5.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.6 HCS12 Breakpoint (BKP) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Section 7 Clock and Reset Generator (CRG) Block Description

7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Section 8 Oscillator (OSC) Block Description

8.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Section 9 Enhanced Capture Timer (ECT) Block Description

Section 10 Analog to Digital Converter (ATD) Block Description

Section 11 Inter-IC Bus (IIC) Block Description

Section 12 Serial Communications Interface (SCI) Block Description

Section 13 Serial Peripheral Interface (SPI) Block Description

Section 14 J1850 (BDLC) Block Description

Section 15 Byteflight (BF) Block Description

15.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Section 16 Pulse Width Modulator (PWM) Block Description

Section 17 Flash EEPROM 128K Block Description

Section 18 EEPROM 2K Block Description

Section 19 RAM Block Description

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