Cypress Semiconductor CY7C1380C Manual de usuario

18-Mb (512K x 36/1M x 18) Pipelined SRAM

CY7C1380C

CY7C1382C

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-05237 Rev. *D Revised February 26, 2004

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 225, 200,166 and

133MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V / 3.3V I/O operation

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 166-MHz device)

— 4.2 ns (for 133-MHz device)

• Provide high-performance 3-1-1-1 access rate

•User-selectable burst counter supporting Intel®

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• OfferedinJEDEC-standard100-pinTQFP,119-ballBGA

and 165-Ball fBGA packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Functional Description[1]

The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36

and 1,048,576 x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE1), depth-expansion Chip

Enables(CE2andCE3[2]),BurstControlinputs (ADSC, ADSP,

and ADV), Write Enables (BWX, and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

toinitiate a self-timed Writecycle.This partsupportsByteWrite

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1380C/CY7C1382C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit

Maximum Access Time 2.6 2.8 3.0 3.4 4.2 ns

Maximum Operating Current 350 325 300 275 245 mA

Maximum CMOS Standby Current 70 70 70 70 70 mA

Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE3, CE2are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

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CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *D Page 2 of 36

LogicBlock Diagram– CY7C1380C(512Kx 36)

ADDRESS

ADV

CLK BURST

COUNTER

AND

LOGIC

CLR

ADSP

ADSC

MODE

BWE

ENABLE

OUTPUT

REGISTERS

SENSE

AMPS

OUTPUT

BUFFERS

PIPELINED

ENABLE

INPUT

REGISTERS

0, A1, A

MEMORY

ARRAY

DQs

DQPA

DQPB

DQPC

DQPD

SLEEP

CONTROL

[1:0]

A ,

DQP

BYTE

WRITE REGISTER

B ,

DQP

BYTE

WRITE REGISTER

C ,

DQP

BYTE

WRITE REGISTER

D ,

DQP

BYTE

WRITE REGISTER

A ,

DQP

BYTE

WRITE DRIVER

B ,

DQP

BYTE

WRITE DRIVER

C ,

DQP

BYTE

WRITE DRIVER

,DQP

BYTE

WRITE DRIVER

0, A1, A ADDRESS

ADV

CLK BURST

COUNTER AND

LOGIC

CLR

ADSC

BWB

BWA

CE1

DQB,DQPB

WRITE REGISTER

DQA,DQPA

WRITE REGISTER

ENABLE

SENSE

AMPS

MEMORY

ARRAY

ADSP

MODE

CE2

CE3

BWE

PIPELINED

ENABLE

DQs

DQP

OUTPUT

REGISTERS

INPUT

REGISTERS

DQA,DQPA

WRITE DRIVER

OUTPUT

BUFFERS

DQB,DQPB

WRITE DRIVER

A[1:0]

ZZ SLEEP

CONTROL

Logic Block Diagram – CY7C1382C (1M x 18)

[+] Feedback

CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *D Page 3 of 36

Pin Configurations

NC / 72M

NC / 36M

DQP

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

DQc

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1380C

(512K X 36)

NC / 72M

NC / 36M

DDQ

SSQ

DQP

SSQ

DDQ

SSQ

DDQ

SSQ

DDQ

SSQ

DQP

SSQ

DDQ

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1382C

(1M x 18)

100-pin TQFP Pinout

[+] Feedback

CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *D Page 4 of 36

Pin Configurations (continued)

2345671

VDDQ

NC DQPC

DQC

DQD

DQC

DQD

AA AA

ADSP VDDQ

DQC

VDDQ

DQC

VDDQ

DQD

NC VDDQ

VDD

CLK

VDD

VSS

TDOTCKTDITMS NC / 36MNC / 72M

VDDQ

AAA

AA0

DQA

DQC

DQA

DQB

DQA

DQB

VDD

DQC

VDD

DQD

ADSC

CE1

ADV

VSS

VSS DQPA

MODE

DQPD

DQPB

BWB

BWC

NC VDD NC

BWA

BWE

BWD

2345671

VDDQ

NC NCDQB

DQB

AA AA

ADSP VDDQ

VDDQ

NC / 72M VDDQ

VDD

CLK

VDD

VSS

TDOTCKTDITMS AA NC

VDDQ

A NC / 36M A A

DQA

DQB

DQA

VDD

DQB

VDD

DQB

ADSC

CE1

ADV

VSS

VSS NC

MODE

DQPB

DQPA

VSS

BWB

NC VDD NC

BWA

BWE

VSS

CY7C1382C (512K x 18)

CY7C1380C (512K x 36)

119-ball BGA (1 Chip Enable with JTAG)

[+] Feedback

CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *D Page 5 of 36

Pin Configurations (continued)

165-ball fBGA

CY7C1380C (512K x 36)

234 5671

TDO

NC / 288M

DQP

CE3

BWE

ACE2

MODE

NC / 36M

NC / 72M

DDQ

CLK GW

DDQ

TCK

TDI

NC NC

DDQ

TMS

891011

ADV

ADSC

OE ADSP

ANC / 144M

DDQ

NC DQP

DDQ

DQP

DDQ

CY7C1382C (1M x 18)

2345671

TDO

NC / 288M

DQP

ACE

BWE

ACE2

MODE

NC / 36M

NC / 72M

DDQ

NC BW

CLK GW

DDQ

TCKA0

TDI

NC V

NC NC

DDQ

TMS

891011

ADV

ADSC

OE ADSP

ANC / 144M

DDQ

NC DQP

DDQ

NC DQ

DDQ

NCV

DDQ

NC ZZ

DDQ

[+] Feedback

CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *D Page 6 of 36

CY7C1380C–Pin Definitions

Name TQFP BGA fBGA I/O Description

A0, A1, A 37,36,32,

33,34,35,

42,43,44,45,

46,47,48,

49,50,81,

82,99,100

P4,N4,

A2,B2,

C2,R2,

A3,B3,C3,

T3,T4,A5,B5,

C5,

T5,A6,B6,C6,

R6,P6,A2,

A10,B2,

B10,N6,P3,P4,

P8,P9,P10,

P11,R3,R4,R8,

R9,R10,R11

Input-

Synchronous Address Inputs used to select one of the

256Kaddresslocations.Sampledattherising

edge of the CLK if ADSP or ADSC is active

LOW, and CE1,CE2, and CE3 [2]are sampled

active. A1: A0 are fed to the two-bit counter..

BWA,BWB

BWC,BWD

93,94,95,

96 L5,G5,

G3,L3 B5,A5,A4,

B4 Input-

Synchronous Byte Write Select Inputs, active LOW.

QualifiedwithBWEtoconductbytewritestothe

SRAM. Sampled on the rising edge of CLK.

GW 88 H4 B7 Input-

Synchronous Global Write Enable Input, active LOW.

WhenassertedLOW onthe risingedge ofCLK,

a global write is conducted (ALL bytes are

written, regardless of the values on BWXand

BWE).

BWE 87 M4 A7 Input-

Synchronous Byte Write Enable Input, active LOW. Sam-

pledontherising edgeofCLK.Thissignalmust

be asserted LOW to conduct a byte write.

CLK 89 K4 B6 Input-

Clock Clock Input. Used to capture all synchronous

inputsto thedevice. Also used toincrementthe

burst counter when ADV is asserted LOW,

during a burst operation.

CE198 E4 A3 Input-

Synchronous ChipEnable1Input,activeLOW.Sampledon

therisingedgeofCLK.Usedinconjunctionwith

CE2and CE3to select/deselect the device.

ADSP is ignored if CE1is HIGH.

CE2[2] 97 - B3 Input-

Synchronous Chip Enable 2 Input, active HIGH. Sampled

on the rising edge of CLK. Used in conjunction

withCE1and CE3to select/deselect the device.

CE3[2] 92 - A6 Input-

Synchronous ChipEnable3Input,activeLOW.Sampledon

therisingedgeofCLK.Usedinconjunctionwith

CE1 andCE2to select/deselect the device.Not

available for AJ package version.Not

connected for BGA. Where referenced, CE3is

assumed active throughout this document for

BGA.

OE 86 F4 B8 Input-

Asynchronous Output Enable, asynchronous input, active

LOW. Controls the direction of the I/O pins.

When LOW, the I/O pins behave as outputs.

When deasserted HIGH, I/O pins are tri-stated,

andactasinputdatapins. OEismaskedduring

the first clock of a read cycle when emerging

from a deselected state.

ADV 83 G4 A9 Input-

Synchronous Advance Inputsignal, sampledon the rising

edge of CLK, active LOW. When asserted, it

automaticallyincrementstheaddressina burst

cycle.

[+] Feedback

CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *D Page 7 of 36

ADSP 84 A4 B9 Input-

Synchronous Address Strobe from Processor, sampled

ontherisingedgeofCLK,activeLOW.When

asserted LOW, addresses presented to the

device are captured in the address registers.

A1: A0 are also loaded into the burst counter.

WhenADSPandADSCarebothasserted,only

ADSP is recognized. ASDP is ignored when

CE1is deasserted HIGH.

ADSC 85 B4 A8 Input-

Synchronous AddressStrobefromController,sampledon

the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the

device are captured in the address registers.

A1: A0 are also loaded into the burst counter.

WhenADSPandADSCarebothasserted,only

ADSP is recognized.

ZZ 64 T7 H11 Input-

Asynchronous ZZ “sleep” Input, active HIGH. When

asserted HIGH places the device in a

non-time-critical “sleep” condition with data

integrity preserved. For normal operation, this

pinhas to be LOW or leftfloating.ZZ pin has an

internal pull-down.

DQs, DQPs 52,53,56,

57,58,59,

62,63,68,

69,72,73,

74,75,78,

79,2,3,6,7,8,9,

12,13,18,19,22

23,24,25,

28,29,51,

80,1,30

K6,L6,

M6,N6,

K7,L7,

N7,P7,

E6,F6,

G6,H6,

D7,E7,

G7,H7,

D1,E1,

G1,H1,

E2,F2,

G2,H2,

K1,L1,

N1,P1,

K2,L2,

M2,N2,

P6,D6,

D2,P2

M11,L11,

K11,J11,

J10,K10,

L10,M10,

D10,E10,

F10,G10,

D11,E11,

F11,G11,

D1,E1,F1,

G1,D2,E2,F2,

G2,J1,

K1,L1,M1,

J2,K2,L2,

M2,N11,

C11,C1,N1

I/O-

Synchronous Bidirectional Data I/O lines. As inputs, they

feed into an on-chip data register that is

triggered by the rising edge ofCLK.As outputs,

they deliver the data contained in the memory

location specified by the addresses presented

during the previous clock rise of the read cycle.

The direction of the pins is controlled by OE.

When OE is asserted LOW, the pins behave as

outputs. When HIGH, DQs and DQPXare

placed in a tri-state condition.

VDD 15,41,65,

91 J2,C4,J4,R4,

J6 D4,D8,E4,E8,

F4,F8,

G4,G8,H4,H8,

J4,J8,

K4,K8,L4,

L8,M4,M8

Power Supply Power supply inputs to the core of the de-

vice.

VSS 17,40,67,

90 D3,E3,

F3,H3,

K3,M3,

N3,P3,

D5,E5,

F5,H5,

K5,M5,

N5,P5

C4,C5,C6,C7,

C8,D5,D6,D7,

E5,E6,E7,F5,

F6,F7,G5,G6,

G7,H2,H5,H6,

H7,J5,J6,J7,

K5,K6,K7,

L5,L6,L7,

M5,M6,M7,N4,

Ground Ground for the core of the device.

CY7C1380C–Pin Definitions (continued)

Name TQFP BGA fBGA I/O Description

[+] Feedback

CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *D Page 8 of 36

VSSQ 5,10,21,26,55,

60,71,

- - I/O Ground Ground for the I/O circuitry.

VDDQ 4,11,20,27,54,

61,70,

A1,F1,J1,M1,

U1,

A7,F7,J7,M7,

C3,C9,D3,D9,

E3,E9,F3,F9,G

G9,J3,J9,

K3,K9,L3,

L9,M3,M9,N3,

I/O Power

Supply Power supply for the I/O circuitry.

MODE 31 R3 R1 Input-

Static Selects Burst Order. When tied to GND

selectslinearburstsequence.WhentiedtoVDD

or left floating selects interleaved burst

sequence.Thisisastrappinandshouldremain

staticduringdeviceoperation.ModePinhasan

internal pull-up.

TDO - U5 P7 JTAG serial

output

Synchronous

Serial data-out to the JTAG circuit. Delivers

data on the negative edge of TCK. If the JTAG

feature is not being utilized, this pin should be

disconnected.ThispinisnotavailableonTQFP

packages.

TDI - U3 P5 JTAG serial

input

Synchronous

Serial data-In to the JTAG circuit. Sampled

on the rising edge of TCK. If the JTAG feature

is not being utilized, this pin can be discon-

nected or connected to VDD. This pin is not

available on TQFP packages.

TMS - U2 R5 JTAG serial

input

Synchronous

Serial data-In to the JTAG circuit. Sampled

on the rising edge of TCK. If the JTAG feature

is not being utilized, this pin can be discon-

nected or connected to VDD. This pin is not

available on TQFP packages.

TCK - U4 R7 JTAG-Clock Clock input to the JTAG circuitry.If theJTAG

feature is not being utilized, this pin must be

connected to VSS. This pin is not available on

TQFP packages.

NC 14,16,66,

39,38 B1,C1,

R1,T1,T2,J3,

D4,

L4,J5,R5,6T,

6U,

B7,C7,

A11,B1,C2,C1

0,H1,H3,H9,

H10,

N2,N5,N7,N10

,P1,A1,B11,P2

,R2,N6

-No Connects. Not internally connected to the

die

CY7C1380C–Pin Definitions (continued)

Name TQFP BGA fBGA I/O Description

[+] Feedback

CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *D Page 9 of 36

CY7C1382C:Pin Definitions

Name TQFP BGA fBGA I/O Description

A0, A1, A 37,36,32,

33,34,35,

42,43,44,

45,46,47,

48,49,50,

80,81,82,

99,100

P4,N4,

A2,B2,

C2,R2,

T2,A3,

B3,C3,

T3,A5,

B5,C5,

T5,A6,

B6,C6,

R6,T6

R6,P6,A2,

A10,A11,

B2,B10,P3,P4,

N6,P8,P9,

P10,P11,

R3,R4,R8,R9,

R10,

R11

Input-

Synchronous Address Inputs used to select one of the 512K

address locations. Sampled at the rising edge of

the CLK if ADSP or ADSC is active LOW, and CE1,

CE2, and CE3 are sampled active. A1: A0 are fed

to the two-bit counter..

BWA,BWB93,94 G3,L5 B5,A4 Input-

Synchronous Byte Write Select Inputs, active LOW. Qualified

with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

GW 88 H4 B7 Input-

Synchronous Global Write Enable Input, active LOW. When

asserted LOW on the rising edge of CLK, a global

write is conducted (ALL bytes are written,

regardless of the values on BWXand BWE).

BWE 87 M4 A7 Input-

Synchronous Byte Write Enable Input, active LOW. Sampled

on the rising edge of CLK. This signal must be

asserted LOW to conduct a byte write.

CLK 89 K4 B6 Input-

Clock Clock Input. Used to capture all synchronous

inputs to the device. Also used to increment the

burst counter when ADVis asserted LOW,during a

burst operation.

CE198 E4 A3 Input-

Synchronous ChipEnable 1 Input, active LOW.Sampledonthe

rising edge of CLK. Used in conjunction with CE2

and CE3to select/deselect the device. ADSP is

ignored if CE1is HIGH.

CE2[2] 97 - B3 Input-

Synchronous Chip Enable 2 Input, active HIGH. Sampled on

the rising edge of CLK. Used in conjunction with

CE1and CE3to select/deselect the device.

CE3 [2] 92 - A6 Input-

Synchronous ChipEnable 3 Input, active LOW.Sampledonthe

rising edge of CLK. Used in conjunction with CE1

andCE2toselect/deselectthedevice.Notavailable

for AJ package version.Not connected for BGA.

Where referenced, CE3is assumed active

throughout this document for BGA.

OE 86 F4 B8 Input-

Asynchronous Output Enable, asynchronous input, active

LOW. Controls the direction of the I/O pins. When

LOW, the I/O pins behave as outputs. When

deassertedHIGH,I/Opins aretri-stated,andactas

input data pins. OE is masked during the first clock

of a read cycle when emerging from a deselected

state.

ADV 83 G4 A9 Input-

Synchronous Advance Input signal, sampled on the rising

edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst

cycle.

[+] Feedback

CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *D Page 10 of 36

ADSP 84 A4 B9 Input-

Synchronous Address Strobe from Processor, sampled on

the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device

are captured in the address registers. A1: A0 are

alsoloadedintotheburstcounter.WhenADSPand

ADSCareboth asserted,onlyADSPisrecognized.

ASDP is ignored when CE1is deasserted HIGH.

ADSC 85 P4 A8 Input-

Synchronous AddressStrobefromController,sampledonthe

rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are

captured in the address registers. A1: A0 are also

loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized.

ZZ 64 T7 H11 Input-

Asynchronous ZZ “sleep” Input, active HIGH. When asserted

HIGH places the device in a non-time-critical

“sleep” condition with data integrity preserved. For

normal operation, this pin has to be LOW or left

floating. ZZ pin has an internal pull-down.

DQs,

DQPs 58,59,62,

63,68,69,

72,73,8,9,

12,13,18,

19,22,23,

74,24

P7,K7,

G7,E7,

F6,H6,L6,N6,

D1,

H1,L1,

N1,E2,

G2,K2,

M2,D6,

J10,K10,

L10,M10,

D11,E11,

F11,G11,J1,K1

,L1,M1,D2,E2,

F2,

G2,C11,N1

I/O-

Synchronous Bidirectional Data I/O lines. As inputs, they feed

into an on-chip data register that is triggered by the

risingedgeofCLK.Asoutputs,theydeliverthedata

contained in the memory location specified by the

addressespresentedduringthe previous clockrise

of the read cycle. The direction of the pins is

controlled by OE. When OE is asserted LOW, the

pins behave as outputs. When HIGH, DQs and

DQPXare placed in a tri-state condition.

VDD 15,41,65,

91 C4,J2,J4,J6,

R4 D4,D8,E4,E8,

F4,F8,

G4,G8,H4,

H8,J4,J8,

K4,K8,L4,

L8,M4,M8

Power Supply Power supply inputs to the core of the device.

VSS 17,40,67,

90 D3,D5,

E5,E3,F3,F5,

G5,

H3,H5,

K3,K5,L3,M3,

M5,

N3,N5,

P3,P5

H2,C4,C5,C6,

C7,C8,D5,D6,

D7,E5,E6,E7,

F5,F6,F7,

G5,G6,G7,

H5,H6,H7,J5,J

6,J7,

K5,K6,K7,

L5,L6,L7,

M5,M6,M7,N4,

Ground Ground for the core of the device.

VSSQ 5,10,21,26,55,

60,71,

- - I/O Ground Ground for the I/O circuitry.

CY7C1382C:Pin Definitions (continued)

Name TQFP BGA fBGA I/O Description

[+] Feedback

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