Cypress Semiconductor CY7C63413C Manual de usuario

Low-SpeedHighI/O,1.5-MbpsUSBControlle

CY7C63413C

CY7C63513C

CY7C63613C

Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-08027 Rev. *B Revised January 6, 2006

Features

• Low-costsolutionforlow-speedapplicationswithhigh

I/O requirements such as keyboards, keyboards with

integrated pointing device, gamepads, and many

others

• USB Specification Compliance

— Conforms toUSB Specification, Versions 1.1 and2.0

— Conforms to USB HID Specification, Version 1.1

— Supports 1 device address and 3 data endpoints

— Integrated USB transceiver

• 8-bit RISC microcontroller

— Harvard architecture

— 6-MHz external ceramic resonator

— 12-MHz internal CPU clock

• Internal memory

— 256 bytes of RAM

— 8 Kbytes of EPROM

• Interface can auto-configure to operate as PS2 or USB

•I/Oport

— TheCY7C63413C/513Chave24 GeneralPurpose I/O

(GPIO) pins (Port 0 to 2) capable of sinking 7 mA per

pin (typical)

— TheCY7C63613Chas12GeneralPurposeI/O(GPIO)

pins (Port 0 to 2) capable of sinking 7 mA per pin

(typical)

— The CY7C63413C/513C have eight GPIO pins (Port

3) capable of sinking 12 mA per pin (typical) which

can drive LEDs

— TheCY7C63613ChasfourGPIOpins(Port3)capable

of sinking 12 mA per pin (typical) which can drive

LEDs

— Higher current drive is available by connecting

multiple GPIO pins together to drive a common

output

— Each GPIO port can be configured as inputs with

internal pull-ups or open drain outputs or traditional

CMOS outputs

— The CY7C63513C has an additional eight I/O pins on

a DAC port which has programmable current sink

outputs

— Maskable interrupts on all I/O pins

• 12-bit free-running timer with one microsecond clock

ticks

• Watch Dog Timer (WDT)

• Internal Power-On Reset (POR)

• Improved output drivers to reduce EMI

• Operating voltage from 4.0V to 5.5V DC

• Operating temperature from 0 to 70 degrees Celsius

• CY7C63413C available in 40-pin PDIP, 48-pin SSOP, 48-

pin SSOP - Tape reel, all in Lead-Free versions for

production

• CY7C63513C available in 48-pin SSOP Lead-Free

packages for production

• CY7C63613C available in 24-pin SOIC Lead-Free

packages for production

• Industry-standard programmer support

Functional Overview

The CY7C63413C/513C/613C are 8-bit RISC One Time

Programmable(OTP)microcontrollers.The instructionsethas

been optimized specifically for USB operations, although the

microcontrollers can be used for a variety of non-USB

embedded applications.

The CY7C63413C/513C features 32 General-Purpose I/O

(GPIO) pins to support USB and other applications. The I/O

pins are grouped into four ports (Port 0 to 3) where each port

can be configured as inputs with internal pull-ups, open drain

outputs,ortraditionalCMOS outputs.The CY7C63413C/513C

have 24 GPIO pins (Ports 0 to 2) that are rated at 7 mA typical

sink current. The CY7C63413C/513C has 8 GPIO pins (Port

3) that are rated at 12 mA typical sink current, which allows

these pins to drive LEDs.

The CY7C63613C features 16 General-Purpose I/O (GPIO)

pins to support USB and other applications. The I/O pins are

grouped into four ports (Port 0 to 3) where each port can be

configured as inputs with internal pull-ups, open drain outputs,

or traditional CMOS outputs. The CY7C63613C has 12 GPIO

pins (Ports 0 to 2) that are rated at 7 mA typical sink current.

The CY7C63613C has 4 GPIO pins (Port 3) that are rated at

12 mA typical sink current, which allows these pins to drive

LEDs.

Multiple GPIO pins can be connected together to drive a single

output for more drive current capacity. Additionally, each I/O

pin can be used to generate a GPIO interrupt to the microcon-

troller. Note the GPIO interrupts all share the same “GPIO”

interrupt vector.

The CY7C63513C features an additional 8 I/O pins in the DAC

port. Every DAC pin includes an integrated 14-Kohm pull-up

resistor. When a “1” is written to a DAC I/O pin, the output

current sink is disabled and the output pin is driven high by the

internal pull-up resistor. When a “0” is written to a DAC I/O pin,

the internal pull-up is disabled and the output pin provides the

programmed amount ofsink

current. A DAC I/O pin can

be used as an input with an

internal pull-up by writing a

“1” to the pin.

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Document #: 38-08027 Rev. *B Page 2 of 32

The sink current for each DAC I/O pin can be individually

programmed to one of sixteen values using dedicated Isink

registers. DAC bits [1:0] can be used as high current outputs

with a programmable sink current range of 3.2 to 16 mA

(typical). DAC bits [7:2] have a programmable current sink

range of 0.2 to 1.0 mA (typical). Again, multiple DAC pins can

be connected together to drive a single output that requires

more sink current capacity. Each I/O pin can be used to

generate a DAC interrupt to the microcontroller and the

interrupt polarity for each DAC I/O pin is individually program-

mable. The DAC port interrupts share a separate “DAC”

interrupt vector.

The Cypress microcontrollers use an external 6-MHz ceramic

resonator to provide a reference to an internal clock generator.

This clock generator reduces the clock-related noise

emissions (EMI). The clock generator provides the 6 and 12-

MHz clocks that remain internal to the microcontroller.

TheCY7C63413C/513C/613C are offeredwith singleEPROM

options. The CY7C63413C, CY7C63513C and the

CY7C63613C have 8 Kbytes of EPROM.

ThesepartsincludePower-onResetlogic,aWatchDogTimer,

a vectored interrupt controller, and a 12-bit free-running timer.

The Power-On Reset (POR) logic detects when power is

applied to the device, resets the logic to a known state, and

begins executinginstructions atEPROM address 0x0000. The

Watch Dog Timer can be used to ensure the firmware never

gets stalled for more than approximately 8 ms. The firmware

can get stalled for a variety of reasons, including errors in the

code or a hardware failure such as waiting for an interrupt that

never occurs. The firmware should clear the Watch Dog Timer

periodically. If the Watch Dog Timer is not cleared for approx-

imately 8 ms, the microcontroller will generate a hardware

watch dog reset.

The microcontroller supports eight maskable interrupts in the

vectoredinterruptcontroller.Interrupt sourcesinclude theUSB

Bus-Reset, the 128-µs and 1.024-ms outputs from the free-

running timer, three USB endpoints, the DAC port, and the

GPIOports.Thetimerbitscausean interrupt (ifenabled)when

the bit toggles from LOW “0” to HIGH “1.” The USB endpoints

interrupt after either the USB host or the USB controller sends

a packet to the USB. The DAC ports have an additional level

of masking that allows the user to select which DAC inputs can

cause a DAC interrupt. The GPIO ports also have a level of

masking to select which GPIO inputs can cause a GPIO

interrupt. For additional flexibility, the input transition polarity

that causes an interrupt is programmable for each pin of the

DAC port. Input transition polarity can be programmed for

each GPIO port as part of the port configuration. The interrupt

polarity can be either rising edge (“0” to “1”) or falling edge (“1”

to “0”).

The free-running 12-bit timer clocked at 1 MHz provides two

interrupt sources as noted above (128-µs and 1.024-ms). The

timer can be used to measure the duration of an event under

firmware control by reading the timer twice: once at the start

of the event, and once after the event is complete. The

difference between the two readings indicates the duration of

the event measured in microseconds. The upper four bits of

the timer are latched into an internal register when the

firmware reads the lower eight bits. A read from the upper four

bitsactually reads datafrom the internalregister, instead ofthe

timer. This feature eliminates the need for firmware to attempt

to compensate if the upper four bits happened to increment

right after the lower 8 bits are read.

The CY7C63413C/513C/613C include an integrated USB

serial interface engine (SIE) that supports the integrated

peripherals. The hardware supports one USB device address

with three endpoints. The SIE allows the USB host to commu-

nicate with the function integrated into the microcontroller.

Finally, the CY7C63413C/513C/613C support PS/2 operation.

With appropriate firmware the D+ and D– USB pins can also

be used as PS/2 clock and data signals. Products utilizing

these devices can be used for USB and/or PS/2 operation with

appropriate firmware.

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Document #: 38-08027 Rev. *B Page 3 of 32

Note:

1. CY7C63613C is not bonded out for all GPIO pins shown in Logic Block Diagram. Refer to pin configuration diagram for bonded out pins. See note on page 12

for firmware code needed for unused GPIO pins.

Logic Block Diagram

Interrupt

Controller

EPROM

12-bit

Timer

Reset

Watch Dog

Timer

Power-on

GPIO

PORT 1

GPIO

PORT 0

P0[0]

P0[7]

P1[0]

P1[7]

8-bit Bus

6-MHz ceramic resonator

RAM

USB

SIE

USB

Transceiver D+

D–

USB

GPIO

PORT 3

GPIO

PORT 2

P2[0]

P2[7]

P3[0]

P3[7]

DAC

PORT

DAC[0]

DAC[7]

High Current

Outputs

256 byte

4/6/8 Kbyte

OSC

6 MHz

12-MHz

8-bit

CPU

12 MHz

Pin Configuration

PS/2

PORT

CY7C63413C

D–

P3[6]

P3[4]

P3[2]

P3[0]

P2[6]

P2[4]

P3[7]

P3[5]

P3[3]

P3[1]

P2[7]

P2[5]

P2[3]

P2[1]

P1[7]

P1[5]

P1[3]

P1[1]

P0[7]

P0[5]

P0[3]

P0[1]

Vss

D+

P2[2]

P2[0]

P1[6]

P1[4]

P1[2]

P1[0]

P0[6]

P0[4]

P0[2]

P0[0]

XTAL

OUT

XTAL

40-pin PDIP

D–

24 25

VCC

Vss

P3[6]

P3[4]

P3[2]

P3[0]

P2[6]

P2[4]

P3[7]

P3[5]

P3[3]

P3[1]

P2[7]

P2[5]

P2[3]

P2[1]

P1[7]

P1[5]

P1[3]

P1[1]

P0[7]

P0[5]

P0[3]

P0[1]

VPP

Vss

D+

P2[2]

P2[0]

P1[6]

P1[4]

P1[2]

P1[0]

P0[6]

P0[4]

P0[2]

P0[0]

XTALOUT

XTALIN

CY7C63513C

D–

24 25

VCC

Vss

P3[6]

P3[4]

P3[2]

P3[0]

P2[6]

P2[4]

P3[7]

P3[5]

P3[3]

P3[1]

P2[7]

P2[5]

P2[3]

P2[1]

P1[7]

P1[5]

P1[3]

P1[1]

DAC[7]

DAC[5]

P0[7]

P0[5]

P0[3]

P0[1]

DAC[3]

DAC[1]

VPP

Vss

D+

P2[2]

P2[0]

P1[6]

P1[4]

P1[2]

P1[0]

DAC[6]

DAC[4]

P0[6]

P0[4]

P0[2]

P0[0]

DAC[2]

DAC[0]

XTALOUT

XTALIN

CY7C63413C

48-pin SSOP

D+

D–

P3[7]

P3[3]

P3[5]

P3[1]

P2[5]

P2[3]

P2[1]

P1[7]

P1[5]

P1[3]

P1[1]

P2[7]

DAC[3]

DAC[1]

Vss

XTAL

OUT

XTAL

DAC[7]

DAC[5]

P0[7]

P0[5]

P0[3]

P0[1]

DAC[6]

DAC[4]

P0[6]

P0[4]

P0[2]

P0[0]

DAC[2]

DAC[0] V

Vss

P3[6]

P3[4]

P3[2]

P3[0]

P2[6]

P2[4]

P2[2]

P2[0]

P1[6]

P1[4]

P1[2]

P1[0]

CY7C63413C

48-Pad Die

CY7C63613C

D–

24 V

P3[6]

P3[4]

P1[2]

P1[0]

P0[6]

P0[4]

P3[7]

P3[5]

P1[3]

P1[1]

P0[7]

P0[5]

P0[3]

P0[1]

Vss

D+

P0[2]

P0[0]

XTAL

OUT

XTAL

24-pin SOIC

CY7C63513C only

See Note 1

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Document #: 38-08027 Rev. *B Page 4 of 32

Programming Model

14-bit Program Counter (PC)

The 14-bit Program Counter (PC) allows access for up to 8

kilobytes of EPROM using the CY7C63413C/513C/613C

architecture. The program counter is cleared during reset,

such that the first instruction executed after a reset is at

address 0x0000. This is typically a jump instruction to a reset

handler that initializes the application.

The lower eight bits of the program counter are incremented

as instructions are loaded and executed. The upper six bits of

the program counter are incremented by executing an XPAGE

instruction. As a result, the last instruction executed within a

256-byte “page” of sequential code should be an XPAGE

instruction. The assembler directive “XPAGEON” will cause

the assembler to insert XPAGE instructions automatically. As

instructions can be either one or two bytes long, the assembler

may occasionally need to insert a NOP followed by an XPAGE

for correct execution.

The program counter of the next instruction to be executed,

carryflag, and zeroflagaresavedas twobyteson theprogram

stack during an interrupt acknowledge or a CALL instruction.

The program counter, carry flag, and zero flag are restored

from the program stack only during a RETI instruction.

Please note the program counter cannot be accessed directly

by the firmware. The program stack can be examined by

reading SRAM from location 0x00 and up.

8-bit Accumulator (A)

The accumulator is the general purpose, do everything

lated.

8-bit Index Register (X)

The index register “X” is available to the firmware as an

auxiliaryaccumulator. TheXregister alsoallowsthe processor

to perform indexed operations by loading an index value into

8-bit Program Stack Pointer (PSP)

During a reset, the Program Stack Pointer (PSP) is set to zero.

This means the program “stack” starts at RAM address 0x00

and “grows” upward from there. Note the program stack

pointer is directly addressable under firmware control, using

the MOV PSP,A instruction. The PSP supports interrupt

service under hardware control and CALL, RET, and RETI

instructions under firmware control.

Pin Definitions

Name I/O CY7C63413C CY7C63513C CY7C63613C Description40-Pin 48-Pin Die 48-Pin 24-Pin

D+, D– I/O 1,2 1,2 1,2 1,2 1,2 USB differential data; PS/2 clock and

data signals

P0[7:0] I/O 15,26,16

25,17,24

18,23

17,32,18

31,19,30

20,29

17,32,18,

31,19,30,

20,29

17,32,18,31,

19,30,20,29 7,18,8,17,9,

16, 10, 15 GPIO port 0 capable of sinking 7 mA

(typical)

P1[3:0] I/O 11,30,12,

29,13,28,

14,27

11,38,12,

37,13,36,

14,35

11,38,12,

37,13,36,

14,35

11,38,12,37,

13,36,14,35 5, 20, 6, 19 GPIO Port 1 capable of sinking 7 mA

(typical).

P2 I/O 7,34,8,

33,9,32,

10,31

7,42,8,

41,9,40,

10,39

7,42,8,

41,9,40,

10,39

7,42,8,41,9,

40,10,39 n/a GPIO Port 2 capable of sinking 7 mA

(typical).

P3[7:4] I/O 3,38,4,

37,5,36,

6,35

3,46,4,

45,5,44,

6,43

3,46,4,

45,5,44,

6,43

3,46,4,45,5,

44,6,43 3, 22, 4, 21 GPIO Port 3 capable of sinking 12 mA

(typical).

DAC I/O n/a n/a 15,34,16,

33,21,28,

22,27

15,34,16,33,

21,28,22,27 n/a DAC I/O Port with programmable

current sink outputs. DAC[1:0] offer a

programmable range of 3.2 to 16 mA

typical. DAC[7:2] have a program-

mable sink current range of 0.2 to 1.0

mA typical. DAC I/O Port not bonded

out on CY7C63613C. See note on

page 12 for firmware code needed for

unused pins.

XTALIN IN 21 25 25 25 13 6-MHz ceramic resonator or external

clock input

XTALOUT OUT 22 26 26 26 14 6-MHz ceramic resonator

VPP 19 23 23 23 11 Programming voltage supply, ground

during operation

VCC 40 48 48 48 24 Voltage supply

Vss 20,39 24,47 24,47 24,47 12, 23 Ground

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During an interrupt acknowledge, interrupts are disabled and

the 14-bit program counter, carry flag, and zero flag are written

as two bytes of data memory. The first byte is stored in the

memory addressed by the program stack pointer, then the

PSP is incremented. The second byte is stored in memory

addressed by the program stack pointer and the PSP is incre-

mented again. The net effect is to store the program counter

and flags on the program “stack” and increment the program

stack pointer by two.

The Return From Interrupt (RETI) instruction decrements the

program stack pointer, then restores the second byte from

memory addressed by the PSP. The program stack pointer is

decremented again and the first byte is restored from memory

addressed by the PSP. After the program counter and flags

havebeenrestored from stack,theinterruptsare enabled. The

effect is to restore the program counter and flags from the

program stack, decrement the program stack pointer by two,

and re-enable interrupts.

The Call Subroutine (CALL) instruction stores the program

counter and flags on the program stack and increments the

PSP by two.

The Return From Subroutine (RET) instruction restores the

program counter, but not the flags, from program stack and

decrements the PSP by two.

8-bit Data Stack Pointer (DSP)

The Data Stack Pointer (DSP) supports PUSH and POP

instructions that use the data stack for temporary storage. A

PUSH instruction will pre-decrement the DSP, then write data

to the memory location addressed by the DSP. A POP

instruction will read data from the memory location addressed

by the DSP, then post-increment the DSP.

During a reset, the Data Stack Pointer will be set to zero. A

PUSH instruction when DSP equal zero will write data at the

top of the data RAM (address 0xFF). This would write data to

the memory area reserved for a FIFO for USB endpoint 0. In

non-USB applications, this works fine and is not a problem.

For USB applications, it is strongly recommended that the

DSP is loaded after reset just below the USB DMA buffers.

Address Modes

The CY7C63413C/513C/613C microcontrollers support three

addressing modes for instructions that require data operands:

data, direct, and indexed.

Data

The “Data” address mode refers to a data operand that is

actually a constant encoded in the instruction. As an example,

consider the instruction that loads A with the constant 0xE8:

• MOV A,0E8h

This instruction will require two bytes of code where the first

byte identifies the “MOV A” instruction with a data operand as

the second byte. The second byte of the instruction will be the

constant “0xE8”. A constant may be referred to by name if a

prior “EQU” statement assigns the constant value to the name.

For example, the following code is equivalent to the example

shown above:

• DSPINIT: EQU 0E8h

• MOV A,DSPINIT

Direct

“Direct” address mode is used when the data operand is a

variable stored in SRAM. In that case, the one byte address of

the variable is encoded in the instruction. As an example,

consider an instruction that loads A with the contents of

memory address location 0x10:

• MOV A, [10h]

In normal usage, variable names are assigned to variable

addresses using “EQU” statements to improve the readability

of the assembler source code. As an example, the following

code is equivalent to the example shown above:

• buttons: EQU 10h

• MOV A,[buttons]

Indexed

“Indexed” address mode allows the firmware to manipulate

arrays of data stored in SRAM. The address of the data

operand is the sum of a constant encoded in the instruction

and the contents of the “X” register. In normal usage, the

constant will be the “base” address of an array of data and the

X register will contain an index that indicates which element of

the array is actually addressed:

• array: EQU 10h

•MOVX,3

• MOV A,[x+array]

This would have the effect of loading A with the fourth element

of the SRAM “array” that begins at address 0x10. The fourth

element would be at address 0x13.

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Instruction Set Summary

MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles

HALT 00 7 NOP 20 4

ADD A,expr data 01 4 INC A acc 21 4

ADD A,[expr] direct 02 6 INC X x 22 4

ADD A,[X+expr] index 03 7 INC [expr] direct 23 7

ADC A,expr data 04 4 INC [X+expr] index 24 8

ADC A,[expr] direct 05 6 DEC A acc 25 4

ADC A,[X+expr] index 06 7 DEC X x 26 4

SUB A,expr data 07 4 DEC [expr] direct 27 7

SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8

SUB A,[X+expr] index 09 7 IORD expr address 29 5

SBB A,expr data 0A 4 IOWR expr address 2A 5

SBB A,[expr] direct 0B 6 POP A 2B 4

SBB A,[X+expr] index 0C 7 POP X 2C 4

OR A,expr data 0D 4 PUSH A 2D 5

OR A,[expr] direct 0E 6 PUSH X 2E 5

OR A,[X+expr] index 0F 7 SWAP A,X 2F 5

AND A,expr data 10 4 SWAP A,DSP 30 5

AND A,[expr] direct 11 6 MOV [expr],A direct 31 5

AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6

XOR A,expr data 13 4 OR [expr],A direct 33 7

XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8

XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7

CMP A,expr data 16 5 AND [X+expr],A index 36 8

CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7

CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8

MOV A,expr data 19 4 IOWX [X+expr] index 39 6

MOV A,[expr] direct 1A 5 CPL 3A 4

MOV A,[X+expr] index 1B 6 ASL 3B 4

MOV X,expr data 1C 4 ASR 3C 4

MOV X,[expr] direct 1D 5 RLC 3D 4

reserved 1E RRC 3E 4

XPAGE 1F 4 RET 3F 8

MOV A,X 40 4 DI 70 4

MOV X,A 41 4 EI 72 4

MOV PSP,A 60 4 RETI 73 8

CALL addr 50-5F 10

JMP addr 80-8F 5 JC addr C0-CF 5

CALL addr 90-9F 10 JNC addr D0-DF 5

JZ addr A0-AF 5 JACC addr E0-EF 7

JNZ addr B0-BF 5 INDEX addr F0-FF 14

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Memory Organization

Program Memory Organization

after reset Address

14-bit PC 0x0000 Program execution begins here after a reset

0x0002 USB Bus Reset interrupt vector

0x0004 128-µs timer interrupt vector

0x0006 1.024-ms timer interrupt vector

0x0008 USB address A endpoint 0 interrupt vector

0x000A USB address A endpoint 1 interrupt vector

0x000C USB address A endpoint 2 interrupt vector

0x000E Reserved

0x0010 Reserved

0x0012 Reserved

0x0014 DAC interrupt vector

0x0016 GPIO interrupt vector

0x0018 Reserved

0x001A Program Memory begins here

(8K - 32 bytes)

0x1FDF 8-KB PROM ends here (CY7C63413C, CY7C63513C, CY7C63613C)

Figure 1. Program Memory Space with Interrupt Vector Table

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Data Memory Organization

The CY7C63413C/513C/613C microcontrollers provide 256

bytes of data RAM. In normal usage, the SRAM is partitioned

into four areas: program stack, data stack, user variables and

USB endpoint FIFOs as shown below:

after reset Address

8-bit PSP 0x00 Program Stack begins here and grows upward

8-bit DSP user Data Stack begins here and grows downward

The user determines the amount of memory required

User Variables

0xE8 USB FIFO for Address A endpoint 2

0xF0 USB FIFO for Address A endpoint 1

0xF8 USB FIFO for Address A endpoint 0

Top of RAM Memory 0xFF

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I/O Register Summary

I/O registers are accessed via the I/O Read (IORD) and I/O

Write (IOWR, IOWX) instructions. IORD reads the selected

port into the accumulator. IOWR writes data from the accumu-

lator to the selected port. Indexed I/O Write (IOWX) adds the

contents of X to the address in the instruction to form the port

address and writes data from the accumulator to the specified

port. Note that specifying address 0 (e.g., IOWX 0h) means

the I/O port is selected solely by the contents of X.

Table 1. I/O Register Summary

Port 0 Data 0x00 R/W GPIO Port 0

Port 1 Data 0x01 R/W GPIO Port 1

Port 2 Data 0x02 R/W GPIO Port 2

Port 3 Data 0x03 R/W GPIO Port 3

Port 0 Interrupt Enable 0x04 W Interrupt enable for pins in Port 0

Port 1 Interrupt Enable 0x05 W Interrupt enable for pins in Port 1

Port 2 Interrupt Enable 0x06 W Interrupt enable for pins in Port 2

Port 3 Interrupt Enable 0x07 W Interrupt enable for pins in Port 3

GPIO Configuration 0x08 R/W GPIO Ports Configurations

USB Device Address A 0x10 R/W USB Device Address A

EP A0 Counter Register 0x11 R/W USB Address A, Endpoint 0 counter register

EP A0 Mode Register 0x12 R/W USB Address A, Endpoint 0 configuration register

EP A1 Counter Register 0x13 R/W USB Address A, Endpoint 1 counter register

EP A1 Mode Register 0x14 R/C USB Address A, Endpoint 1 configuration register

EP A2 Counter Register 0x15 R/W USB Address A, Endpoint 2 counter register

EP A2 Mode Register 0x16 R/C USB Address A, Endpoint 2 configuration register

USB Status & Control 0x1F R/W USB upstream port traffic status and control register

Global Interrupt Enable 0x20 R/W Global interrupt enable register

Endpoint Interrupt Enable 0x21 R/W USB endpoint interrupt enables

Timer (LSB) 0x24 R Lower eight bits of free-running timer (1 MHz)

Timer (MSB) 0x25 R Upper four bits of free-running timer that are latched

when the lower eight bits are read.

WDR Clear 0x26 W Watch Dog Reset clear

DAC Data 0x30 R/W DAC I/O[2]

DAC Interrupt Enable 0x31 W Interrupt enable for each DAC pin

DAC Interrupt Polarity 0x32 W Interrupt polarity for each DAC pin

DAC Isink 0x38-0x3F W One four bit sink current register for each DAC pin

Processor Status & Control 0xFF R/W Microprocessor status and control

Note:

2. DAC I/O Port not bonded out on CY7C63613C. See note on page 12 for firmware code needed for unused GPIO pins.

[+] Feedback

CY7C63413C

CY7C63513C

CY7C63613C

Document #: 38-08027 Rev. *B Page 10 of 32

Clocking

The XTALIN and XTALOUT are the clock pins to the microcon-

troller. The user can connect a low-cost ceramic resonator or

an external oscillator can be connected to these pins to

provide areference frequency for theinternalclock distribution

and clock doubler.

An external 6-MHz clock can be applied to the XTALIN pin if

the XTALOUT pin is left open. Please note that grounding the

XTALOUT pin is not permissible as the internal clock is effec-

tively shorted to ground.

Reset

The USB Controller supports three types of resets. All

registers are restored to their default states during a reset. The

USB Device Addresses are set to 0 and all interrupts are

disabled. In addition, the Program Stack Pointer (PSP) and

Data Stack Pointer (DSP) are set to 0x00. For USB applica-

tions, the firmware should set the DSP below 0xE8 to avoid a

memory conflict with RAM dedicated to USB FIFOs. The

assembly instructions to do this are shown below:

Mov A, E8h ; Move 0xE8 hex into Accumulator

Swap A,dsp ; Swap accumulator value into dsp register

The three reset types are:

1. Power-On Reset (POR)

2. Watch Dog Reset (WDR)

3. USB Bus Reset (non hardware reset)

The occurrence of a reset is recorded in the Processor Status

and Control Register located at I/O address 0xFF. Bits 4, 5,

and 6 are used to record the occurrence of POR, USB Reset,

andWDR respectively. Thefirmware caninterrogatethesebits

to determine the cause of a reset.

The microcontroller begins execution from ROM address

0x0000 after a POR or WDR reset. Although this looks like

interrupt vector 0, there is an important difference. Reset

processing does NOT push the program counter, carry flag,

and zero flag onto program stack. That means the reset

handler in firmware should initialize the hardware and begin

executingthe“main”loopof code.Attemptingto execute either

a RET or RETI in the reset handler will cause unpredictable

execution results.

Power-On Reset (POR)

Power-On Reset (POR) occurs every time the VCC voltage to

the device ramps from 0V to an internally defined trip voltage

(Vrst)of approximately1/2full supplyvoltage. Inadditiontothe

normal reset initialization noted under “Reset,” bit 4 (PORS) of

the Processor Status and Control Register is set to “1” to

indicate to the firmware that a Power-On Reset occurred. The

POR event forces the GPIO ports into input mode (high

impedance), and the state of Port 3 bit 7 is used to control how

the part will respond after the POR releases.

If Port 3 bit 7 is HIGH (pulled to VCC) and the USB IO are at

the idle state (DM HIGH and DP LOW) the part will go into a

semi-permanent power down/suspend mode, waiting for the

USB IO to go to one of Bus Reset, K (resume) or SE0. If Port

3 bit 7 is still HIGH when the part comes out of suspend, then

a128-µs timerstarts,delaying CPUoperationuntil theceramic

resonator has stabilized.

If Port 3 bit 7 was LOW (pulled to VSS) the part will start a 96-

ms timer, delaying CPU operation until VCC has stabilized,

then continuing to run as reset.

Firmware should clear the POR Status (PORS) bit in register

0xFF before going into suspend as this status bit selects the

128-µs or 96-ms start-up timer value as follows: IF Port 3 bit 7

is HIGH then 128-µs is always used; ELSE if PORS is HIGH

then 96-ms is used; ELSE 128-µs is used.

Watch Dog Reset (WDR)

The Watch Dog Timer Reset (WDR) occurs when the Most

Significant Bit (MSB) of the 2-bit Watch Dog Timer Register

transitions from LOW to HIGH. In addition to the normal reset

Figure 2. Clock Oscillator On-chip Circuit

XTALOUT

XTALIN

Clock Distribution

clk2x Clock

Doubler

clk1x

(to Microcontroller)

(to USB SIE)

30 pF

At least 8.192 ms WDR goes high Execution begins at

Reset Vector 0X00

8.192 ms

2.048 ms

since last write to WDT for 2.048 ms

to 14.336 ms

Figure 3. Watch Dog Reset (WDR)

[+] Feedback

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