Texas Instruments TRF3765 Series Manual de usuario

User's Guide

SLWU076A–November 2011–Revised July 2012

TRF3765 Integer/Fractional-N PLL With Integrated VCO

Evaluation Module

This document describes usage and features of the TRF3765 evaluation module (EVM) for wideband

frequency synthesis applications. The synthesizer uses an integer/fractional-N PLL with integrated VCOs

to generate local oscillator signals from 300 MHz to 4800 MHz. This document describes rapid-start setup

procedures, detailed descriptions of circuit blocks and available options, schematics and printed-circuit

board layout, and a common start-up problem troubleshooting guide.

Contents

1 Quick-Start Operating Procedures ........................................................................................ 2

2 Circuit Block Descriptions .................................................................................................. 2

2.1 Test Points .......................................................................................................... 2

2.2 Power Supply ....................................................................................................... 3

2.3 Loop Filter ........................................................................................................... 3

2.4 SPI Communication ................................................................................................ 4

2.5 Reference Clock ................................................................................................... 4

3 Configuration Options ...................................................................................................... 4

4 Physical Description ........................................................................................................ 5

4.1 Schematic ........................................................................................................... 5

4.2 Layout ............................................................................................................... 8

4.3 Bill of Materials .................................................................................................... 12

5 Troubleshooting FAQs .................................................................................................... 15

List of Figures

1 Loop Filter Reference Designators ....................................................................................... 4

2 TRF3765EVM Schematic, Page 1 of 3 .................................................................................. 5

3 TRF3765EVM Schematic, Page 2 of 3 .................................................................................. 6

4 TRF3765EVM Schematic, Page 3 of 3 .................................................................................. 7

5 Silkscreen, Top.............................................................................................................. 8

6 Top Layer and Drill Map ................................................................................................... 9

7 Layer 2, Ground ........................................................................................................... 10

8 Layer 3, Power............................................................................................................. 11

9 Bottom Layer and Silkscreen ............................................................................................ 12

10 Fabrication Drawing....................................................................................................... 12

List of Tables

1 Test Point Color Codes .................................................................................................... 2

2 Integer and Fractional Mode Configurations ............................................................................ 5

3 Fractional Board Bill of Materials........................................................................................ 12

4 Integer Board Bill of Materials, Differences from Fractional Board ................................................. 14

5 Troubleshooting Sequences ............................................................................................. 15

SLWU076A–November 2011–Revised July 2012 TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module

Quick-Start Operating Procedures

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1 Quick-Start Operating Procedures

The TRF3765 evaluation module (EVM) is preconfigured to use a 3.3-Vdc power supply on TP2. The

supply must be capable of supplying 250 mA.

SPI communication is required for configuring the TRF3765 device. J7 accepts a mini-USB connector that

can be driven through the device graphical user interface (GUI).

Local oscillator (LO) outputs are available in four differential pairs on SMA coaxial connectors J1, J3-J6,

and J9-J11.

The following steps describe the EVM setup for basic operation with the default hardware configuration.

1. Connect the mini-USB connector. LED D1 draws power through the mini-USB connector and

illuminates immediately.

2. Power the device by supplying TP2 with 3.3 V. Use TP3 for the ground connection. Board revisions

prior to Revision D may require additional power supply connections.

3. Connect the LO output to measurement equipment.

4. Install and start the GUI software.

5. Initiate a communication link with the device by using the GUI Connect button. Follow on-screen

instructions to load a register configuration file. Select file TRF3765.FracMode.3p3Vtank.2600MHz.txt

for a fractional mode board and TRF3765.IntMode.3p3Vtank.2600MHz.txt for an integer mode board.

6. Verify lock-detect on LED D2 and the signal on measurement equipment. If D2 is not illuminated, no

signal is present or the signal is at the incorrect frequency. Check GUI settings on any of the High

Level tabs and recalibrate.

7. Using default hardware and configuration settings, fractional mode integrate phase noise is –47 dBc to

–48 dBc/Hz, whereas integer mode integrated phase is –44 dBc/Hz.

2 Circuit Block Descriptions

This section describes each of the major circuit blocks and their configuration options.

2.1 Test Points

Test points are used throughout the board for control and monitoring. These test points are color-coded

for quick reference. The color codes are described in Table 1.

Table 1. Test Point Color Codes

Color Group Reference Designators

Black Ground TP1, TP3, TP4, TP11, TP14, TP27-TP30

White Unregulated supply TP2, TP24

Red Unregulated supply TP5

Purple Regulated supply TP25, TP26

Green VCC and SPI monitor TP6-TP10, TP12, TP13, TP19-TP23

Blue VCC1 monitor TP15-TP18

2TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module SLWU076A–November 2011–Revised July 2012

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Circuit Block Descriptions

2.2 Power Supply

The TRF3765 uses three primary power supplies: VCC1, VCC2, and VCC3. In the default configuration,

VCC1 and VCC2 are connected onboard by R41 and VCC3 is unused. The entire board can be supplied

through 3.3 V on TP2 or Revision D boards. Earlier board revisions require multiple power connections.

A clean power supply is critical to optimal phase noise performance of the synthesizer. The impact of the

power supply is discussed in detail in the application report Supply Noise Effect on Oscillator Phase Noise

(SLWA066). Linear power supplies are the best sources available. Switching power supplies degrade in-

band phase noise by 10 dB compared to linear laboratory supplies. Onboard regulators U3 and U4 are

ultra-clean TPS74201 linear regulators that also provide excellent performance when they are driven by

most laboratory power supply equipment. These regulators provide performance comparable to a clean

linear supply. To use these regulated 3.3-V supplies, disconnect power from TP2 and remove R41.

Connect 5 V to TP26, using TP27 for ground. Place jumpers on JP4 and JP5 to shunt jumper pins 1 and

VCC3 can be used to drive VCC_TK, a 3.3-V/5-V tolerant supply on the TRF3765. VCC_TK is normally

driven by the 3.3-V VCC2 supply, but some applications perform better with a 5-V supply on VCC_TK. To

use VCC3 to drive VCC_TK at 5 V, move FB2 onto FB11. Populate R12 with a short. Then drive VCC3

through TP5 with a clean linear laboratory supply at 5 V.

VCC3 can also be driven at 5 V by onboard regulator U5. However, this regulator is not as clean as a

linear laboratory supply, and some phase noise performance loss occurs. To use the VCC3 onboard 5-V

regulator, drive TP25 with 6 V using TP28 for ground and place a jumper on JP1 to shunt jumper pins 1

and 2.

The TRF3765EVM includes a power supply filter. This filter can be used to reduce in-band frequency

noise from a switching power supply so that an external supply can drive 5 V on VCC_TK. Phase noise

performance using a high-quality laboratory switching power supply to drive VCC3 through TP5 is similar

to performance measured using a linear supply. The filter is integrated on Rev. E and later boards. Rev. D

and earlier boards include an external filter that is equipped with BNC connectors for a convenient

connection with power supply banana jacks.

Each VCC pin on the TRF3765 connects to an individual test point. The test point may be used for

monitoring. Because each supply pin is isolated through a ferrite bead, by lifting the ferrite bead these test

points may also be used to drive single-device supply pins.

Spurs occurring in the LO signal at 60 kHz and 100 kHz offset from the carrier are usually the result of

ground loops in power supply cabling.

2.3 Loop Filter

Loop-filter components are also critical to optimal phase noise performance. The loop filter must be

matched to the selected phase frequency detector (PFD) frequency. TRF3765 boards are shipped with

components matched to the onboard reference clock and configuration file. However, to use a different

PFD frequency, the loop-filter components must be updated. The Loop Filter Design Tool available at

ti.com in the TRF3765EVM product folder is an intuitive software package that identifies proper

component values.

Loop filter reference designators are shown in Figure 1. The assembly layout of these components is

shown in a silkscreen blow-up on the EVM.

SLWU076A–November 2011–Revised July 2012 TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module

C1 C2 C3

CP_OUT VTUNE_IN

CP_REF VTUNE_REF

R15R13

R20

R45

R46

TP12

VCC2

Configuration Options

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Figure 1. Loop Filter Reference Designators

VTune may be monitored on TP12 without disrupting circuit operation, because R20 is a high-value

resistance. TP12 can also be used to drive VTune for open-loop VCO measurements when the TRF3765

charge pump is in 3-state logic. A 1-µF capacitor on C4 is also recommended for open-loop

measurements to help stabilize the applied voltage.

By default, reference is tied to ground through shorts on R13, R15, and R45, with R46 open.

2.4 SPI Communication

SPI communication from the TRF3765 GUI passes through mini-USB connector J7. The USB interface is

decoded and encoded by U2 into SPI lines DATA, STROBE, CLK, and RDBK. U2 is powered through the

USB connection instead of the board supply, and LED D1 indicates USB power is applied. Test points

TP6–TP10 can be used to monitor SPI communication with laboratory equipment. The laboratory

equipment must be set to high impedance so that it does not load the communication lines.

When the USB cable is disconnected, U2 I/Os are high impedance. In this case, TP6–TP10 can be used

to directly drive the SPI lines.

The power-on reset default register settings in the TRF3765 do not correspond to a valid operational state.

SPI initialization is required to operate the device. Once the registers have been initialized, the mini-USB

cable may be disconnected without disrupting device operation. However, once the mini-USB has been

reconnected, the link must be reestablished through the GUI Connect button on the Start Up tab. The link

exists between the GUI computer and U2, so loss of power to the TRF3765 device does not require

reestablishing the link. Loss of device power, however, does require re-initialization of the registers.

2.5 Reference Clock

An oscillator is installed on the TRF3765EVM to provide a reference clock to the device. JP2 installed

provides supply voltage to the oscillator, whereas JP3 installed connects the oscillator output to the

TRF3765. The oscillator frequency drifts over temperature and is not rated for the full TRF3765

temperature operating range, so temperature testing must use an external reference clock.

An external reference clock can be supplied through the SMA connector J8. When using an external

reference clock, remove jumpers on JP2 and JP3. The external reference is ac-coupled to the TRF3765

input pin. An external reference can also be used to frequency-lock the device to laboratory equipment.

Verify that any supplied reference clock has low phase noise.

3 Configuration Options

The TRF3765 evaluation module ships configured for either integer mode or fractional mode. Each

configuration is designed to use different reference and PFD frequencies and also has the corresponding

loop-filter components. Differences in integer mode and fractional mode boards are listed in Table 2.

4TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module SLWU076A–November 2011–Revised July 2012

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C41

47pF

C17

47pF

DNI

LED AMBER

C23

1uF

C72

0.1uF

DNI

C31

47pF

C53

1uF

10nF

R10

DNI

FB2

C21

10nF

R23 100

LO4_OUTP

5234

SMA

END

TP18

BLU

VCC_LO4

C51

4.7pF

C28

1uF

FB11

DNI

FB4

C38

47pF

C59

10nF

R3 0

LO1_OUTP

5234

SMA

END

R34

DNI

TP20

GRN

VCC_DIG

FB13

C37

1uF

R19

15K

TP15

BLU

VCC_LO1

LO3_OUTM

5234

SMA

END

C18

10nF

R40

DNI

R24 100

4.7pF

R12

DNI

C49

27pF

C11

47pF

C12

10nF

R7 0

TP13

GRN

VCC_TK

TRF3765

GND_DIG

VCC_DIG

DATA

CLOCK

STROBE

READBACK

VCC_DIV

GND_BUFF1

LO1_OUTP

LO1_OUTM

LO2_OUTM

LO2_OUTP

LO3_OUTP

LO3_OUTM

LO4_OUTM

LO4_OUTP

GND_BUFF2 17

EXTVCO_IN 18

EXTVCO_CTRL 19

VCC_TK 20

VCC_OSC 21

GND_OSC 22

VTUNE_IN 23

VTUNE_REF 24

CP_REF 25

CP_OUT 26

VCC_CP 27

VCC_PLL 28

GND 29

REF_IN 30

GND 31

LD 32

PWRPAD 33

R27 100

FB12

C50

1uF

FB6

R30

DNI

R11 0

1uF

J11

LO2_OUTM

5234

SMA

END

R25 100

C10 4.7pF

R28 100

LO1_OUTM

5234

SMA

END

C52

10nF

C39

1uF

FB5

47pF

27pF

R33 0

FB15

R37

DNI

C27

27pF

TP8

GRN

TP23

GRN

VCC_OSC

C13

10nF

R26 100

TP19

GRN

VCC_DIV

C43

.1uF

DNI

C47

47pF

C54

1uF

EXT_VCO

5234

SMA

END

TP22

GRN

VCC_CP

R29 0

R35 0

SJP1

EXTVCO_CTRL_OUT

C55

27pF

LO4_OUTM

5234

SMA

END

C56

10nF

C45

1uF

C57

4.7pF

C44

47pF

DNI

TP16

BLU

VCC_LO2

R39

DNI

R31 0

49.9

DNI

C46

47pF

LO3_OUTP

5234

SMA

END

TP21

GRN

VCC_PLL

C16

.1uF

DNI

C48

27pF

R22 100

TP17

BLU

VCC_LO3

R36

DNI

FB8

FB14

J10

LO2_OUTP

5234

SMA

END

C22

4.7pF

C32

47pF

C40

1uF

R21 100

FB1

R32

DNI

C24

4.7pF

R2 0 LO1P

LO1M

LO2M

LO2P

LO3P

LO3M

LO4M

LO4P

EXTVCO

EXT_VCO

LO1_P

LO1_M

LO2_M

LO2_P LO3_P

LO3_M

LO4_M

LO4_P

GNDGND GND GND

GND

GNDGND GND GND

GND

GNDGND GND GND

GND

GNDGND GND GND

GND

GND GND

VCC2

GND GNDGND

VCC2

GND

GND GND

GND

VCC2

GND

GND GND

VCC1

GND

VCC3

VCC2

GNDGND

GND

GND GND GND

VCC2

GND GND

GND

VCC2

GND

VCC1

GND

DATASH2

CLKSH2

STROBESH2

RDBKSH2

REFINSH2

RF_VTUNE SH2

RF_CP_OUT SH2

RF_CP_REF

RF_VTUNE_REF

SHUNT 2-3

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Physical Description

Table 2. Integer and Fractional Mode Configurations

Item Fractional Mode Integer Mode

Oscillator Y1 frequency 61.44 MHz Y1 frequency 40 MHz

Typical PFD frequency 30.72 MHz 1.6 MHz

C20 = 2200 pF C20 = 47 pF

C19 = 22000 pF C19 = 560 pF

R6 = 475 ΩR6 = 10 kΩ

Loop filter components R5 = 475 ΩR5 = 5 kΩ

C14 = 220 pF C14 = 4.7 pF

R4 = 475 ΩR4 = 0 Ω

C15 = 220 pF C15 = open

Configuration file TRF3765.FracMode.3p3Vtank.2600MHz.txt TRF3765.IntMode.3p3Vtank.2600MHz.txt

4 Physical Description

The TRF3765EVM is designed to be a high-performance platform for the TRF3765 device. This section

describes the schematic, layout and stackup, and bill of materials corresponding to Revision D boards.

4.1 Schematic

Figure 2. TRF3765EVM Schematic, Page 1 of 3

SLWU076A–November 2011–Revised July 2012 TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module

TP6

GRN

RDBK

C34

.1uF

FB10

C19

560pF

1 2

R17

15K

R14

10K

DNI

C67

100pF

EXT_REF

5234

SMA

END

R15

1 2

10K

R18

DNI

1 2

4.99K

1 2

JP3

C30

.1uF

DNI

1 2

C35

47pF

R16

49.9

DNI

1 2

R45 0

1 2

USB_PWR

LED AMBER

1 2

120

FB7

USB_SUPER-MINI_AB

VBUS 1

D- 2

D+ 3

ID 4

GND 5

GND1

GND2

GND3

GND4

C26 22pF

C36

.1uF

C25

.01uF

TP10

GRN

DATA

R20

C14

4.7pF

1 2

TSM75-1148-40.000M

1VCC 4

OUT 3

GND

C29

47pF

C15

2.2pF

DNI

1 2

TP9

GRN

CLK

FT245RL

USBDM

USBDP

VCCIO

NC1

RESET

NC2

OSCI

OSCO

3V3OUT

AGND

GND

TEST

26 PWREN 12

WR 14

D1 5

D7 6

D5 9

D6 10

TXE 22

D4 2

D3 11

RXF 23

D0 1

RD 13

VCC

D2 3

C20

47pF

1 2

TP7

GRN

STROBE

C33

.1uF

1 2

TP11

BLK

GND

JP2

R13

1 2

R38 0

R46 0

DNI

TP12

GRN

VTUNE

EXT_REF

GND

GND GNDGND GND

GND GND

GND

GNDGND

GND

VCC2

GND

VCC2

RF_CP_OUTSH1 RF_VTUNE SH1

REFIN SH1

CLK SH1

DATA SH1

RDBK SH1

STROBE SH1

RF_VTUNE_REF SH1RF_CP_REFSH1

SERIAL INTERFACE

RF/IF FREQ REF

INTERFACE

TABLE 1

INTEGER FRACTIONAL

C14

C15

C19

C20

4.7pF

DNI

560pF

47pF

4.99K

10K

220pF

22000pF

2200pF

470pF

Physical Description

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Figure 3. TRF3765EVM Schematic, Page 2 of 3

6TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module SLWU076A–November 2011–Revised July 2012

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TP4

BLK

GND

SCREW PHIL 4-40 X 3/8"

1uF SH5

RF SHIELD 1

TP2

WHT

VCC1_+3.3V

MT1

C65

1uF

TPS74201RGW

IN1

5OUT1 1

BIAS

OUT2 18

OUT3 19

OUT4 20

IN2

IN3

IN4

FB/SNS 16

PG 9

NC1 2

NC2 3

NC3 4

NC4 13

NC5

NC6

GND

PAD

MT2

TP1

BLK

GND

JP1

VCC3_+5V

C63

10uF

TP5

RED

VCC3_+5V

TP27

BLK

GND

C58

100uF

MT3

R48 10K

SH1

RF SHIELD 1

TP25

PURPLE

+6.0V

TP26

PURPLE

+5.0V

.1uF

MT4

TP29

BLK

GND

C79

10uF

C66

.1uF

R49

52.3K

SH2

RF SHIELD 1

C64

1uF

TP28

BLK

GND

C80

10uF

C74

160pF

TP30

BLK

GND

C69

100uF

SH3

RF SHIELD 1

BARE BOARD, TRF3765

1uF

C81

10uF

C68

1uF

JP4

VCC2_+3.3V

C75

10uF

SH4

RF SHIELD 1

C70

10uF

TP24

WHT

VCC2_+3.3V

C42

100uF

C76

10uF

TPS7A8001

OUT1 1

OUT2 2

GND 4

IN2

FB/SNS 3

IN1

PAD 9

TP14

BLK

GND

TPS74201RGW

IN1

5OUT1 1

BIAS

OUT2 18

OUT3 19

OUT4 20

IN2

IN3

IN4

FB/SNS 16

PG 9

NC1 2

NC2 3

NC3 4

NC4 13

NC5

NC6

GND

PAD

R50

31.6K

R52

31.6K

R47

10K

.1uF

TP3

BLK

GND

R51

10.2K

SCREW PHIL 4-40 X 3/8"

R53

10.2K

SCREW PHIL 4-40 X 3/8"

C73

10uF

C62

1uF

R54 10K

JP5

VCC1_+3.3V

C78

10uF

SCREW PHIL 4-40 X 3/8"

GND

GNDGND GND

VCC2

GND

GND GND

VCC1

VCC3

GNDGND

GND GND

+6.0V VCC3

GND

+5.0V

GND

+5.0V

GND

VCC2

GND

+5.0V

GND

+5.0V

GND

VCC1

GND

RF FENCE AND COVER

QTY 1

BOARD HARDWARE

NO SHUNT

R48 0

VCC2

VCC1

C82

4.7uF

GND

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Physical Description

Figure 4. TRF3765EVM Schematic, Page 3 of 3

SLWU076A–November 2011–Revised July 2012 TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module

Physical Description

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4.2 Layout

Figure 5. Silkscreen, Top

8TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module SLWU076A–November 2011–Revised July 2012

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Physical Description

Figure 6. Top Layer and Drill Map

SLWU076A–November 2011–Revised July 2012 TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module

Physical Description

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Figure 7. Layer 2, Ground

10 TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module SLWU076A–November 2011–Revised July 2012

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