Texas Instruments DAC9881 Manual de usuario

User's Guide

SLAU279A–March 2009–Revised November 2009

DAC9881 Evaluation Module

This user’s guide describes the characteristics, operation, and the use of the DAC9881 Evaluation Module

(EVM). It covers all pertinent areas involved to properly use this EVM board along with the devices that it

supports. The physical PCB layout, schematic diagram, and circuit descriptions are included.

Contents

1 EVM Overview ............................................................................................................... 2

1.1 Features ............................................................................................................. 2

1.2 Power Requirements .............................................................................................. 2

1.3 EVM Basic Functions .............................................................................................. 3

2 PCB Design and Performance ............................................................................................ 4

2.1 PCB Layout ......................................................................................................... 4

3 EVM Performance .......................................................................................................... 7

4 Bill of Materials .............................................................................................................. 9

5 EVM Operation ............................................................................................................ 10

5.1 Factory Default Setting .......................................................................................... 10

5.2 Host Processor Interface ........................................................................................ 11

5.3 Digital Control Interface .......................................................................................... 11

5.4 Analog Output ..................................................................................................... 12

5.5 Jumper Setting .................................................................................................... 14

5.6 DAC9881EVM Schematic ....................................................................................... 16

6 Using the DAC9881EVM with DXP ..................................................................................... 16

6.1 Hardware .......................................................................................................... 16

6.2 MMB0 Power Supplies ........................................................................................... 17

6.3 Software – Running DXP ........................................................................................ 18

7 Related Documentation From Texas Instruments ..................................................................... 19

List of Figures

1 Block Diagram............................................................................................................... 4

2 Top Silkscreen............................................................................................................... 5

3 Layer 1, Top Signal Plane ................................................................................................. 6

4 Layer 2, Ground Plane ..................................................................................................... 6

5 Layer 3, Power Plane ...................................................................................................... 7

6 Layer 4, Bottom Signal Plane ............................................................................................. 7

7 Bottom Silkscreen........................................................................................................... 7

8 INL and DNL Characteristic Plot.......................................................................................... 8

9 DAC9881 EVM Default Jumper Configuration......................................................................... 10

10 MMB0 with DAC9881EVM Installed .................................................................................... 17

11 Loading the DAC9881EVM INI File..................................................................................... 18

12 DAC9881 – Frequency/Amplitude and GPIO Control Options ...................................................... 19

List of Tables

1 Parts Lists.................................................................................................................... 9

2 Factory Default Jumper Setting.......................................................................................... 10

3 Digital Control Interface Signal Mapping for J2/P2 Connectors..................................................... 11

SLAU279A–March 2009–Revised November 2009 DAC9881 Evaluation Module

EVM Overview

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4 Bipolar Output Operation Jumper Settings............................................................................. 13

5 Gain of Two Output Jumper Settings................................................................................... 13

6 Capacitive Load Drive Output Jumper Settings ....................................................................... 13

7 Jumper Setting Function.................................................................................................. 14

1 EVM Overview

This section gives a general overview of the DAC9881 evaluation module (EVM), and describes some of

the factors that must be considered in using this module.

1.1 Features

This EVM features the DAC9881 digital-to-analog converter (DAC). The DAC9881EVM is a simple

evaluation module designed for quick and easy evaluation of the functionality and performance of the

18-bit, high-resolution, voltage-output, single-channel, and serial input DAC. This EVM features a

high-speed serial interface of up to 50 MHz to communicate with any host microprocessor or DSP-based

system.

The DAC9881 is designed to work by default for unipolar output range, but it can also be configured for

bipolar output range with the addition of an external amplifier and some resistors. The option for bipolar

mode of operation is included in the EVM with some minor jumper configuration.

A +5-V precision voltage reference is provided on the board via U3 (REF5050) to supply the necessary

external reference voltage to set the DAC9881 output range. The footprint of U3 is compatible with many

SO-8 package type reference devices. The user has the flexibility to select the reference supply to set the

output range of the DAC9881 differently than what is provided on the board. The family of REF50xx

precision reference sources work well with this EVM. In addition, the provision of test points TP1 and TP8,

allow users to use their own external reference supply. Typically, TP1 (VREFL) must be connected to

ground, but it can accept up to ±0.2 V, if necessary. The test point, TP8 (VREFH), is typically set to +5 V,

but can accept a minimum of +1.25 V and up to a maximum of +5.5 V.

The voltage reference configuration implemented on this EVM uses the Kelvin connection feature of the

DAC9881 device. This connection helps minimize the internal errors caused by the changing reference

current and its associated circuit impedances.

1.2 Power Requirements

The following sections describe the power requirements of this EVM.

1.2.1 Supply Voltage

The dc power supply requirement for this DAC9881EVM (AVDD and DVDD) is selectable between +3.3 VA

and +5 VA via W1 jumper header. The +3.3 VA comes from J6-8, and the +5 VA comes from J6-3. These

power supply voltages are referenced to analog ground through J6-5 and J6-6.

The logic voltage, IOVDD, is selectable between +1.8 VD, +3.3 VD and +5 VD via the J3 jumper.

The VCC and VSS that ranges from +15-V to –15-V maximum connect through J6-1 and J6-2 terminals,

respectively. All the analog power supplies are referenced to analog ground through J3-6.

CAUTION

To avoid potential damage to the EVM board, ensure that the proper voltages

are connected to their respective terminals as labeled on the EVM board.

Stresses above the maximum listed voltage ratings may cause permanent

damage to the device.

C5000, C6000 are trademarks of Texas Instruments.

LabVIEW is a trademark of National Instruments Corporation.

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EVM Overview

1.2.2 Reference Voltage

The DAC9881 requires an external reference source to set the DAC’s operating voltage output range.

Applying the desired voltage between the ranges of 1.25 V to AVDD into the VREFH pin sets the positive

range of the DAC9881 output. Also, applying the desired voltage between the range of -0.2 V to +0.2 V

into the VREFL pin sets the negative range of the DAC9881 output, although the VREFL pin must nominally

be set to zero volts. The voltages applied into the VREFH and VREFL pins set the DAC9881’s full output

voltage swing.

For optimum performance, the DAC9881 supports a set Kelvin connection to the external reference via

VREFHF and VREFHS pins, as well as VREFLF and VREFLS pins. This option for reference configuration

minimizes the internal errors caused by the changing reference current and its associated circuit

impedances.

A +5-V precision voltage reference is provided for the external reference source of the DAC through

REF5050, U3. The power supply for the reference device, U3, is selectable between VCC and +5 VA via

W11 to ensure that the correct voltage range of U3 can be set. As mentioned earlier, the family of

REF50xx reference devices may be used and the installed device on the EVM changed to provide the

desired voltage range required.

The reference voltages, VREFH and VREFL are selectable via jumpers W8 and W4. When shorting pins 1

and 2 of both jumpers, the onboard +5-V reference via REF5050 is selected. Shorting pins 2 and 3 of both

jumpers selects the reference voltages that are applied via J4 pins 18 and 20, respectively. These

voltages normally come from the host platform that is used to interface with the DAC9881EVM.

The test points TP1 and TP8 are also provided to allow the user to connect other external reference

sources if the onboard reference circuit is not desired. The external voltage reference must not exceed the

applied power supplies, AVDD and DVDD of the DAC.

CAUTION

When applying an external voltage reference through TP8 or J4-20, ensure that

it does not exceed the applied AVDD. This can permanently damage the

DAC9881, U1.

1.3 EVM Basic Functions

This EVM is designed as a functional evaluation platform to test certain characteristics of the DAC9881

digital-to-analog converter. Functional evaluation of the installed DAC device can be accomplished with

the use of any microprocessor, DSP, or a signal/waveform generator.

The headers J2 (top side) and P2 (bottom side) are pass through connectors provided to allow the control

signals and data required to interface a host processor or waveform generator to the DAC9881 EVM. All

signals are routed through except SDI because of daisy-chain capability. SDI to the DAC9881 enters the

P2 connector (located on the bottom side of the board) at pin 11 and is viewable on TP7. SDO from the

DAC9881 exits the board at J1 pin 11 and is viewable on TP6.

An adapter interface card (5–6K Interface Board) is also available to fit and mate with TI’s C5000™ and

C6000™ DSP Starter Kit (DSK). This alleviates the building of a custom cable. In addition, the Precision

Analog Application group of Texas Instruments has other interface boards that are designed to connect to

and interface with this EVM as well. For more details or information regarding the 5-6K Interface Board,

call Texas Instruments Incorporated or visit the product folder for the tool here: 5-6K Interface Board.

The DAC output can be monitored through pins 2 and 6 of the J4 connector. The DAC output can be

switched through W2 for stacking the EVM for daisy-chaining purposes.

A block diagram of the EVM is shown in Figure 1.

SLAU279A–March 2009–Revised November 2009 DAC9881 Evaluation Module

PCB Design and Performance

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Figure 1. Block Diagram

2 PCB Design and Performance

This section discusses the layout design of the printed-circuit board (PCB), the physical and mechanical

characteristics of the EVM, and a brief description of the EVM test performance procedure. The list of

components used on this evaluation module also is included in this section.

2.1 PCB Layout

The DAC9881EVM is designed to preserve the performance quality of the DAC as specified in the data

sheet. To take full advantage of the EVM's capabilities, use care during the schematic design phase to

properly select the right components and to build the circuit correctly. The circuit must include adequate

bypassing, identifying, and managing the analog and digital signals, and understanding the components

electrical and mechanical attributes.

The main design concern during the layout process is the optimal placement of components and the

proper routing of signals. Place the bypass capacitors as close as possible to the pins and be sure to

route the analog and digital signals away from each other. A solid ground plane is preferred. When

considering a split plane design, analyze the component placement and carefully split the board into its

analog and digital sections starting from the DUT. The ground plane plays an important role in reducing

noise that contributes to the error of the DAC output. To ensure that the return currents are handled

properly, route the appropriate signals only in their respective sections, the analog traces should only lay

directly above or below the analog section and the digital traces in the digital section. Minimize the length

of the traces but use the largest possible trace width allowable in the design. These design practices were

applied to the DAC9881EVM PCB.

The DAC9881EVM board is constructed on a four-layer PCB using a copper-clad FR-4 laminate material.

The PCB has a dimension of 43,18 mm (1.70 inch) × 82,55 mm (3.25 inch), and the board thickness is

1,57 mm (0.062 inch). Figure 2 through Figure 7 show the individual artwork layers.

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PCB Design and Performance

Figure 2. Top Silkscreen

Figure 3. Layer 1, Top Signal Plane

SLAU279A–March 2009–Revised November 2009 DAC9881 Evaluation Module

PCB Design and Performance

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Figure 4. Layer 2, Ground Plane

Figure 5. Layer 3, Power Plane

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EVM Performance

Figure 6. Layer 4, Bottom Signal Plane

Figure 7. Bottom Silkscreen

3 EVM Performance

The DAC9881 is optimized for DC performance; total harmonic distortion (THD) is typically at -80 dB. The

EVM INL and DNL testing is performed using a high-density DAC bench test board, an Agilent 3458A

digital multimeter, and a personal computer (PC) running LabVIEW™ software. The EVM board is tested

for all codes of 262,144 × 8 bits organization and the DAC is allowed to settle for 1 ms before the meter is

read. This process is repeated for all codes to generate the measurements for INL and DNL.

Figure 8 shows the INL and DNL characteristic plots.

SLAU279A–March 2009–Revised November 2009 DAC9881 Evaluation Module

EVM Performance

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Figure 8. INL and DNL Characteristic Plot

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Bill of Materials

4 Bill of Materials

Table 1. Parts Lists

Qty. Designators Description Manufacturer Mfg. Part Number

1 N/A Printed Wiring Board TI 6498232

6 C1–C4, C15, C17 0.1 μF, 0805, Ceramic, X7R, 50V, 10% TDK C2012X7R1H104K

3 C5, C11, C16 10 μF, 1210, Ceramic, X7R, 25V, 20% TDK C3225X7R1E106M

2 C6, C13 2200 pF, 0805, Ceramic, C0G, 50V, 5% TDK C2012C0G1H222J

3 C8, C12, C14 1000 pF, 0805, Ceramic, C0G, 50V, 5% TDK C2012C0G1H102J

4 C9, C10, C18, C19 1 μF, 0805, Ceramic, X7R, 25V, 10% TDK C2012X7R1E105K

0 C20 DNP

2 C21, C22 2.2 μF, 0805, Ceramic, X7R, 16V, 10% TDK C2012X7R1C225K

1 J1 7 × 2 × 2 mm Terminal Strip Samtec TMM-107-01-T-D

2 J2, J4 (top side) 10 Pin, Dual Row, TH Header (20 Pos.) Samtec TSM-110-01-T-DV-P

1 J3 3 × 2 × 2mm Terminal Strip Samtec TMM-103-01-T-D

1 J6 (top side) 5 Pin, Dual Row, TH Header (10 Pos.) Samtec TSM-105-01-T-DV-P

2 P2, P4 (bottom side) 10 Pin, Dual Row, TH Header (20 Pos.) Samtec SSW-110-22-F-D-VS-K

1 P6 (bottom side) 5 Pin, Dual Row, TH Header (10 Pos.) Samtec SSW-105-22-F-D-VS-K

6 R1–R4, R8, R20 0.0 Ω1/10W, 5%, 0603, SMD Yageo RC0603JR-070RL

0 R5, R7, R25, R27, R28 DNP

2 R6, R12 6.04 kΩ, 1/10W, 0.1%, 0603, SMD BCC 2312-201-76042

1 R9 10 kΩ4MM TOP ADJ SMD Bourns 3214W-1-103E

7 R10, R11, R15–R19 10.0 kΩ, 1/10W, 1%, 0603, SMD Yageo RC0603FR-0710KL

1 R13 100 Ω, 1/10W, 0.1%, 0603, SMD BCC 2312-201-71001

1 R14 3.01 kΩ, 1/10W, 0.1%, 0603, SMD BCC 2312-201-73012

2 R21, R24 2.00 kΩ,1/10W, 0.1%, 0603, SMD BCC 2312-201-72002

1 R22 95.3 kΩ, 1/10W, 0.1%, 0603, SMD KOA RN731JTTDK9532B25

2 R23, R26 49.9 Ω, 1/10W, 0.1%, 0603, SMD KOA RN731JTTDK49R9B25

4 R29, R31, R32, R33 10.0 kΩ, 1/10W, 0.1%, 0603, SMD KOA RN731JTTDK1002B25

1 R30 470 kΩ, 1/10W, 1%, 0603, SMD Yageo RC0603FR-07470KL

1 R34 1.00 kΩ, 1/10W, 1%, 0603, SMD Yageo RC0603FR-071KL

8 TP1–TP8 Test Point Turret Mill-Max 2348-2-00-44-00-00-07-0

1 U1 18-Bit, Buffered Voltage Output DAC TI DAC9881SBRGET

1 U2 High Precision Op-Amp TI OPA211AIDR

1 U3 5V Precision Voltage Reference TI REF5050AID

1 U4 High Precision Dual Operational Amplifier TI OPA2277UA

10 W1, W2, W4–W11 3 Pin Mini Header Samtec TMM-103-01-T-T

2 W3, W12 2 Pin Mini Header Components Samtec TMM-102-01-T-T

ADDITIONAL COMPONENTS

9 Shunt for items 33 and 34 2mm Shunt – Black Samtec 2SN-BK-G

1 Shunt for J4 0.100 Shunt – Black (J4 Pins 1 and 2) Samtec SNT-100-BK-T

Notes: 1. P2, P4 and P6 parts are not shown in the schematic diagram. All the P designated parts are installed in the bottom side of the

PC Board opposite the J designated counterpart. Example, J2 is installed on the topside while P2 is installed in the bottom side

opposite of J2.

SLAU279A–March 2009–Revised November 2009 DAC9881 Evaluation Module

EVM Operation

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5 EVM Operation

This section covers in detail the operation of the EVM to provide guidance to the user in evaluating the

onboard DAC and how to interface the EVM to a specific host processor.

For information about the serial interface and other related topics, see the DAC9881 data sheet

(SBAS438).

The EVM board is factory tested and configured to operate in the unipolar output mode.

5.1 Factory Default Setting

The EVM board is set to its default configuration from the factory as described in the Table 2 to operate in

unipolar +5V mode of operation. Figure 9 shows the default jumper configuration as described in table 2.

Table 2. Factory Default Jumper Setting

Reference Jumper Function

Position

W1 1-2 The +5VA is used for AVDD and DVDD to power the analog and digital supplies of the DAC9881.

W2 1-2 Routes VOUT of the DAC9881 to J4-2 for analog output monitoring.

W3 OPEN Disconnects VREFH from the inverting input of U2 to allow other output mode of configuration.

W4 2-3 Connects the VREFL pin of the DAC9881 to ground.

W5 1-2 Negative supply rail of the output operational amplifier, U2, is powered by VSS for bipolar operation.

W6 2-3 FS signal from J2-7 is routed to drive the CS signal of the DAC9881.

W7 OPEN Leave this jumper open because R1 is installed. This is the default mode of the EVM when it leaves the

factory.

W8 1-2 Routes the onboard +5-V voltage reference, VREFH for the DAC.

W9 1-2 Routes VOUT and RFB from J4-2 and J4-4 (if they are shunted) to the noninverting input of U2 operational

amplifier.

W10 OPEN The LDAC signal of the DAC9881 is tied to ground for synchronous update of the DAC9881 output.

W11 1-2 Routes VCC to power the analog supply of the U3 reference device.

W12 OPEN Disconnects the inverting input of U2 from R12 gain resistor to allow other output mode of configuration.

J1 1-2 The LDAC signal of the DAC9881 is tied to ground for synchronous DAC update operation.

J3 5-6 The DAC9881’s IOVDD is powered with +3.3 VD.

Figure 9. DAC9881 EVM Default Jumper Configuration

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