Texas Instruments TPS652353 Manual de usuario

SLVUAZ0–November 2016

Evaluation Module for the TPS65235-1 LNB Voltage Regulator With I2C

Interface for DiSEqC2.x Application

User's Guide

SLVUAZ0–November 2016

Evaluation Module for the TPS65235-1 LNB Voltage

Regulator With I2C Interface for DiSEqC2.x Application

This document presents the information required to operate the TPS65235-1 for DiSEqC2.x application as

well as the support documentation including schematic, layout, hardware setup, software application, key

waveforms, and bill of materials.

Contents

1 Introduction ................................................................................................................... 2

2 Schematic..................................................................................................................... 3

3 Board Layout ................................................................................................................. 4

4 Bench Test Setup Conditions .............................................................................................. 6

4.1 Headers Description and Jumper Placement ................................................................... 6

4.2 Hardware Requirement ............................................................................................ 8

4.3 Hardware Setup..................................................................................................... 8

5 Software Installation......................................................................................................... 9

6 Software Operation.......................................................................................................... 9

6.1 Register Map Page................................................................................................ 10

6.2 Basic Settings...................................................................................................... 11

7 Test Procedure Example.................................................................................................. 12

7.1 Voltage output check ............................................................................................. 12

7.2 Tone Output ....................................................................................................... 12

8 Bill of Materials ............................................................................................................. 14

List of Tables

1 Input and Output Connection............................................................................................... 7

2 Jumpers and Switches...................................................................................................... 7

3 VLNB Output Control Without I2C Interface Connection................................................................ 7

4 I2C Address Selection...................................................................................................... 11

5 Bill of Materials ............................................................................................................. 14

Trademarks

Microsoft, Windows, Internet Explorer are registered trademarks of Microsoft Corporation.

VERISIGN is a registered trademark of VeriSign Incorporated.

All other trademarks are the property of their respective owners.

Introduction

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1 Introduction

The TPS65235-1 device is designed to provide 13-V and 18-V output voltage for satellite receiver, with an

operational range of 4.5 V to 16 V.

TPS65235-1 features I2C controlled output voltage from 11 V to 20 V with 16 options; output current limit

with ±10% accuracy is set by ISET pin connecting different resistors. The maximum output current limit is

up to 1 A.

TPS65235-1 can also run without I2C. In non-I2C mode, the SCL pin and VCTRL pin are used to control

13-V and 18-V output. These two pins can be controlled by GPIO from a processor. A dedicated enable

pin EN, is available to turn the LNB output on and off.

The evaluation module is designed to provide access to the features of the TPS65235-1 for DiSEqC2.x

application. While PWR747 is designed for DiSEqC1.x application, some modifications can be made to

this module to test performance at different input and output voltages, current, and switching frequency.

Contact TI Field Applications Group for advice on these matters.

GND

V3V

100k

VIN

GND

10k

GND

40V

3A D1

2 3

10μH

220uH

15.0

100μF

DNP

0.01μF

0.022μF

C12

1 Fμ

0.1μF

C13

DNP

100k

10k

100k

EXTM

VCTRL

LX 1

VIN

VCC

AGND 4

TCAP

ISET

FAULT 8

ADDR

VCTRL

SDA

11 SCL

EXTM

DOUT

DIN

VLNB 16

VCP 17

BOOST 18

GDR 19

PGND 20

EP 21

TPS65235-1RUKR

0.01μF

C14

1 2

3 4

5 6

TP6

TP8

1 2

3 4

5 6

7 8

9 10

0.022μF

1 Fμ

110k

1 Fμ

TP3

GND

28V

DNP

VCC

SCL

SDA 100k

33.0k

VCC

GND

BOOST

VCC

VCTRL

0.1μF

C10

GND

40V 2A

0.1μF

C11

40V2A

DNP

GND

VOUT

FAULT VCC

VOUT

VCC

GND

EXTM

SCL

SDA

ADDR

DIN

DOUT

VIN

VCC

ISET

TCAP

TP1

VCP

VLNB

GDR J1

ADDR

GND GND

TP5

TP7

22μF

10k

GND

TP2

22μF

TP4

GND

10μF

4.5V to 16V, 6A

11V to 20V, 1A

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Schematic

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Evaluation Module for the TPS65235-1 LNB Voltage Regulator With I2C

Interface for DiSEqC2.x Application

2 Schematic

Figure 1 illustrates the EVM schematic.

Figure 1. TPS65235-1 EVM Schematic for DiSEqC 2.x Application

Board Layout

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In the TPS65235-1 application, the recommended ceramic capacitors rated are at least X7R and X5R, 35-

V rating and 1206 size for achieving lower LNB output ripple. For this EVM, two 22-μF, 35-V capacitors,

C8 and C9, are put at the output of the boost converter. If lower cost is demanded, a 100-μF electrolytic

(low ESR) and a 10-μF and 35-V ceramic capacitor also works well.

3 Board Layout

Figure 2 shows the component placement on the EVM. Figure 3 and Figure 4 illustrate the top and bottom

layers, respectively.

Figure 2. Component Placement (Top Layer)

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Board Layout

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Evaluation Module for the TPS65235-1 LNB Voltage Regulator With I2C

Interface for DiSEqC2.x Application

Figure 3. Board Layout (Top Layer)

Figure 4. Board Layout (Bottom Layer)

VIN

Test Point A J7

EN Control

ADDR Control

VOUT

EXTM Control

SCL/I2C Power

I2C Interface to PC

VCTRL Control

Bench Test Setup Conditions

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4 Bench Test Setup Conditions

4.1 Headers Description and Jumper Placement

Figure 5 shows the header descriptions and jumper placement.

Figure 5. Headers Description and Jumper Placement

Test points:

A: LX for Boost

Notes:

• At non-I2C mode, P1 should be floating, J5 and J3 are used to set the output, refer to Table 3.

• At I2C mode, P1 is connected to the PC through the USB-TO-GPIO box, which makes the SCL signal

to be high. J5 can be used to set the default output when powered on, refer to Table 3.

• P1 and J3 cannot be connected at the same time.

Table 1 lists the I/O connections and Table 2 lists the EVM jumpers and switches.

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Bench Test Setup Conditions

SLVUAZ0–November 2016

Evaluation Module for the TPS65235-1 LNB Voltage Regulator With I2C

Interface for DiSEqC2.x Application

Table 1. Input and Output Connection

# Function Description

J1 VOUT Connector VLNB output

J2 Vin Connector Apply power supply through this connector

Table 2. Jumpers and Switches

# Function Placement Comment

Output voltage control (SCL)

If the IC is not controlled by I2C, VCTRL pin and SCL pin

are combined to control the VLNB output voltage. Refer

to Table 3.

Jumper J3-2 and J3-1 makes SCL to VCC connection

and gives VLNB with output 14.6 V or 19.4 V.

Jumper J3-2 and J3-3 makes SCL to GND connection

and gives VLNB with output 13.4 V or 18.2 V.

I2C Power

If the IC is controlled by I2C, this is used to provide the

I2C power which is connected to the SCL and SDA

through pull-up resistors.

Leaving non jumper connected sets the power to be 3.3

V from the I2C interface adapter.

Shorting the J3-1 and J3-2 by jumper sets the power to

be VCC.

On board VCC is 6.3 V

J4 Tone control (EXTM)

Toggle the EXTM signal (J4-2 to J4-3 and then J4-2 to

J4-1), the internal tone signal is superimposed at the

VLNB output VOUT.

EXTM to GND (J4-2 to J4-3), no internal tone signal is

superimposed at the VOUT.

J5 Output voltage control (VCTRL)

If the IC is not controlled by I2C, VCTRL pin and SCL pin

are combined to control the VLNB output voltage. Refer

to Table 3.

Jumper J5-2 and J5-1 makes VCTRL to VCC connection

and gives VLNB with output 18.2 V or 19.4 V.

Jumper J5-2 and J5-3 makes VCTRL to VCC connection

and gives VLNB with output 13.4 V or 14.6 V.

J6 I2C address set (ADDR)

This pin is the I2C address set pin: tie to VCC sets I2C

address with 0x08H; floating sets I2C address with

0x09H; tie to GND sets I2C address with 0x10H; Resistor

divider R9A and R9B make ADDR pin at the voltage to

set the I2C address with 0x11H. Refer to Table 4.

With 3 V-> VCC- 0.8 V will

set the I2C address 0x11H

J7 VLNB output enable (EN)

Jumper EN to GND disables the VLNB output (short J7-2

to J7-3).

Jumper EN to Vin through a 100-kΩresistor enables the

VLNB output (short J7-2 to J7-1).

Leaving J7 open also enables VLNB output.

Table 3. VLNB Output Control Without I2C Interface

Connection

EN SCL VCRTL VLNB

H H H 19.4 V

H H L 14.6 V

H L H 18.2 V

H L L 13.4 V

L X X 0 V

Host

Computer

USB Cable

USB

Interface

Adapter

Green LED

Indicates

Power

10-Pin

Ribbon

Cable

EVM Board

Bench Test Setup Conditions

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4.2 Hardware Requirement

This EVM requires an external power supply capable of providing 4.5 V to 16 V at 4 A.

The EVM kit includes USB-TO-GPIO interface box which, when installed on a PC and connected to the

EVM, allows the user to communicate with the EVM through a GUI interface. (The EVM and USB-TO-

GPIO interface box must be ordered separately.) The minimum PC requirements are:

• Microsoft®Windows®2000, Windows XP or Windows 7 operating system

• USB port

• Minimum of 30 MB of free hard disk space (100 MB recommended)

• Minimum of 256 MB of RAM

4.3 Hardware Setup

After connecting the power supply to J2, floating J7, connect J3, J4, and J5 to GND, J6 and P1 floating,

turning on the power supply, the EVM will regulate the output voltages to 13.4 V without tone

superimposed.

Perform the following steps to change the output voltage by sending the digital control signal through a PC

running the TPS65235-1 Controller software and USB-TO-GPIO interface box:

• Connect one end of the USB-TO-GPIO box to the PC using the USB cable and the other end to P1 of

the TPS65235-1 using the supplied 10-pin ribbon cable per Figure 6. The connectors on the ribbon

cable are keyed to prevent incorrect installation.

• Floating J3.

• Connect the power supply on J2, and turn on the power supply.

• Run the software as explained in Section 5.

Figure 6. USB Interface Adapter Quick Connection Diagram

Basic Information

About TPS65235-1

Status for USB

Adapter Connection

Main Control Panel

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Software Installation

SLVUAZ0–November 2016

Evaluation Module for the TPS65235-1 LNB Voltage Regulator With I2C

Interface for DiSEqC2.x Application

5 Software Installation

If installing from the TI Web site, visit SLVC651.

NOTE: This installation page is best viewed with Microsoft Internet Explorer®browser (it may not

work correctly with other browsers).

1. Click on the install button; the PC should display a security warning and ask if you want to install this

application. Select Install to proceed.

2. To run the software after installation, either use the desktop icon, which is created by the installer if the

user agrees to creating a desktop icon, or go to Start →All programs →Texas Instruments →

TPS65235-1.

At start-up, the software first checks the firmware version of the USB-to-GPIO adapter box. If an incorrect

firmware version is installed, the software automatically searches the Internet (if connected) for updates. If

a new update is available, the software notifies the user of the update then downloads and installs the

software. Note that after the firmware is updated, the user must disconnect and then reconnect the USB

cable between the adapter and PC, as instructed during the install process. The host PC software also

automatically searches on the Internet (if connected) for updates. If a new update is available, the

software notifies the user of the update and downloads and installs it. During future use of the software,

you are prompted to install a new version if one becomes available on the Web.

NOTE: VERISIGN®Code Signing is used to prevent any malicious code from changing this

application. If at any time in the future the binaries are modified, the code will no longer

attempt to run.

6 Software Operation

This section provides descriptions of the EVM software.

The supplied software is used to communicate with the TPS65235-1EVM. Click on the icon on the host

computer to start the software. The software first displays the home page for the user interface. Two

entrances are available for the expert user or beginner.

Figure 7. Home Page for GUI Interface

Software Operation

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By clicking on the Bbutton, the Basic information about TPS65235-1 page comes up which lists the

features and application information for TPS65235-1. Follow the steps to do the basic check for the EVM.

The GUI will guide the beginner to setup the EVM and GUI.

6.1 Register Map Page

By clicking the Ebutton, the Register Map interface comes out. See Figure 8.

Figure 8. Register Map Page for GUI

Single click on a register name to show FIELD VIEW. This shows the detail setting of each bit.

Double click on the bit to change the bit to 0 or 1.

Single click the ?for the register name to show the detail description page for the register.

For Write Registers option, when the Immediate option is selected, any change is sent to the EVM

immediately; otherwise, Write Registers button for each register must be clicked to send the control signal.

Registers or set the Auto Read option.

The Status for USB Adapter Connection, only shows the status for the adapter, not the EVM board. The

user can select the Write Registers on Register Map page to check whether the board communication is

ok or not.

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