Texas Instruments TPS7A74EVM-068 Manual de usuario

User’s Guide

TPS7A74EVM-068 Evaluation Module

ABSTRACT

Figure 1-1. TPS7A74EVM-068 Evaluation Module

This user's guide describes the operational use of the TPS7A74EVM-068 evaluation module (EVM) as a

reference design for engineering demonstration and evaluation of the TPS7A74 low-dropout linear regulator

(LDO). Included in this user's guide are setup and operating instructions, thermal and layout guidelines, a

printed-circuit board (PCB) layout, a schematic diagram, and a bill of materials (BOM).

Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous with the

TPS7A74EVM-068.

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Table of Contents

1 Introduction.............................................................................................................................................................................3

2 Setup........................................................................................................................................................................................3

2.1 LDO Input/Output Connector Descriptions.........................................................................................................................3

2.2 Optional Load Transient Input/Output Connector Descriptions..........................................................................................4

2.3 TPS7A74 LDO Operation and Component Selection........................................................................................................ 4

2.4 Optional Load Transient Circuit Operation.........................................................................................................................6

3 Board Layout...........................................................................................................................................................................8

4 TPS7A74EVM Schematic..................................................................................................................................................... 10

5 Bill of Materials......................................................................................................................................................................11

List of Figures

Figure 1-1. TPS7A74EVM-068 Evaluation Module..................................................................................................................... 1

Figure 2-1. TPS7A74EVM-068 Turn-On......................................................................................................................................5

Figure 2-2. TPS7A74EVM-068 With Current Probes Attached................................................................................................... 5

Figure 2-3. TPS7A74EVM-068 Load Transient Results: 50-μA to 1.42-A Load Step..................................................................7

Figure 2-4. TPS7A74EVM-068 Load Transient Results: 1.42-A to 50-μA Load Step..................................................................7

Figure 3-1. Top Assembly Layer and Silk Screen........................................................................................................................8

Figure 3-2. Top Layer Routing..................................................................................................................................................... 8

Figure 3-3. Layer 2...................................................................................................................................................................... 8

Figure 3-4. Layer 3...................................................................................................................................................................... 8

Figure 3-5. Layer 4...................................................................................................................................................................... 9

Figure 3-6. Layer 5...................................................................................................................................................................... 9

Figure 3-7. Bottom Layer Routing................................................................................................................................................9

Figure 3-8. Bottom Assembly Layer and Silk Screen.................................................................................................................. 9

Figure 4-1. Schematic................................................................................................................................................................10

Trademarks

LeCroy™ is a trademark of Teledyne LeCroy.

Kapton® is a registered trademark of DuPont.

All trademarks are the property of their respective owners.

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1 Introduction

The Texas Instruments TPS7A74EVM-068 evaluation module (EVM) helps designers evaluate the operation and

performance of the TPS7A74 LDO voltage regulator. As shown in Table 1-1, the TPS7A74EVM-068 contains

one TPS7A74 LDO voltage regulator in the DSD package. An optional load transient circuit is also included to

assist the user with high-speed load transient testing. To simplify current measurements, an input current loop is

included.

Table 1-1. Device Information

EVM ORDERABLE NUMBER VOUT PART NAME PACKAGE

TPS7A74EVM-068 Adjustable TPS7A7401DSDR 8-pin DSD

2 Setup

This section describes the jumpers and connectors on the EVM, and how to properly connect, set up, and use

the TPS7A74EVM-068. Section 2.1 and Section 2.3 describe the test setup and operation for the TPS7A74

LDO. Section 2.2 and Section 2.4 describe the test setup and operation of the optional load transient circuit.

2.1 LDO Input/Output Connector Descriptions

2.1.1 VIN and GND

VIN and GND are the connection terminals for the input supply. The VIN terminal is the positive connection, and

the GND terminal is the negative (that is, ground) connection.

2.1.2 BIAS and GND

BIAS and GND are the connection terminals for the bias supply. The BIAS terminal is the positive connection,

and the GND terminal is the negative (that is, ground) connection.

2.1.3 VOUT and GND

VOUT and GND are the connection terminals for the output load. The VOUT terminal is the positive connection,

and the GND terminal is the negative (that is, ground) connection.

2.1.4 EN

EN is a 3-pin header used to enable or disable the TPS7A74.

The center pin of the 3-pin header is tied to the TPS7A74 EN input. When the 2-pin shunt is placed across the

top two pins of the header, VIN is shorted to EN and the TPS7A74 is enabled. When the 2-pin shunt is placed

across the bottom two pins of the header, GND is shorted to EN and the TPS7A74 is disabled.

When driving the EN terminal with an off-board supply or signal generator, the applied voltage must be kept

between 0 V and 5.5 V.

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2.2 Optional Load Transient Input/Output Connector Descriptions

2.2.1 VDD and GND

VDD and GND are the connection terminals for the input supply of the load transient circuit. The VDD terminal is

the positive connection, and the GND terminal is the negative (that is, ground) connection.

2.2.2 J20

J20 is an optional connection for the user to make measurements or apply loads to the output of the LDO.

2.2.3 J22

J22 is an optional connection to insert a damping circuit across the load transient MOSFET drain to source

voltage.

2.2.4 J23

J23 is an optional connection to insert capacitance or additional load across the drain to source of the load

transient MOSFET.

2.2.5 J25

J25 is the connection for the function generator to drive the gate driver device. J25 is terminated by the 50-Ω

resistor, R24.

2.2.6 J26

J26 is a high-frequency kelvin connection that allows accurate measurements of the load transient MOSFET

drain to source voltage.

2.2.7 J28

J28 is a high-frequency kelvin connection that allows accurate measurements of the load transient MOSFET

gate to source voltage.

2.2.8 TP2

TP2 is the test point used to enable the gate driver device. Tie this pin to GND to enable the gate driver.

2.3 TPS7A74 LDO Operation and Component Selection

The TPS7A74EVM-068 evaluation module contains the TPS7A74 LDO with input, bias, soft-start, and output

capacitors installed, as well as feedback resistors installed. These seven components provide an implementation

example, as illustrated by the white boxes in Figure 2-2. The prepopulated capacitors are sized to ensure the

minimum capacitance requirements are maintained under all normal operating conditions. Optional pads are

available to test the LDO with additional setpoint options, as well as input, bias, and output capacitors beyond

what is already installed on the EVM.

Setpoint resistors are prepopulated on the TPS7A74EVM-068 to provide an output voltage of 1 V, 1.2 V, 1.5 V,

1.8 V, or 3.3 V. Select one of these output voltages by using the provided shunt to short the necessary pin on

header J16. If 0.65 V is desired on VOUT, remove the shunt from J16 and short J6. For other voltage options,

resistor R10 can be populated and R1 modified as necessary. See the Application and Implementation section in

the TPS7A74 data sheet for guidance on selecting R10 and R1 for alternate values of VOUT.

The TPS7A74 LDO can be enabled or disabled by using the J9 3-pin header:

• Place a 2-pin shunt across the header to tie VIN to EN to enable the device

• Place a 2-pin shunt across the header to tie GND to EN to disable the device

Alternatively, by connecting an external function generator to TP1 (EN) and a nearby GND post (J17), the

user can enable or disable the TPS7A74 LDO after VIN is applied. Figure 2-1 illustrates the result of the

TPS7A74EVM-068 during turn-on. The blue trace is the enable voltage, the green trace is the output voltage,

and the red trace is the load current.

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Figure 2-1. TPS7A74EVM-068 Turn-On

If desired, a current probe can be inserted in the EVM as shown in Figure 2-2 to measure the input and output

current. The slots were sized to fit most current probes, such as the LeCroy™ AP015 or CP031 current probes.

Figure 2-2. TPS7A74EVM-068 With Current Probes Attached

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The user has two options for providing a DC load on the output of the TPS7A74. J12 can be used to place a

DC load that flows through the current sense path on the output of the LDO. Alternatively, the J4 (VOUT) and

J18 (GND) banana connectors can be used for external measurements and loading; however, the IOUT loop

does not sense current flowing through these connectors. In cases where very fast transient tests are performed,

ringing may occur on VIN or VOUT as a result of the PCB parasitic inductance. Placing a strip of wire on the

exposed copper in the current path can reduce this ringing. 10 AWG wire can be used as needed. If ringing

persists, install damping networks by adding a series resistor and capacitor in parallel with VIN. Locations where

damping can be installed include C5 and R8, C6 and R9, C10 and R7, and C18 and R23.

WARNING

Current probe sensors can be tied to GND and must not come into contact with energized

conductors. See the user manual of your current probe for details. If your current probe has this

limitation, use a thin strip of electrical or Kapton® tape to isolate the current sense path from the

current probe.

Optional kelvin sense points are provided using the SMA connectors J1 (VIN) and J2 (VOUT).

2.4 Optional Load Transient Circuit Operation

The TPS7A74EVM-068 evaluation module contains an optional high-performance load transient circuit to allow

efficient testing of the TPS7A74 LDO load transient performance. To use the optional load transient circuit, install

the correct components in accordance with the application. Modify the input and output capacitance connected

to the TPS7A74 LDO to match the expected operating conditions. Determine the desired peak current to test,

and modify the parallel resistor combination of R12, R13, R14, R15, and R16 as shown:

IPeak =

VOUT

R12 R13 R14 R15 R16 (1)

The slew rate of the load step can be adjusted by C17, R17, R18, and R20. In this section, only R18 and R20

are adjusted to set the slew rate. For a 0-mA to 1.5-A to 0-mA load step, use Table 2-1 to select a value of R18

and R20 that results in the desired rise or fall time.

Table 2-1. Suggested Ramp Rate Resistor Values

R18 R20 Rise, Fall Time

90.9 kΩ 97.6 kΩ 12 µs

44.2 kΩ 47.5 kΩ 6 µs

28 kΩ 23.2 kΩ 3 µs

14 kΩ 12.1 kΩ 1.5 µs

6.65 kΩ 5.9 kΩ 750 ns

3.24 kΩ 2.49 kΩ 300 ns

1.43 kΩ 1.21 kΩ 150 ns

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After the EVM is modified (if needed), connect a power supply to banana connectors J24 (VDD) and J30 (GND)

with a 5-V DC supply and a 1-A DC current limit. As illustrated in Figure 2-3 and Figure 2-4, the TPS7A74

transient response is very fast and the output voltage recovers in well under 1 ms after the initial load transient.

Use a pulse-duration limit of 1 ms to prevent excessive heating of the pulsed resistors (R12, R13, R14, R15,

and R16). Configure a function generator for the 50-Ω output, in a 0-V DC to 5-V DC square pulse. If necessary,

burst mode can be configured in the function generator for repetitive, low duty cycle, load transient testing.

Use J16 to short R2 to GND and configure VOUT to be 1-V DC. The series combination of R1 and R2 provide

50-μA of DC load current. A 20-kΩ resistor is installed on the EVM at R18, and a 20-kΩ resistor is installed on

the EVM at R20. These resistors provide approximately 0.75-A/μs slew rate from 0 mA to 1.5 A, and 0.5-A/μs

slew rate from 1.5 A to 0 mA. Figure 2-3 and Figure 2-4 provide example test data with R18 = 20 kΩ and R20 =

20 kΩ. The orange trace is the input voltage, the green trace is the output voltage, and the red trace is the output

current. R12, R13, R14, R15, and R16 provide 1.42 A of pulsed load. The resulting test data shows a 50-μA to

1.42-A load step on VOUT of the LDO, with only a 47-μF capacitor on the output of the LDO.

Figure 2-3. TPS7A74EVM-068 Load Transient

Results: 50-μA to 1.42-A Load Step

Figure 2-4. TPS7A74EVM-068 Load Transient

Results: 1.42-A to 50-μA Load Step

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3 Board Layout

Figure 3-1 through Figure 3-8 illustrate the board layout for the TPS7A74EVM-068 PCB.

The TPS7A74EVM-068 dissipates power, which may cause some components to experience an increase in

temperature. The TPS7A74 LDO and pulsed resistors R12, R13, R14, R15, and R16 are most at risk of

raising the junction temperature during normal operation. The LDO may become hot to the touch during normal

operation, see the thermal impedance discussion in the TPS7A74 data sheet.

Figure 3-1. Top Assembly Layer and Silk Screen Figure 3-2. Top Layer Routing

Figure 3-3. Layer 2 Figure 3-4. Layer 3

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Figure 3-5. Layer 4 Figure 3-6. Layer 5

Figure 3-7. Bottom Layer Routing Figure 3-8. Bottom Assembly Layer and Silk

Screen

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4 TPS7A74EVM Schematic

Figure 4-1 shows a schematic for the TPS7A74EVM-068.

GND

1.00k

R19

TP1

GND

J3 J 4

J 18J 17

J10

OUTIN

Vin R e com m e nde d Ma x = 5.5V

Vo ut Max = 3.6V

Iout Max = 1.5A

1nF

100V

C23

VDD

A1 OUTH A2

OUTL B2

IN-

C2 GND B1

IN+

LMG1020YFFR

J25

J 24

VDD

J 30

GND

50V

10uF

C22

50V

10uF

C21

1.00k

R11

J 20

50V

0.1uF

C20

154

R15

154

R16

154

R14

154

R13

GND

OUT

154

R12

100V

1pF

C17

R21

R17

5,6,84,7

1,2,

C S D173 13 Q2

J 28

1nF

100V

C24

R22

J 22 J 23

50V

0.015uF

C19

49.9

R24

GND

J 27

TP2

J1210V

1uF

C16

10V

10uF

C12

10V

10uF

25V

1000pF

10µF

10V

47µF

6.3V

C8 63V

10uF

1 2

3 4

5 6

7 8

J 19

BIAS

FBJ5

J 15

BIAS R e comme nde d Ma x = 5.5V

VDD Re com m e nde d Ma x = 5.4V

10V

10uF

C13

10V

4.7uF

VDD

47µF

6.3V

C14

63V

10uF

C11

47µF

6.3V

C15

47µF

6.3V

7.15k

R10

8.45k

5.49k

13.3k

1.74k

4.02k

1 2

3 4

5 6

7 8

9 10

J 16

25V

10uF

1.00

25V

10uF

1.00

25V

10uF

C18

1.00

R23

25V

10uF

C10

1.00

J 13 J 14

J 29

20k

R20

20k

R18

J 11

J 26

J 21

OUT 5

OUT 6

BIAS

FB 7

3Thermal_Pad 9

GND 8

TPS7A7401DSDR

Figure 4-1. Schematic

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