Texas Instruments ADS62PXXEVM Manual de usuario

ADS62PXXEVM

User's Guide

Literature Number: SLAU237B

May 2008–Revised July 2010

2SLAU237B–May 2008–Revised July 2010

1 Overview ............................................................................................................................ 5

1.1 EVM Block Diagram ..................................................................................................... 5

1.2 ADS62Pxx EVM Quick-Start Procedure .............................................................................. 6

2 Circuit Description .............................................................................................................. 7

2.1 Schematic Diagram ..................................................................................................... 7

2.2 ADC Circuit Function .................................................................................................... 7

3 TI ADC SPI Control Interface ............................................................................................... 15

3.1 Installing the ADC SPI Control Software ............................................................................ 15

3.2 Setting Up the EVM for ADC SPI Control .......................................................................... 16

3.3 Using the TI ADC SPI Interface Software .......................................................................... 17

4 Connecting to FPGA Platforms ........................................................................................... 19

4.1 TSW1200 Capture Board ............................................................................................. 19

4.2 TSW1100 ............................................................................................................... 22

5 ADC Evaluation ................................................................................................................. 23

5.1 Hardware Selection .................................................................................................... 23

5.2 Coherent Input Frequency Selection ................................................................................ 24

6 Revision Changes ............................................................................................................. 24

SLAU237B–May 2008–Revised July 2010 Table of Contents

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List of Figures

1 EVM Block Diagram ........................................................................................................ 5

2 ADS62PXXEVM Power Distribution...................................................................................... 8

3 CDCE72010 EEPROM Configuration Block Diagram................................................................ 14

4 Found New Hardware..................................................................................................... 15

5 Window Logo Testing..................................................................................................... 16

6 Hardware Device Manager............................................................................................... 16

7 SPI Interface Screen...................................................................................................... 17

8 TSW1200 GUI Introduction .............................................................................................. 19

9 Quick-Setup Test Result.................................................................................................. 20

10 ADC Performance With Clock Through Onboard VCXO, CDCE72010 and Crystal Filter....................... 21

11 ADC Performance With Clock Through Onboard VCXO, CDCE72010 Configured for Differential LVPECL

Output....................................................................................................................... 22

List of Tables

1 Jumper List .................................................................................................................. 6

2 EVM Power Supply Jumper Description................................................................................. 9

3 EVM Power Supply Options............................................................................................... 9

4 Analog Input Jumper description........................................................................................ 10

5 EVM Analog Input Options............................................................................................... 11

6 Clock Input Jumper Description ......................................................................................... 12

7 EVM Clock Input Options................................................................................................. 13

8 ADS62PXX Frequently Used Registers ................................................................................ 18

4List of Figures SLAU237B–May 2008–Revised July 2010

CDCE72010

ADS62Pxx DATA

Data_CLK

J19

VCXO Divider 245.76MHz

Crystal Filter +

Optional Amplifier Path

Ext. CLK

Ref. CLK

CLK Input

Transformers Coupled

Input Circuit

User's Guide

SLAU237B–May 2008–Revised July 2010

ADS62PXXEVM

1 Overview

This user’s guide gives a general overview of the evaluation module (EVM) and provides a general

description of the features and functions to be considered while using this module. This manual is

applicable to the ADS62P42/43/44/45/48/49, ADS62P22/23/24/25/28/29 and ADS62C15/17 analog to

digital converters (ADC), which will be collectively referred to as ADS62PXX. This document should be

used in combination with respective ADC data sheet. The ADS62PXX EVM provides a platform for

evaluating the analog-to-digital converter (ADC) under various signal, clock, reference and power supply

conditions.

1.1 EVM Block Diagram

Please refer to Figure 1 below for EVM block diagram and configuration.

Figure 1. EVM Block Diagram

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SLAU237B–May 2008–Revised July 2010 ADS62PXXEVM

Overview

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1.2 ADS62Pxx EVM Quick-Start Procedure

The ADS62PXXEVM provides numerous options for providing clock, input frequency and power to the

ADC under evaluation. The quick start procedure describes how to quickly get initial results using the

default configuration of the EVM as it was shipped. The EVM can be put back to default configuration by

setting all jumpers to the default positions as described in Table 1. The default configuration of the EVM is

for the Input Frequency (IF) and the clock input, each to be a single ended input that is

transformer-coupled to the ADC. The default configuration for the power supply is to provide a single 5V

supply to the red banana jack J10, PWR IN. The default configuration for the EVM is to control the modes

of operation by jumper settings for parallel input control pins rather than serial SPI control of the register

space. The other modes of operation of the EVM are described in the latter sections of this document. If

users modify the default jumper settings, this procedure does not apply.

A quick-setup procedure for the default configuration of the ADS62PXX follows:

1. Verify all the jumper settings against the schematic jumper list in Table 1.

2. Connect the 5V supply between J10 (PWR IN) and J12(GND). If you are using the TSW1200 for

capture, it also can be used to source 5V for the EVM. To use the 5V output power of the TSW1200,

configure JP8 to short 1-2, J22 to short 1-2, and jumper over 5V from the banana jacks on the

TSW1200 to J10 on the ADC EVM. Do not connect a voltage source greater than 5.5V.

3. Switch on power supplies.

4. Using a function generator with 50Ωoutput impedance, generate a 0V offset, 1.5VPP sine-wave clock

into J19. The frequency of the clock must be within the specification for the device speed grade.

5. Use a frequency generator with a 50Ωoutput impedance, generate a 0V offset, –1 dBFS-amplitude

sine-wave signal into J6 (Channel A) or J3 (Channel B).This provides a transformer-coupled differential

input signal to the ADC.

6. Connect the TSW1200 or suitable logic analyzer to J8 to capture the resulting digital data. If a

TSW1200 is being used to capture data, follow the additional alphabetically labeled steps. For more

details, see Connecting to FPGA Platforms, located in this document.

(a) After installing the TSW1200 software and connecting the TSW1200 to the USB port, open the

TSW1200 software.

(b) Depending on the ADC under evaluation, select from the TI ADC Selection pull-down menu.

(d) After selecting a Single Tone FFT test, press the Capture Data button.

Table 1. Jumper List

Jumper Function Default Jumper Setting

Interface Circuit Operational Amplifier THS4509 (Bypassed)

SJP1 AMP_OUT+ 1-2

SJP2 AMP_OUT- 1-2

JP3 THS4509_PD 2-3

SJP5 AMPIN- 1-2

SJP3 AMPIN+ No Shunt

ADC Circuit

JP11 Parallel 1-2

JP9 SDATA 1-2

JP10 SEN 1-2

JP8 SCLK 1-2

JP5 CTRL3 1-2

JP6 CTRL2 1-2

JP7 CTRL1 1-2

MODE (Internal or External reference and Gain

JP12 1-2

selection)

JP13 No Shunt

DFS (Data Format and LVDS/CMOS output

JP14 3-4

interface)

6ADS62PXXEVM SLAU237B–May 2008–Revised July 2010

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Circuit Description

Table 1. Jumper List (continued)

Jumper Function Default Jumper Setting

JP22 SDOUT/SPI-MISO Selection No Shunt

Clock Interface Circuit

J18 VCXO EN No Shunt

SJP4 CLOCKIN 1-2

SJP7 CLOCK OPTION SELECT 1-2

SJP6 CLOCK OPTION SELECT 3-4

SJP8 PLL LOCK 1-2

J15 RST (CDC Reset) No Shunt

J14 CDC_PWRDWN 1-2

JP20 AUX SEL 1-2

JP21 MODE_SEL 1-2

J22 SPI Bus Access for CDCE72010

Power Supply

JP15 ADC VA 1-2

JP18 ADC VD 1-2

JP16 TPS7A4501 INPUT SELECT 1-2

JP19 5V_AUX 1-2

JP17 TPS5420 INPUT SELECT No Shunt

2 Circuit Description

2.1 Schematic Diagram

The schematic and layout for this EVM can be found on the EVM Product Folder Page of TI web as a

design package. Please see the schematic or relevant section of this user's guide before changing any

jumpers.

2.2 ADC Circuit Function

Selection of various modes of operation of the ADS62PXX EVM is most often controlled by jumpers on the

EVM, either by placing shunts on 0.025-inch square jumper posts or by installation of surface mount 0Ω

resistors. In general, the use of 0Ωresistors as jumpers are used in the clock or signal path where signal

integrity is critical, and jumper posts are used for static or low-speed control paths.

2.2.1 ADC Operational Mode

By default, the ADC is configured to operate in parallel-mode operation, since jumper (JP11) asserts a

3.3V state to the ADC reset pin. Consequently, the SW1 reset pushbutton must be pressed only when the

device is configured in serial operation mode. Since the ADC is in parallel operation mode, voltages are

used to set the ADC configuration modes. Users can use the information printed on the EVM silkscreen to

set the operation modes.

SLAU237B–May 2008–Revised July 2010 ADS62PXXEVM

GND

5 to 36 V

Amp VCC+

J10

J13

J11

J12

JP17

open

TPS5420D

Switching Regulator to 5.3V TPS7A4501

LDO Regulator to 5V

JP16

JP19

TPS79633

LDO 3.3V

TPS79601

LDO 1.8V

(option for 3.3V)

5 V Analog

VDD

Digital

VDD

THS4509

TPS79601

LDO 3.3V

TPS79633

LDO 3.3V

To Clock Gen

option, to USB

port

To ADC

To Clock

Generator

Option

To Clock

Generator

Option, USB

Port, CMOS

buffer

To USB

Port

Amp VCC-

PWR IN

J17

Circuit Description

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Figure 2. ADS62PXXEVM Power Distribution

2.2.2 EVM Power Connections

Power is supplied to the EVM through banana jacks. From this input power, several different ways of

delivering power to the ADC and other EVM functions are available. Figure 2 shows a simplified

representation of the power options available for the ADS62PXXEVM. The default option is to provide 5V

to J10 or J17, and from there, the EVM generates 3.3V for the analog supply to the ADC and the

necessary digital supply voltage for the populated ADC. The EVM also generates the proper voltages for

optional features of the EVM such as the Clock Generation circuitry, the USB circuitry, and the CMOS

output buffer.

Some ADC devices that may be evaluated on the ADS62PXXEVM platform do not take 1.8V for the digital

supply, but rather require 3.3V for the digital supply. For this reason, an adjustable voltage regulator was

chosen for the digital supply; the output may be changed to 3.3V by changing the value of a resistor, R269

and capacitor C148. The resistor and capacitor need not to be changed in the field unless the ADC is

being changed, because the EVM ships with the correct digital supply voltage for the ADC that is installed.

For reference, ADS62P42/43/44/45,ADS62P22/23/24/25 and ADS62C15 use 3.3V as digital supply for the

ADC whereas ADS62P48/49,ADS62P28/29 and ADS62C17 use 1.8V as digital supply for the ADC.

Power for the optional THS4509 operational amplifier is supplied by banana jacks J11 and J13. If the

amplifier is being evaluated in AC coupled configuration, 5V is supplied to J11, and J13 is connected to

ground. In DC-coupled configuration, 4V is supplied to J11 and –1V is supplied to J13. Otherwise, these

inputs may be left unconnected.

Although various power options are available on this EVM, care must be taken while applying power on

J10 or J17 as different options have different voltage ranges specified. Table 2 displays the general

jumper setting information; Table 3 displays the various power option settings. Prior to making any jumper

settings, see the schematics located in the design package.

CAUTION

Voltage limits: Exceeding the maximum input voltages can damage EVM

components. Undervoltage can cause improper operation of some or all of the

EVM components.

8ADS62PXXEVM SLAU237B–May 2008–Revised July 2010

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Circuit Description

Table 2. EVM Power Supply Jumper Description

EVM Jumper Description Jumper

Default 5V Supply Input

J10 Power Supply Input 6V to 36V Supply Input for Power Supply Option 2

J17 (same node as Default 5V Supply Input

Power Supply Jack

J10) 6V to 36V Supply Input for Power Supply Option 2

1-2 →Connects U11 Output to Input of U14

JP16 U14 Input Select 2-3 →Connects Supply Voltage at J10 or J17 to Input of U14

1-2 →Connects Supply Voltage at J10 or J17 to 5V_AUX

JP19 5V_AUX 2-3 →Connects TPS7A4501 Output to 5V_AUX

JP17 U11 Enable Shunt →J10 or J17 connected to U11

Table 3. EVM Power Supply Options

EVM Evaluation Goal Jumper Changes Required Voltage on J10 Comments

Option

JP17 →No Shunt

JP16 →1-2

Evaluate ADC performance using Maximum ADC

1 JP19 →1-2 5.0V to 5.5V

a LDO based solution performance

JP15 →1-2

JP18 →1-2

JP17 →1-2

Evaluate ADC performance using Maximum ADC

JP16 →1-2

a cascaded switching power performance and

2 JP19 →2-3 6V to 36V

supply (U11) and LDO (U14) power supply

JP15 →1-2

solution efficiency

JP18 →1-2

JP17 →No Shunt

Evaluate ADC performance using Isolated power supply

JP16 →No Shunt

an isolated ADC AVDD and for current

3 JP19 →No Shunt Do not apply power

DVDD for current consumption consumption

JP15 →AVDD to pin 2

measurements measurements

JP18 →DVDD to pin 2

2.2.2.1 Power Supply Option 1

Option 1 supplies power to the ADC using the LDOs TPS79633DCQ and TPS79601DCQ. The LDOs take

a maximum input of 5.5V. When using this option, take care powering up the EVM, because higher

voltage or reverse polarity can damage it. This is the default power-supply configuration for the

ADS62PXXEVM.

2.2.2.2 Power Supply Option 2

Option 2 supplies the power to the ADC using cascaded topology of the TPS5420D switching power

regulator and the TPS7A4501 Low Drop-Out regulator. The TPS5420 is a step-down converter which

works with the input voltage in the range 6V to 36V. The switching supply increases efficiency for higher

input voltages but does create noise on the voltage supplies. To reduce the noise, an low-noise,

high-PSSR LDO TPS7A4501 is used to clean the power supply. The TPS5420D is designed for 5.3V

output, which acts as a supply for the TPS7A4501. The TPS7A4501 is designed to output 5V. This voltage

rail is input to the LDO TPS79633, which outputs 3.3V, used for the ADC. A separate TPS79633 is

designed to output 3.3V for the CDCE72010 supply rail. This solution adds two features to the EVM: one

is to increase the range of the power supply on jumper J10 from 6V to 36V, allowing the user to choose

any power supply source in the specified range without causing significant power dissipation. The other

feature is that the output-voltage rail has a much lower ripple, allowing better performance of the part even

when the power source is fluctuating.

2.2.2.3 Power Supply Option 3

Option 3 is used to evaluate ADC performance using an isolated AVDD and DVDD power supply for

current-consumption measurements. This option must be used with caution, because reversing the power

SLAU237B–May 2008–Revised July 2010 ADS62PXXEVM

Circuit Description

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supply or connecting to the wrong connector can damage the EVM. One common use of this option is to

measure the separate current consumption of the relative supplies under particular operating conditions.

For this option, the shunts on jumpers JP18 and JP15 are removed and the input power is supplied to the

center post of the jumper. For convenience, a ground post is provided next to the center post for header

connections that contain power and ground on 0.1" centers.

2.2.3 ADC Analog Inputs

The EVM can be configured to use either a transformer-coupled input or a THS4509 amplifier input, both

from a single-ended source. The SMA connector J6 (for Channel A) and J3 (for Channel B) provide the

single-ended analog input to the transformer-coupled input circuit to the ADC. The SMA connector J7 and

J9 are not installed by default, but can be used to bring a differential input to the transformer-coupled input

or to bring a single ended input to the THS4509 input circuit. To use the transformer for one of these

options, the EVM must be configured for one of the options listed in Table 5. See the schematic located in

the design package prior to making any jumper changes.

Table 4. Analog Input Jumper description

EVM Jumper Description Jumper Setting

J6 Analog Input single-ended

J3 Analog Input single-ended

Analog input, can be used with J6 for

J7 Not populated

differential input

Analog input, can be used with J3 for

J9 Not populated

differential input 2-3 →AMPOUT+ is selected as source of input to ADC

SJP1 AMPOUT+, +ve terminal of T4 1-2 →Use analog input from J3 as signal source to ADC

(use with appropriate SJP5 setting)

2-3 →AMPOUT- is selected as source of input to ADC

SJP2 AMPOUT-, -ve terminal of T4 1-2 →Use analog input from J9 as signal source to ADC

(use with appropriate SJP3 setting)

1-2 →J3 supplies the analog signal to ADC

SJP5 INPUT -ve select 2-3 →-ve input to amplifier

1-2 →J9 supplies the analog signal to ADC

SJP3 INPUT +ve select 2-3 →+ve input to amplifier (DEFAULT is no shunt)

1-2 →Pulls up the pin (Normal operation or amplifier is ON)

JP3 Power down for amplifier THS4509 2-3 →Grounds the pin (Low-power mode or amplifier is off)

10 ADS62PXXEVM SLAU237B–May 2008–Revised July 2010

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