Texas Instruments RM46L852 Manual de usuario

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RM46L852

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SPNS185 –SEPTEMBER 2012

RM46L852 16/32-Bit RISC Flash Microcontroller

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1 RM46L852 16/32-Bit RISC Flash Microcontroller

1.1 Features

• High-Performance Microcontroller for Safety • Two High-End Timer Modules (N2HET)

Critical Applications – N2HET1: 32 programmable channels

– Dual CPUs running in lockstep – N2HET2: 18 programmable channels

– ECC on flash and RAM interfaces – 160 Word Instruction RAM with parity

– Built-In Self Test for CPU and on-chip RAMs protection each

– Error Signaling Module with Error Pin – Each includes Hardware Angle Generator

– Voltage and Clock Monitoring – Dedicated Transfer Units (HTU) on N2HETs

• ARM® Cortex™ – R4F 32-bit RISC CPU • Two 10/12-bit Multi-Buffered ADC Modules

– 1.66DMIPS/MHz with 8-stage pipeline – ADC1: 24 channels

– FPU with Single/Double Precision – ADC2: 16 channels

– 12-Region Memory Protection Unit – 16 shared channels

– Open Architecture with 3rd Party Support – 64 result buffers with parity protection each

• Operating Conditions • Multiple Communication Interfaces

– Up to 220MHz System Clock – 10/100 Mbps Ethernet MAC (EMAC)

– Core Supply Voltage (VCC): 1.14V - 1.32V • IEEE 802.3 compliant (3.3V-I/O only)

– I/O Supply Voltage (VCCIO): 3.0V - 3.6V • Supports MII, RMII and MDIO

• Integrated Memory – USB (revision 2.0 full-speed)

– 1.25MB Program Flash with ECC • 2-port USB Specification, revision 2.0-

compatible host controller, based on the

– 192KB RAM with ECC OHCI Specification for USB, release 1.0

– 64KB Flash for emulated EEPROM with ECC • USB device compatible with the USB

• 16- bit External Memory Interface (EMIF) Specification, revision 2.0 and USB

• Common Platform Architecture Specification, revision 1.1

– Consistent memory map across family – Three CAN Controllers (DCAN)

– Real-Time Interrupt Timer (RTI) OS Timer • 64 mailboxes with parity protection each

– 128-channel Vectored Interrupt Module (VIM) • Compliant to CAN protocol version

– 2-channel Cyclic Redundancy Checker (CRC) 2.0A/B

• Direct Memory Access (DMA) Controller – Inter-Integrated Circuit (I2C)

– 16 Channels and 32 Control Packets – Three Multi-buffered Serial Peripheral

– Parity protection for control packet RAM Interfaces (MibSPI)

– DMA Accesses Protected by Dedicated MPU • 128 Words with Parity Protection each

• Frequency-Modulated Phase-Locked-Loop • 8 Transfer groups

(FMPLL) with Built-In Slip Detector – Up to two Standard Serial Peripheral

• Separate Non-Modulating PLL Interfaces (SPI)

• IEEE 1149.1 JTAG, Boundary Scan and ARM – Two UART (SCI) interfaces, one with Local

CoreSight Components Interconnect Network Interface (LIN 2.1)

• Advanced JTAG Security Module (AJSM) Support

• Trace and Calibration Capabilities • Up to 101 general purpose I/O (GIO) capable

pins

– Parameter Overlay Module (POM) – 16 dedicated GIO pins with interrupt

• Enhanced Timing Peripherals for Motor Control generation capability

– 7 Enhanced Pulse Width Modulators (ePWM) • Packages

– 6 Enhanced Capture (eCAP) – 144-pin Quad Flatpack (PGE) [Green]

– 2 Enhanced Quadrature Encoder Pulse – 337-Ball Grid Array (ZWT) [Green]

(eQEP)

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

development. Characteristic data and other specifications are design goals. Texas

Instruments reserves the right to change or discontinue these products without notice.

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1.2 Applications

• Industrial Safety Applications

– Industrial Automation

– Safe PLC’s (Programmable Logic Controllers)

– Power Generation and Distribution

– Turbines and Windmills

– Elevators and Escalators

• Medical Applications

– Ventilators

– Defibrillators

– Infusion and Insulin pumps

– Radiation therapy

– Robotic surgery

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RM46L852

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1.3 Description

The RM46L852 is a high performance microcontroller family for safety systems. The safety architecture

includes Dual CPUs in lockstep, CPU and Memory Built-In Self Test (BIST) logic, ECC on both the Flash

and the data SRAM, parity on peripheral memories, and loop back capability on peripheral IOs.

The RM46L852 integrates the ARM® Cortex™-R4F Floating Point CPU which offers an efficient

1.66DMIPS/MHz, and has configurations which can run up to 220MHz providing up to 365 DMIPS.

The RM46L852 has 1.25MB integrated Flash and 192KB data RAM configurations with single bit error

correction and double bit error detection. The flash memory on this device is a nonvolatile, electrically

erasable and programmable, implemented with a 64-bit-wide data bus interface. The flash operates on a

3.3V supply input (same level as I/O supply) for all read, program and erase operations. When in pipeline

mode, the flash operates with a system clock frequency of up to 220MHz. The SRAM supports single-

cycle read/write accesses in byte, halfword, and word modes throughout the supported frequency range..

The RM46L852 device features peripherals for real-time control-based applications, including two Next

Generation High End Timer (N2HET) timing coprocessors with up to 44 total IO terminals, seven

Enhanced PWM (ePWM) modules with up to 14 outputs, six Enhanced Capture Modules (eCAP), two

Enhanced Quadrature Encoders (eQEP) and two 12-bit Analog-to-Digital converters supporting up to 24

inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer

micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,

capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring

multiple sensor information and drive actuators with complex and accurate time pulses. A High End Timer

Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to or from main

memory. A Memory Protection Unit (MPU) is built into the HET-TU.

The enhanced pulse width modulator (ePWM) module is able to generate complex pulse width waveforms

with minimal CPU overhead or intervention. It is easy to use and supports both high side and low side

PWM and deadband generation. With integrated trip zone protection and synchronization with the on chip

MibADC, the ePWM module is ideal for digital motor control applications.

The enhanced Capture (eCAP) module is essential in systems where the accurately timed capture of

external events is important. The eCAP can also be used to monitor the ePWM outputs or for simple PWM

generation when not needed for capture applications.

The enhanced quadrature encoder pulse (eQEP) module is used for direct interface with a linear or rotary

incremental encoder to get position, direction, and speed information from a rotating machine as used in

high-performance motion and position-control systems.

The device has two 12-bit-resolution MibADCs with 24 total channels and 64 words of parity protected

buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for

sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are

three separate groups. Each group can be converted once when triggered or configured for continuous

conversion mode.

The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three

DCANs, one I2C, one Ethernet, and one USB module.. The SPI provides a convenient method of serial

interaction for high-speed communications between similar shift-register type devices. The LIN supports

the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard

Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial,

multimaster communication protocol that efficiently supports distributed real-time control with robust

communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating

in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial

communication or multiplexed wiring. The Ethernet module supports MII, RMII and MDIO interfaces. The

USB module includes a 2-port USB host controller and a USB device controller

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The I2C module is a multi-master communication module providing an interface between the

microcontroller and an I2C compatible device via the I2C serial bus. The I2C supports both 100 Kbps and

400 Kbps speeds.

A frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply the external

frequency reference to a higher frequency for internal use. The FMPLL provides one of the seven possible

clock source inputs to the global clock module (GCM). The GCM module manages the mapping between

the available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous

external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral

interface clock (VCLK) frequency. This low frequency output can be monitored externally as an indicator of

the device operating frequency.

The Direct Memory Access Controller (DMA) has 16 channels, 32 control packets and parity protection on

its memory. A Memory Protection Unit (MPU) is built into the DMA to protect memory against erroneous

transfers.

The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or

external Error pin/ball is triggered when a fault is detected. The nERROR terminal can be monitored

externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous

memories or other slave devices.

A Parameter Overlay Module (POM) is included to enhance the calibration capabilities of application code.

The POM can re-route Flash accesses to internal memory or to the EMIF, thus avoiding the re-

programming steps necessary for parameter updates in Flash.

With integrated safety features and a wide choice of communication and control peripherals, the

RM46L852 is an ideal solution for high performance real time control applications with safety critical

requirements.

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Main Cross Bar: Arbitration and Prioritization Control

CRC Switched Central Resource Peripheral Central Resource Bridge

Dual Cortex-R4F

CPUs in Lockstep

DCAN1

DCAN2

DCAN3

LIN

SCI

SPI4

64 KB Flash

for EEPROM

Emulation

with ECC

MibSPI1

CAN1_RX

CAN1_TX

CAN2_RX

CAN2_TX

CAN3_RX

CAN3_TX

MIBSPI1_CLK

MIBSPI1_SIMO[1:0]

MIBSPI1_SOMI[1:0]

MIBSPI1_nCS[5:0]

MIBSPI1_nENA

SPI2

SPI2_CLK

SPI2_SIMO

SPI2_SOMI

SPI2_nCS[1:0]

SPI2_nENA

MibSPI3

MIBSPI3_CLK

MIBSPI3_SIMO

MIBSPI3_SOMI

MIBSPI3_nCS[5:0]

MIBSPI3_nENA

SPI4_CLK

SPI4_SIMO

SPI4_SOMI

SPI4_nCS0

SPI4_nENA

MibSPI5

MIBSPI5_SIMO[3:0]

MIBSPI5_SOMI[3:0]

MIBSPI5_nCS[3:0]

MIBSPI5_nENA

LIN_RX

LIN_TX

SCI_RX

SCI_TX

IOMM

PMM

VIM

RTI

DCC1

DCC2

32K

192kB RAM

with ECC

MibADC1 MibADC2 I2C

N2HET1 GIO

I2C_SCL

I2C_SDA

GIOB[7:0]

GIOA[7:0]

AD1EVT

AD1IN[7:0]

AD2EVT

# 2

# 3

# 5

# 1

# 2

# 1

always on

Core/RAM

RAM

Core

Color Legend for

Power Domains

SYS

nPORRST

nRST

ECLK

ESM nERROR

1.25MB

Flash

with

ECC

32K

Switched

Central Resource

Switched Central Resource

N2HET2[18,16]

N2HET2[15:0]

N2HET1[31:0]

N2HET1_PIN_nDIS

N2HET2_PIN_nDIS

VSSAD

VCCAD

ADREFHI

ADREFLO

N2HET2

AD1IN[15:8] \

AD2IN[15:8]

AD1IN[23:16] \

AD2IN[7:0]

EMAC Slaves

MDIO

MII

MDCLK

MDIO

MII_RXD[3:0]

MII_RXER

MII_TXD[3:0]

MII_TXEN

MII_TXCLK

MII_RXCLK

MII_CRS

MII_RXDV

MII_COL

EMIF

EMIF_CLK

EMIF_CKE

EMIF_nCS[4:2]

EMIF_nCS[0]

EMIF_ADDR[12:0]

EMIF_BA[1:0]

EMIF_DATA[15:0]

EMIF_nDQM[1:0]

EMIF_nOE

EMIF_nWE

EMIF_nRAS

EMIF_nCAS

EMIF_nRW

EMIF_nWAIT

eQEP

1,2

eQEPxA

eQEPxB

eQEPxS

eQEPxI

eCAP

1..6 eCAP[6:1]

ePWM

1..7

nTZ[3:1]

SYNCO

SYNCI

ePWMxA

ePWMxB Device

Host

USB1.OverCurrent

USB1.RCV

USB1.VM

USB1.VP

USB1.PortPower

USB1.SPEED

USB1.SUSPEND

USB1.TXDAT

USB1.TXEN

USB1.TXSE0

USB2.OverCurrent

USB2.RCV

USB2.VM

USB2.VP

USB2.PortPower

USB2.SPEED

USB2.SUSPEND

USB2.TXDAT

USB2.TXEN

USB2.TXSE0

USB_FUNC.GZO

USB_FUNC.PUENO

USB_FUNC.PUENON

USB_FUNC.RXDI

USB_FUNC.RXDMI

USB_FUNC.RXDPI

USB_FUNC.SE0O

USB_FUNC.SUSPENDO

USB_FUNC.TXDO

USB_FUNC.VBUSI

USB Slaves

HTU1 HTU2

Switched

Central Resource

DMA POM

Switched

Central Resource

Switched

Central Resource

EMAC OHCI

RM46L852

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SPNS185 –SEPTEMBER 2012

1.4 Functional Block Diagram

NOTE

The block diagram reflects the 337BGA package. Some pins are multiplexed or not available

in the 144QFP. Please see the Terminal functions table for details.

Figure 1-1. Functional Block Diagram

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RM46L852

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Table 1-1. Device Comparison Table

Orderable Part # Part # Flash RAM EMAC USB Package

xRM46L852PGET RM46L852 1.25MB 192kB 10/100 Host + Device 144-Pin QFP

xRM46L852ZWTT RM46L852 1.25MB 192kB 10/100 Host + Device 337-Ball Grid Array

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RM46L852

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SPNS185 –SEPTEMBER 2012

1 RM46L852 16/32-Bit RISC Flash Microcontroller .14.11 Tightly-Coupled RAM Interface Module ............ 84

1.1 Features ............................................. 14.12 Parity Protection for Accesses to peripheral RAMs 84

1.2 Applications .......................................... 24.13 On-Chip SRAM Initialization and Testing ........... 86

1.3 Description ........................................... 34.14 External Memory Interface (EMIF) ................. 88

1.4 Functional Block Diagram ........................... 54.15 Vectored Interrupt Manager ........................ 95

2 Device Package and Terminal Functions .......... 84.16 DMA Controller ..................................... 99

2.1 PGE QFP Package Pinout (144-Pin) ................ 84.17 Real Time Interrupt Module ....................... 102

2.2 ZWT BGA Package Ball-Map (337 Ball Grid Array) .94.18 Error Signaling Module ............................ 104

2.3 Terminal Functions ................................. 10 4.19 Reset / Abort / Error Sources ..................... 108

3 Device Operating Conditions ....................... 46 4.20 Digital Windowed Watchdog ...................... 111

3.1 Absolute Maximum Ratings Over Operating Free- 4.21 Debug Subsystem ................................. 112

Air Temperature Range, ............................ 46 5 Peripheral Information and Electrical

3.2 Device Recommended Operating Conditions ...... 46 Specifications ......................................... 117

3.3 Switching Characteristics over Recommended 5.1 Enhanced Translator PWM Modules (ePWM) .... 117

Operating Conditions for Clock Domains .......... 47 5.2 Enhanced Capture Modules (eCAP) .............. 122

3.4 Wait States Required ............................... 47 5.3 Enhanced Quadrature Encoder (eQEP) .......... 124

3.5 Power Consumption Over Recommended 5.4 Multi-Buffered 12bit Analog-to-Digital Converter .. 126

Operating Conditions ............................... 48 5.5 General-Purpose Input/Output .................... 137

3.6 Input/Output Electrical Characteristics Over 5.6 Enhanced High-End Timer (N2HET) .............. 138

Recommended Operating Conditions .............. 49 5.7 Controller Area Network (DCAN) .................. 142

3.7 Output Buffer Drive Strengths ...................... 50 5.8 Local Interconnect Network Interface (LIN) ....... 143

3.8 Input Timings ....................................... 51 5.9 Serial Communication Interface (SCI) ............ 144

3.9 Output Timings ..................................... 51 5.10 Inter-Integrated Circuit (I2C) ...................... 145

3.10 Low-EMI Output Buffers ............................ 53 5.11 Multi-Buffered / Standard Serial Peripheral Interface

4 System Information and Electrical Specifications ..................................................... 148

............................................................. 54 5.12 Ethernet Media Access Controller ................ 160

4.1 Device Power Domains ............................ 54 5.13 Universal Serial Bus Controller ................... 164

4.2 Voltage Monitor Characteristics .................... 54 6 Device and Documentation Support ............. 165

4.3 Power Sequencing and Power On Reset .......... 56 6.1 Device and Development-Support Tool

4.4 Warm Reset (nRST) ................................ 58 Nomenclature ..................................... 165

4.5 ARM©Cortex-R4F™ CPU Information ............. 59 6.2 Community Resources ............................ 165

4.6 Clocks .............................................. 62 6.3 Device Identification ............................... 166

4.7 Clock Monitoring .................................... 71 7 Mechanical Data ...................................... 167

4.8 Glitch Filters ........................................ 73 7.1 Thermal Data ...................................... 167

4.9 Device Memory Map ................................ 74 7.2 Packaging Information ............................ 167

4.10 Flash Memory ...................................... 81

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1108

GIOA[1]

nTRST 109

144

110

111

112

113

114

115

116

117

118

119

120

121

AD1IN[10] / AD2IN[10]

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

2323

2727

107

106

105

104

103

102

101

100

GIOB[3]

GIOA[0]

MIBSPI3NCS[3]

MIBSPI3NCS[2]

N2HET1[11]

FLTP1

FLTP2

GIOA[2]

VCCIO

VSS

CAN3RX

CAN3TX

GIOA[5]

N2HET1[22]

GIOA[6]

VCC

OSCIN

Kelvin_GND

OSCOUT

VSS

GIOA[7]

N2HET1[01]

N2HET1[03]

N2HET1[0]

VCCIO

VSS

VCC

N2HET1[02]

N2HET1[05]

MIBSPI5NCS[0]

N2HET1[07]

TEST

N2HET1[09]

N2HET1[4]

MIBSPI3NCS[1]

N2HET1[06]

N2HET1[13]

MIBSPI1NCS[2]

N2HET1[15]

VCCIO

VSS

VCC

nPORRST

VSS

VCC

VSS

MIBSPI3SOMI

MIBSPI3SIMO

MIBSPI3CLK

MIBSPI3NENA

MIBSPI3NCS[0]

VSS

VCC

AD1IN[16] / AD2IN[0]

AD1IN[17] / AD2IN[01]

AD1IN[0]

AD1IN[07]

AD1IN[18] / AD2IN[02]

AD1IN[19] / AD2IN[03]

AD1IN[20] / AD2IN[04]

AD1IN[21] / AD2IN[05]

ADREFHI

ADREFLO

VSSAD

VCCAD

AD1IN[09] / AD2IN[09]

AD1IN[01]

AD1IN[02]

AD1IN[03]

AD1IN[11] / AD2IN[11]

AD1IN[04]

AD1IN[12] / AD2IN[12]

AD1IN[05]

AD1IN[13] / AD2IN[13]

AD1IN[06]

AD1IN[22] / AD2IN[06]

AD1IN[14] / AD2IN[14]

AD1IN[08] / AD2IN[08]

AD1IN[23] / AD2IN[07]

AD1IN[15] / AD2IN[15]

AD1EVT

VCC

VSS

CAN1TX

CAN1RX

N2HET1[24]

N2HET1[26]

MIBSPI1SIMO

MIBSPI1SOMI

MIBSPI1CLK

MIBSPI1NENA

MIBSPI5NENA

MIBSPI5SOMI[0]

MIBSPI5SIMO[0]

MIBSPI5CLK

VCC

VSS

VCCIO

N2HET1[08]

N2HET1[28]

TMS

TDI

TDO

TCK

RTCK

VCC

VSS

nRST

nERROR

N2HET1[10]

ECLK

VCCIO

VSS

VCC

N2HET1[12]

N2HET1[14]

GIOB[0]

N2HET1[30]

CAN2TX

CAN2RX

MIBSPI1NCS[1]

LINRX

LINTX

GIOB[1]

VCCP

VSS

VCCIO

VCC

VSS

N2HET1[16]

N2HET1[18]

N2HET1[20]

GIOB[2]

VCC

VSS

MIBSPI1NCS[0]

RM46L852

SPNS185 –SEPTEMBER 2012

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2 Device Package and Terminal Functions

2.1 PGE QFP Package Pinout (144-Pin)

Figure 2-1. PGE QFP Package Pinout (144-Pin)

Note: Pins can have multiplexed functions. Only the default function is depicted in above diagram.

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VSS

TMS

N2HET1

[10]

MIBSPI5

NCS[0]

MIBSPI1

SIMO

MIBSPI1

NENA

MIBSPI5

CLK

MIBSPI5

SIMO[0]

N2HET1

[28]

CAN3RX

AD1EVT

AD1IN[15]

AD2IN[15]

AD1IN[22]

AD2IN[06]

AD1IN

[06]

AD1IN[11]

AD2IN[11]

VSSAD

VSS

TCK

TDO

nTRST

N2HET1

[08]

MIBSPI1

CLK

MIBSPI1

SOMI

MIBSPI5

NENA

MIBSPI5

SOMI[0]

N2HET1

[0]

CAN3TX

AD1IN[08]

AD2IN[08]

AD1IN[14]

AD2IN[14]

AD1IN[13]

AD2IN[13]

AD1IN

[04]

AD1IN

[02]

VSSAD

TDI

nRST

EMIF_

nWE

MIBSPI5

SOMI[1]

MIBSPI5

SIMO[3]

MIBSPI5

SIMO[2]

N2HET1

[31]

EMIF_

nCS[3]

EMIF_

nCS[2]

EMIF_

nCS[4]

EMIF_

nCS[0]

AD1IN

[05]

AD1IN

[03]

AD1IN[10]

AD2IN[10]

AD1IN

[01]

AD1IN[09]

AD2IN[09]

RTCK

EMIF_

BA[1]

MIBSPI5

SIMO[1]

MIBSPI5

SOMI[3]

MIBSPI5

SOMI[2]

AD1IN[23]

AD2IN[07]

AD1IN[12]

AD2IN[12]

AD1IN[19]

AD2IN[03]

ADREFLO

VSSAD

EMIF_

DATA[0]

EMIF_

DATA[1]

EMIF_

DATA[2]

EMIF_

DATA[3]

AD1IN[21]

AD2IN[05]

AD1IN[20]

AD2IN[04]

ADREFHI

VCCAD

N2HET1

[26]

nERROR

VCCIO

VCC

VCCIO

AD1IN[18]

AD2IN[02]

AD1IN

[07]

AD1IN

[0]

N2HET1

[17]

N2HET1

[19]

EMIF_BA[0]

VCCIO

AD1IN[17]

AD2IN[01]

AD1IN[16]

AD2IN[0]

ECLK

N2HET1

[04]

EMIF_nOE

VCCIO

VSS

VCC

VSS

VCCIO

MIBSPI5

NCS[3]

N2HET1

[14]

N2HET1

[30]

EMIF_

nDQM[1]

VCCIO

VSS

VCCPLL

CAN1TX

CAN1RX

EMIF_

ADDR[12]

EMIF_

nDQM[0]

VCC

VSS

VCC

MIBSPI3

NCS[0]

GIOB[3]

N2HET1

[27]

EMIF_

ADDR[11]

EMIF_

ADDR[5]

VCC

VSS

VCCIO

EXTCLKI

MIBSPI3

CLK

MIBSPI3

NENA

EMIF_

ADDR[10]

EMIF_

ADDR[4]

VCCP

VSS

VCC

VSS

VCCIO

EMIF_

DATA[15]

MIBSPI3

SOMI

MIBSPI3

SIMO

LINRX

LINTX

EMIF_

ADDR[9]

EMIF_

ADDR[3]

VCCIO

EMIF_

DATA[14]

N2HET1

[09]

nPORRST

GIOA[4]

MIBSPI5

NCS[1]

EMIF_

ADDR[8]

EMIF_

ADDR[2]

VCCIO

VCC

VCCIO

EMIF_

DATA[13]

N2HET1

[05]

MIBSPI5

NCS[2]

GIOA[0]

GIOA[5]

EMIF_

ADDR[7]

EMIF_

ADDR[1]

EMIF_

DATA[4]

EMIF_

DATA[5]

EMIF_

DATA[6]

FLTP2

FLTP1

EMIF_

DATA[7]

EMIF_

DATA[8]

EMIF_

DATA[9]

EMIF_

DATA[10]

EMIF_

DATA[11]

EMIF_

DATA[12]

MIBSPI3

NCS[1]

N2HET1

[02]

N2HET1

[16]

N2HET1

[12]

EMIF_

ADDR[6]

EMIF_

ADDR[0]

N2HET1

[21]

N2HET1

[23]

EMIF_

nCAS

N2HET1

[29]

N2HET1

[22]

MIBSPI3

NCS[3]

SPI2

NENA

N2HET1

[11]

MIBSPI1

NCS[1]

MIBSPI1

NCS[2]

GIOA[6]

MIBSPI1

NCS[3]

EMIF_

CLK

EMIF_

CKE

N2HET1

[25]

SPI2

NCS[0]

EMIF_

nWAIT

EMIF_

nRAS

N2HET1

[06]

VSS

MIBSPI3

NCS[2]

GIOA[1]

SPI2

SOMI

SPI2 CLK

GIOB[2]

GIOB[5]

CAN2TX

GIOB[6]

GIOB[1]

KELVIN_

GND

GIOB[0]

N2HET1

[13]

N2HET1

[20]

MIBSPI1

NCS[0]

TEST

N2HET1

[01]

VSS

GIOA[2]

SPI2

SIMO

GIOA[3]

GIOB[7]

GIOB[4]

CAN2RX

N2HET1

[18]

OSCIN

OSCOUT

GIOA[7]

N2HET1

[15]

N2HET1

[24]

N2HET1

[07]

N2HET1

[03]

VSS

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

2.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)

Figure 2-2. ZWT Package Pinout. Top View

Note: Balls can have multiplexed functions. Only the default function is depicted in above diagram.

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PRODUCT PREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

www.ti.com

2.3 Terminal Functions

Section 2.3.1 and Section 2.3.2 identify the external signal names, the associated pin/ball numbers along

with the mechanical package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether

the pin/ball has any internal pullup/pulldown, whether the pin/ball can be configured as a GIO, and a

functional pin/ball description. The first signal name listed is the primary function for that terminal. The

signal name in Bold is the function being described. Refer to the I/O Multiplexing Module (IOMM) User

Guide for information on how to select between different multiplexed functions.

NOTE

All I/O signals except nRST are configured as inputs while nPORRST is low and immediately

after nPORRST goes High.

All output-only signals are configured as inputs while nPORRST is low, and are configured

as outputs immediately after nPORRST goes High.

While nPORRST is low, the input buffers are disabled, and the output buffers are tri-stated.

2.3.1 PGE Package

2.3.1.1 Multi-Buffered Analog-to-Digital Converters (MibADC)

Table 2-1. PGE Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2)

Terminal Signal Default Pull Type Description

Type Pull State

Signal Name 144

PGE

ADREFHI(1) 66 Power - - ADC high reference

supply

ADREFLO(1) 67 Power ADC low reference supply

VCCAD(1) 69 Power Operating supply for ADC

VSSAD(1) 68 Ground

AD1EVT/MII_RX_ER/RMII_RX_ER 86 Input Pull Down Programmable, ADC1 event trigger input,

20uA or GIO

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ 55 I/O Pull Up Programmable, ADC2 event trigger input,

EQEP1I/N2HET2_PIN_nDIS 20uA or GIO

AD1IN[0] 60 Input - - ADC1 analog input

AD1IN[01] 71

AD1IN[02] 73

AD1IN[03] 74

AD1IN[04] 76

AD1IN[05] 78

AD1IN[06] 80

AD1IN[07] 61

(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.

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