Texas Instruments ADC1173 Manual de usuario

SNAU224–March 2018

ADC117x Evaluation Module

User's Guide

SNAU224–March 2018

ADC117x Evaluation Module

This user's guide describes the function and use of the ADC117x evaluation module (EVM). Included in

this document are a quick-start guide, jumper and connector descriptions, software description, and

alternate hardware configurations.

Contents

1 Overview ..................................................................................................................... 2

2 Quick-Start Guide ........................................................................................................... 4

3 Evaluation Optimization .................................................................................................... 9

4 Alternate Hardware Configurations ....................................................................................... 9

5 Jumper Settings ........................................................................................................... 10

6 References ................................................................................................................. 10

List of Figures

1 EVM Feature Identification ................................................................................................ 3

2 EVM Jumper Identification.................................................................................................. 3

3 Typical Test Setup Using ADC117xEVM and TSW1400EVM......................................................... 4

4 ADC1173 Data Capture Using the HSDC Pro GUI ..................................................................... 6

5 ADC1175 Data Capture Using the HSDC Pro GUI ..................................................................... 7

6 ADC1175-50 Data Capture Using the HSDC Pro GUI ................................................................. 8

List of Tables

1 Quick-Start Measurements for ADC1173................................................................................. 6

2 Quick-Start Measurements for ADC1175................................................................................. 7

3 Quick-Start Measurements for ADC1175-50............................................................................. 8

4 HSDC Pro Settings for Optimizing Results............................................................................... 9

5 EVM Jumper Settings...................................................................................................... 10

Trademarks

Microsoft, Windows are registered trademarks of Microsoft Corporation.

All other trademarks are the property of their respective owners.

Overview

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ADC117x Evaluation Module

1 Overview

The ADC117xEVM is designed to evaluate the ADC1173, ADC1175, and ADC1175-50. The EVM

provides simple and minimal external components to reduce system cost and power consumption.

The following features apply to this EVM:

• 8-bit, low-cost, low-power, high-speed CMOS interface ADC117x data converter

• Onboard oscillator or external source for sampling clock

• User-programmable, low-dropout (LDO) voltage regulator

• Level-shifting data buffer for ADC CMOS output

The ADC117xEVM is designed to work seamlessly with the TSW1400EVM, TI's CMOS and LVDS pattern

generator and data-capture board.

1.1 Required Hardware

The following equipment is included in the EVM kit:

• ADC117xEVM

• Standard banana jack power supply cables

The following list of equipment are items that are not included in the EVM kit, but are items required for

optimal evaluation of this product:

•TSW1400EVM Data Capture Board, 5-VDC cable connector, and mini-USB cable

• Personal computer running Microsoft®Windows®XP or later.

• One low-noise signal generator. Recommendations:

– RF generator, > +17 dBm, < –40 dBc harmonics, < 500 fsec jitter 20 kHz–20 MHz, 1-MHz to 2-GHz

frequency range

– Examples: HP HP8644B, Rohde & Schwarz SMA100A

• DC power supply. Recommendations:

– Power supply, 0–6 VDC, > 3 A

– Examples: Agilent E363A or equivalent

• Band-pass filter for desired analog input. Recommendations:

– Filter, ≥60-dB harmonic attenuation, ≤5% bandwidth, > +18-dBm power, < 5-dB insertion loss

– Examples: Trilithic 5VH-series Tunable BPF, K&L BT-series Tunable BPF, TTE KC6 or KC7-series

Fixed BPF

• Signal path cables, SMA or BNC with BNC-to-SMA adapters

1.2 Required Software

The following software is required to operate the TSW1400EVM and is available online. See Section 6 for

links.

•High-Speed Data Converter Pro (HSDC Pro)

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Overview

SNAU224–March 2018

ADC117x Evaluation Module

1.3 EVM Features and Jumpers

Figure 1 shows the EVM features and Figure 2 shows the EVM jumper locations.

Figure 1. EVM Feature Identification

Figure 2. EVM Jumper Identification

Quick-Start Guide

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ADC117x Evaluation Module

2 Quick-Start Guide

This section details the EVM test procedure to obtain a valid data capture from the ADC117xEVM using

the TSW1400EVM capture card and HSDC Pro. This should be the starting point for all evaluations.

2.1 Software Installation

HSDC Pro must be installed before beginning the evaluation. See Section 1.2 for a list of the required

software. Section 6 contains links to find the software on the TI website.

1. Download HSDC Pro from the TI website. The References section of this document contains the link to

find the software on the TI website.

2. Extract the files from the zip file.

3. Run setup.exe and follow the installation prompts.

2.2 Hardware Setup Procedure

Figure 3 shows a typical test setup using the ADC117xEVM and the TSW1400EVM. This is the test setup

used for the quick-start procedure. The rest of the section describes the hardware setup steps for each

variant of the ADC117xEVM.

Figure 3. Typical Test Setup Using ADC117xEVM and TSW1400EVM

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Quick-Start Guide

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ADC117x Evaluation Module

2.2.1 TSW1400EVM Setup

Set up the TSW1400EVM using the following steps:

1. Connect the ADC117xEVM to the TSW1400EVM connecting pin 1 of the CMOS_INTERFACE (J1) to

pin 1 of ADC117xEVM output data (J1).

2. Connect the power cable to connector J12 (5 V IN) to the TSW1400EVM.

3. Connect the mini-USB cable to the USB connector (J5).

4. Turn on the power supply. Flip the power switch (SW7) to the ON position.

This setup procedure is performed for each variant of the ADC117xEVM.

2.2.2 ADC1173EVM Setup

Set up the ADC1173EVM using the following steps:

1. Connect the banana jack power-supply cables to the EVM. Connect the red wire to +5 VDC of a power

supply, rated for at least 3 A, and to J4.Connect the black wire to J5 and to GND of the power supply.

2. Turn on the power supply.

3. Ensure JP2 is shunted to the 1-2 position to provide a 15-MHz clock signal to the ADC and CMOS

interface. To use an external clock source, provide an external 15-MHz, 1-dBm, clock signal to J3.

Shunt jumper JP2 to the 2-3 position.

4. Set the analog input signal generator to 4.44 MHz, +7 dBm.

5. Place a 4-MHz band-pass filter at the output of the analog input signal generator to reduce noise and

harmonics.

6. Connect the output of the band-pass filter to the analog input at J6.

2.2.2.1 ADC1173EVM Evaluation

Use the following steps for ADC1173EVM evaluation:

1. Launch HSDC Pro by going to Start Menu →All Programs →Texas Instruments →High Speed Data

Converter Pro.

2. A prompt appears showing the TSW1400EVM as a connection. Click OK.

3. A dialog box informs you that there is no firmware loaded, click on the Select ADC box and choose

ADC1173_cmos. Select Yes when prompted to update the firmware.

4. Once the firmware has been loaded, enter "15M" in the ADC Output Data Rate field, and push enter

on the keyboard.

5. Click the Capture button. The results of the captured data should look like that of Figure 4, and the

performance should be similar to that of Table 1.

NOTE: After performing the capture, ensure that the amplitude of the analog input signal is –1 dBFS

or lower.

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Figure 4. ADC1173 Data Capture Using the HSDC Pro GUI

Table 1. Quick-Start Measurements for ADC1173

Result Measured Value Units

SNR 48 dBFS

SFDR 55 dBFS

2.2.3 ADC1175EVM Setup

See Section 2.2 if the TSW1400EVM is not set up.

Set up the ADC1175EVM using the following steps:

1. Connect the banana jack power-supply cables to the EVM. Connect the red wire to +5 VDC of a power

supply, rated for at least 3 A, and to J4.Connect the black wire to J5 and to GND of the power supply.

2. Turn on the power supply.

3. Ensure JP2 is shunted to the 1-2 position to provide a 20-MHz clock signal to the ADC and CMOS

interface. To use an external clock source, provide an external 20-MHz, 1-dBm, clock signal to J3.

Shunt jumper JP2 to the 2-3 position.

4. Set the analog input signal generator to 4.9 MHz, +10 dBm.

5. Place a 5-MHz band-pass filter at the output of the analog input signal generator to reduce noise and

harmonics.

6. Connect the output of the band-pass filter to the analog input at J6.

2.2.3.1 ADC1175EVM Evaluation

Use the following steps for ADC1175EVM evaluation:

1. Launch HSDC Pro by going to Start Menu →All Programs →Texas Instruments →High Speed Data

Converter Pro.

2. A prompt appears showing the TSW1400EVM as a connection. Click OK.

3. A dialog box informs you that there is no firmware loaded, click on the Select ADC box and choose

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Quick-Start Guide

SNAU224–March 2018

ADC117x Evaluation Module

ADC1175_cmos. Select Yes when prompted to update the firmware.

4. Once the firmware has been loaded, enter "20M" in the ADC Output Data Rate field, and push enter

on the keyboard.

5. Click the Capture button. The results of the captured data should look like that of Figure 5, and the

performance should be similar to that of Table 2.

NOTE: After performing the capture, ensure that the amplitude of the analog input signal is –1 dBFS

or lower.

Figure 5. ADC1175 Data Capture Using the HSDC Pro GUI

Table 2. Quick-Start Measurements for ADC1175

Result Measured Value Units

SNR 46 dBFS

SFDR 53 dBFS

2.2.4 ADC1175-50EVM Setup

See Section 2.2 if the TSW1400EVM is not set up.

Set up the ADC1175-50EVM using the following steps:

1. Connect the banana jack power-supply cables to the EVM. Connect the red wire to +5 VDC of a power

supply, rated for at least 3 A, and to J4.Connect the black wire to J5 and to GND of the power supply.

2. Turn on the power supply.

3. Ensure JP2 is shunted to the 1-2 position to provide a 20-MHz clock signal to the ADC and CMOS

interface. To use an external clock source, provide an external 20-MHz, 1-dBm, clock signal to J3.

Shunt jumper JP2 to the 2-3 position.

4. Set the analog input signal generator to 5 MHz, +10 dBm.

5. Place a 5-MHz band-pass filter at the output of the analog input signal generator to reduce noise and

harmonics.

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6. Connect the output of the band-pass filter to the analog input at J6.

2.2.4.1 ADC1175-50EVM Evaluation

Use the following steps for ADC1175-50EVM evaluation:

1. Launch HSDC Pro by going to Start Menu →All Programs →Texas Instruments →High Speed Data

Converter Pro.

2. A prompt appears showing the TSW1400EVM as a connection. Click OK.

3. A dialog box informs you that there is no firmware loaded, click on the Select ADC box and choose

ADC1175-50_cmos. Select Yes when prompted to update the firmware.

4. Once the firmware has been loaded, enter "50M" in the ADC Output Data Rate field, and push enter

on the keyboard.

5. Click the Capture button. The results of the captured data should look like that of Figure 6, and the

performance should be similar to that of Table 3.

NOTE: After performing the capture, ensure that the amplitude of the analog input signal is –1 dBFS

or lower.

Figure 6. ADC1175-50 Data Capture Using the HSDC Pro GUI

Table 3. Quick-Start Measurements for ADC1175-50

Result Measured Value Units

SNR 44 dBFS

SFDR 51 dBFS

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Evaluation Optimization

SNAU224–March 2018

ADC117x Evaluation Module

3 Evaluation Optimization

3.1 Clocking Optimization

The sampling clock provided to the ADC needs to have very low phase noise to achieve optimal results.

The default EVM configuration uses a crystal oscillator to generate the sampling clock. Another option to

improve the clock noise performance is bypassing the onboard clock in favor of an external clock. The

clock must have very low noise and must use an external narrow pass-band filter to achieve optimal noise

performance.

3.2 Coherent Input Source

ARectangular window function can be applied to the captured data when the sample rate and the input

frequency are set precisely to capture an integer number of cycles of the input frequency (sometimes

called coherent frequency). This may yield better SNR results. The clock and analog inputs must be

frequency locked (such as through 10-MHz references) in order to achieve coherency.

3.3 HSDC Pro Settings

HSDC Pro has some settings that can help improve the performance measurements. These are

highlighted in Table 4.

Table 4. HSDC Pro Settings for Optimizing Results

HSDC Pro Feature Description

Analysis Window (Samples) Selects the number of samples to include in the selected test analysis. Collect

more data to improve frequency resolution of Fast-Fourier Transform (FFT)

analysis. If more than 65,536 samples are required, increase the setting in the

Data Capture Options to match this value.

Data Windowing Function Select the desired windowing function applied to the data for FFT analysis.

Select Blackman when sampling a non-coherent input signal or Rectangle

when sampling a coherent input signal.

Test Options →Notch Frequency Bins Select bins to be removed from the spectrum and back-filled with the average

noise level. May also customize which Harmonics and Spurs are considered

in SNR and THD calculations and select the method for calculating spur

power.

Test Options →Bandwidth Integration Markers Enable markers to narrow the Single-Tone FFT test analysis to a specific

bandwidth.

Data Capture Options →Capture Options Configure the number of contiguous samples per capture (capture depth).

May also enable Continuous Capture and FFT Averaging

4 Alternate Hardware Configurations

This section describes alternate hardware configurations in order to achieve better results or to more

closely mimic the user's system configuration.

4.1 Clocking Options

The default clocking mode uses an onboard oscillator, and clock splitter, to generate the ADC sampling

clock and FPGA clocks.

4.1.1 External Clock

To use an external source to provide the clock signal, shunt JP2 (2-3) and remove the jumper on JP7.

Connect the external clock source to J3.

4.1.2 Clock Splitter Bypass

The clock splitter, U3, receives the clock signal, from the either the onboard oscillator or external source,

and then distributes the clock to the ADC and the FPGA. If desired, the clock splitter signal to the ADC

can be bypassed by shunting JP3 (1-2) and JP5 (1-3).

Alternate Hardware Configurations

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4.2 Voltage Reference Options

The default reference voltage is set by tying both VRT and VRTS (the upper reference voltage limit), and

VRB and VRBS (the lower reference voltage limit), to ground via JP6 (shunt 2-3) and JP9 (shunt 2-3).

This configuration provides ADC reference voltages of 1.56 V to 0.36 V for the ADC1173EVM and 2.6 V to

0.6 V for the ADC1175EVM and ADC1175-50EVM.

NOTE: The analog input op amp (OPA830) has been set to provide a known DC offset (0.96 V for

the ADC1173EVM and 1.6 V for the ADC1175EVM and ADC1175-50EVM). Modifying the

reference voltages will require modifying the DC offset to ensure that the analog input signal

is within the bounds of the references.

4.2.1 External Voltage Reference

An external voltage reference can be used to supply the reference voltage to the ADC. For this option,

jumper VRT (JP9) and VRB (JP6) must be pulled out and left OPEN. If the desired voltage references are

1.5 V and 0.5 V, apply the top voltage reference (1.5 V) at the test point VRTP (TP5) and bottom

reference (0.5 V) at VRBP (TP6). Change jumpers JP9 and JP8 to shunt 1-2.

5 Jumper Settings

Table 5 details the EVM jumper settings.

Table 5. EVM Jumper Settings

Jumper Default

Position Description

JP1 1-2 Enable onboard clock source

JP2 1-2 Select internal clock source

JP3 Not Populated Use clock splitter output for ADC clock

JP4 1-2 Enable clock splitter

JP5 2-3 Use clock splitter output for ADC clock

JP6 2-3 Set VRB for ADC

JP7 1-2 VDD for onboard clock source

JP8 2-3 Enable ADC

JP9 2-3 Set VRT for ADC

JP10 2-3 Enable output data buffer

JP11 2-3 Input data voltage level. Shunt 1-2 for ADC1175-50EVM

6 References

• Texas Instruments, ADC1173 8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter Data Sheet

• Texas Instruments, ADC1175 8-Bit, 20MHz, 60mW A/D Converter

• Texas Instruments, ADC1175-50 8-Bit, 50 MSPS, 125 mW A/D Converter

• Texas Instruments, TSW140x High Speed Data Capture/Pattern Generator User's Guide

• Texas Instruments, High Speed Data Converter Pro GUI Installer

• Texas Instruments, TSW140x High Speed Data Capture/Pattern Generator Card User's Guide

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