ST STM32F205 series Manual del propietario

June 2013 DocID15687 Rev 5 1/29

PM0059

Programming manual

STM32F205/215, STM32F207/217 Flash programming manual

Introduction

This programming manual describes how to program the Flash memory of STM32F205/215

and STM32F207/217 microcontrollers. For convenience, these will be referred to as

STM32F20x and STM32F21x in the rest of this document unless otherwise specified.

The STM32F20x and STM32F21xembedded Flash memory can be programmed using in-

circuit programming or in-application programming.

The in-circuit programming (ICP) method is used to update the entire contents of the

Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application

into the microcontroller. ICP offers quick and efficient design iterations and eliminates

unnecessary package handling or socketing of devices.

In contrast to the ICP method, in-application programming (IAP) can use any

communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I2C, SPI,

etc.) to download programming data into memory. With IAP, the Flash memory can be re-

programmed while the application is running. Nevertheless, part of the application has to

have been previously programmed in the Flash memory using ICP.

The Flash interface implements instruction access and data access based on the AHB

protocol. It implements a prefetch buffer that speeds up CPU code execution. It also

implements the logic necessary to carry out Flash memory operations (program/erase).

Program/erase operations can be performed over the whole product voltage range.

Read/write protections and option bytes are also implemented.

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Contents PM0059

2/29 DocID15687 Rev 5

Contents

1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Read interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4.1 Relation between CPU clock frequency and Flash memory read time . . 8

2.4.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 9

2.5 Erase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.5.1 Unlocking the Flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5.2 Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5.3 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5.4 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6.1 Description of user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6.2 Programming user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.3 Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.4 Write protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.7 One-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.8 Flash interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.8.1 Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . 20

2.8.2 Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.8.3 Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 21

2.8.4 Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.8.5 Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.8.6 Flash option control register (FLASH_OPTCR) . . . . . . . . . . . . . . . . . . . 24

2.8.7 Flash interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DocID15687 Rev 5 3/29

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . . . 8

Table 4. Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Flash interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Option byte organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. Description of the option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. Access versus read protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9. OTP part organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10. Flash register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

List of figures

4/29 DocID15687 Rev 5

List of figures

Figure 1. Flash memory interface connection inside system architecture . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Sequential 32-bit instruction execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 3. RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

DocID15687 Rev 5 5/29

PM0059 Glossary

1 Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:

•The CPU core integrates two debug ports:

– JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the

Joint Test Action Group (JTAG) protocol.

– SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on

the Serial Wire Debug (SWD) protocol.

For both the JTAG and SWD protocols, please refer to the Cortex M3 Technical

Reference Manual

•Word: data/instruction of 32-bit length.

•Half word: data/instruction of 16-bit length.

•Byte: data of 8-bit length.

•Double word: data of 64-bit length.

•IAP (in-application programming): IAP is the ability to reprogram the Flash memory of a

microcontroller while the user program is running.

•ICP (in-circuit programming): ICP is the ability to program the Flash memory of a

microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the

device is mounted on the user application board.

•I-Code: this bus connects the Instruction bus of the CPU core to the Flash instruction

interface. Prefetch is performed on this bus.

•D-Code: this bus connects the D-Code bus (literal load and debug access) of the CPU

to the Flash data interface.

•Option bytes: product configuration bits stored in the Flash memory.

•OBL: option byte loader.

•AHB: advanced high-performance bus.

•CPU: refers to the Cortex-M3 core.

Flash memory interface PM0059

6/29 DocID15687 Rev 5

2 Flash memory interface

2.1 Introduction

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the

1 Mbyte (64 Kbit × 128 bits) Flash memory. It implements the erase and program Flash

memory operations and the read and write protection mechanisms.

The Flash memory interface accelerates code execution with a system of instruction

prefetch and cache lines.

2.2 Main features

•Flash memory read operations

•Flash memory program/erase operations

•Read / write protections

•Prefetch on I-Code

•64 cache lines of 128 bits on I-Code

•8 cache lines of 128 bits on D-Code

Figure 1 shows the Flash memory interface connection inside the system architecture.

Figure 1. Flash memory interface connection inside system architecture

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DocID15687 Rev 5 7/29

PM0059 Flash memory interface

2.3 Flash memory

The Flash memory has the following main features:

•Capacity up to 1 Mbyte

•128 bits wide data read

•Byte, half-word, word and double word write

•Sector and mass erase

•Memory organization

The Flash memory is organized as follows:

– Main memory block containing 4 sectors of 16 Kbytes, 1 sector of 64 Kbytes, and

7 sectors of 128 Kbytes

– System memory used to boot the device in System memory boot mode.

This area is reserved for STMicroelectronics and contains the bootloader which is

used to reprogram the Flash memory through one of the following interfaces:

USART1, USART3, CAN2, USB OTG FS in Device mode (DFU: device firmware

upgrade). The bootloader is programmed by ST when the device is manufactured,

and protected against spurious write/erase operations.

– 512 OTP (one-time programmable) bytes for user data

The OTP area contains 16 additional bytes used to lock the corresponding OTP

data block.

– Option bytes: read and write protections, BOR level, watchdog software/hardware

and reset when the device is in Standby or Stop mode.

•Low power modes (for details refer to the Power control (PWR) section of the reference

manual)

Table 2. Flash module organization

Block Name Block base addresses Size

Main memory

Sector 0 0x0800 0000 - 0x0800 3FFF 16 Kbyte

Sector 1 0x0800 4000 - 0x0800 7FFF 16 Kbyte

Sector 2 0x0800 8000 - 0x0800 BFFF 16 Kbyte

Sector 3 0x0800 C000 - 0x0800 FFFF 16 Kbyte

Sector 4 0x0801 0000 - 0x0801 FFFF 64 Kbyte

Sector 5 0x0802 0000 - 0x0803 FFFF 128 Kbyte

Sector 6 0x0804 0000 - 0x0805 FFFF 128 Kbyte

Sector 11 0x080E 0000 - 0x080F FFFF 128 Kbyte

System memory 0x1FFF 0000 - 0x1FFF 77FF 30 Kbyte

OTP area 0x1FFF 7800 - 0x1FFF 7A0F 528 bytes

Option bytes 0x1FFF C000 - 0x1FFF C00F 16 bytes

Flash memory interface PM0059

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2.4 Read interface

2.4.1 Relation between CPU clock frequency and Flash memory read time

To correctly read data from Flash memory, the number of wait states (LATENCY) must be

correctly programmed in the Flash access control register (FLASH_ACR) according to the

frequency of the CPU clock (HCLK) and the supply voltage of the device. Table 3 shows the

correspondence between wait states and CPU clock frequency.

The prefetch must be disabled when the supply voltage is below 2.1 V.

After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the

FLASH_ACR register.

It is highly recommended to use the following software sequences to tune the number of

wait states needed to access the Flash memory with the CPU frequency.

Increasing the CPU frequency

1. Program the new number of wait states to the LATENCY bits in the FLASH_ACR

2. Check that the new number of wait states is taken into account to access the Flash

memory by reading the FLASH_ACR register

3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register

4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR

5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are

taken into account by reading the clock source status (SWS bits) or/and the AHB

prescaler value (HPRE bits), respectively, in the RCC_CFGR register.

Table 3. Number of wait states according to CPU clock (HCLK) frequency

Wait states (WS)

(LATENCY)

HCLK (MHz)

Voltage range

2.7 V - 3.6 V Voltage range

2.4 V - 2.7 V Voltage range

2.1 V - 2.4 V Voltage range

1.8 V - 2.1 V(1)

0 WS (1 CPU cycle) 0 <HCLK≤30 0 <HCLK ≤24 0 <HCLK ≤18 0 < HCLK ≤16

1 WS (2 CPU cycles) 30 <HCLK ≤60 24 < HCLK≤48 18 <HCLK ≤36 16 <HCLK ≤32

2 WS (3 CPU cycles) 60 <HCLK ≤90 48 < HCLK≤72 36 < HCLK≤54 32 < HCLK≤48

3 WS (4 CPU cycles) 90 <HCLK ≤120 72 < HCLK≤96 54 <HCLK ≤72 48 < HCLK≤64

4 WS (5 CPU cycles) 96 < HCLK≤120 72 < HCLK≤90 64 < HCLK≤80

5 WS (6 CPU cycles) 90 < HCLK≤108 80 < HCLK≤96

6 WS (7 CPU cycles) 108 < HCLK≤120 96 < HCLK≤112

7 WS (8 CPU cycles) 112 < HCLK≤120

1. If IRROFF is set to VDD on STM32F20xx devices, this value can be lowered to 1.65 V when the device operates in a

reduced temperature range.

DocID15687 Rev 5 9/29

PM0059 Flash memory interface

Decreasing the CPU frequency

1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register

2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR

3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are

taken into account by reading the clock source status (SWS bits) or/and the AHB

prescaler value (HPRE bits), respectively, in the RCC_CFGR register

4. Program the new number of wait states to the LATENCY bits in FLASH_ACR

5. Check that the new number of wait states is used to access the Flash memory by

reading the FLASH_ACR register

Note: A change in CPU clock configuration or wait state (WS) configuration may not be effective

straight away. To make sure that the current CPU clock frequency is the one you have

configured, you can check the AHB prescaler factor and clock source status values. To

make sure that the number of WS you have programmed is effective, you can read the

FLASH_ACR register.

2.4.2 Adaptive real-time memory accelerator (ART Accelerator™)

The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32

industry-standard ARM®Cortex™-M3 processors. It balances the inherent performance

advantage of the ARM Cortex-M3 over Flash memory technologies, which normally requires

the processor to wait for the Flash memory at higher operating frequencies.

To release the processor full performance of 150 DMIPS, the accelerator implements an

instruction prefetch queue and branch cache which increases program execution speed

from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved

thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash

memory at a CPU frequency up to 120 MHz.

Instruction prefetch

Each Flash memory read operation provides 128 bits from either four instructions of 32 bits

or 8 instructions of 16 bits according to the program launched. So, in case of sequential

code, at least four CPU cycles are needed to execute the previous read instruction line.

Prefetch on the I-Code bus can be used to read the next sequential instruction line from the

Flash memory while the current instruction line is being requested by the CPU. Prefetch is

enabled by setting the PRFTEN bit in the FLASH_ACR register. This feature is useful if at

least one wait state is needed to access the Flash memory.

Figure 2 shows the execution of sequential 32-bit instructions with and without prefetch

when 3 WSs are needed to access the Flash memory.

Flash memory interface PM0059

10/29 DocID15687 Rev 5

Figure 2. Sequential 32-bit instruction execution

When the code is not sequential (branch), the instruction may not be present in the currently

used instruction line or in the prefetched instruction line. In this case (miss), the penalty in

terms of number of cycles is at least equal to the number of wait states.

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Este manual sirve para los siguientes modelos

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