ST STM32F0 Series Manual del propietario

April 2012 Doc ID 022979 Rev 1 1/91

PM0215

Programming manual

STM32F0xxx Cortex-M0 programming manual

Introduction

This programming manual provides information for application and system-level software

developers. It gives a full description of the STM32 Cortex™-M0 processor programming

model, instruction set and core peripherals.

The STM32 Cortex™-M0 processor is a high performance 32-bit processor designed for the

microcontroller market. It offers significant benefits to developers, including:

■Outstanding processing performance combined with fast interrupt handling

■Enhanced system debug with extensive breakpoint and trace capabilities

■Efficient processor core, system and memories

■Ultra-low power consumption with integrated sleep modes

■Platform security

Table 1. Applicable products

Type Part numbers

Microcontroller STM32F0xxx

www.st.com

Contents PM0215

2/91 Doc ID 022979 Rev 1

Contents

1 About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1 Typographical conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3 About the STM32 Cortex-M0 processor and core peripherals . . . . . . . . . . 9

1.3.1 System level interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3.2 Integrated configurable debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3.3 Cortex-M0 processor features and benefits summary . . . . . . . . . . . . . . 10

1.3.4 Cortex-M0 core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 The STM32 Cortex-M0 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Programmers model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1.1 Processor modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1.2 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1.3 Core registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.4 Exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.5 Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.6 The Cortex microcontroller software interface standard (CMSIS) . . . . . 17

2.2 Memory model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2.1 Memory regions, types and attributes . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2.2 Memory system ordering of memory accesses . . . . . . . . . . . . . . . . . . . 19

2.2.3 Behavior of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.4 Software ordering of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.5 Memory endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3 Exception model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.1 Exception states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.2 Exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.3 Exception handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3.4 Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.3.5 Exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.3.6 Exception entry and return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.4 Fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.5.1 Entering sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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2.5.2 Wakeup from sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.5.3 The external event input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.5.4 Power management programming hints . . . . . . . . . . . . . . . . . . . . . . . . 30

3 The STM32 Cortex-M0 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2 CMSIS intrinsic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3 About the instruction descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.3.1 Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.3.2 Restrictions when using PC or SP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.3.3 Shift operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.3.4 Address alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.3.5 PC-relative expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.3.6 Conditional execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.4 Memory access instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.4.1 ADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.4.2 LDR and STR, immediate offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.4.3 LDR and STR, register offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.4.4 LDR, PC-relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.4.5 LDM and STM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.4.6 PUSH and POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.5 General data processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.5.1 ADD{S}, ADCS, SUB{S}, SBCS, and RSBS . . . . . . . . . . . . . . . . . . . . . 49

3.5.2 ANDS, ORRS, EORS and BICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.5.3 ASRS, LSLS, LSRS and RORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.5.4 CMP and CMN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.5.5 MOV, MOVS and MVNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.5.6 MULS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.5.7 REV, REV16, and REVSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.5.8 SXTB, SXTH, UXTB and UXTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.5.9 TST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.6 Branch and control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.6.1 B, BL, BX, and BLX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.7 Miscellaneous instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.7.1 BKPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.7.2 CPSID CPSIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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3.7.3 DMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.7.4 DSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.7.5 ISB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.7.6 MRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.7.7 MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.7.8 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.7.9 SEV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.7.10 SVC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.7.11 WFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.7.12 WFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4 Core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.1 About the STM32 Cortex-M0 core peripherals . . . . . . . . . . . . . . . . . . . . . 69

4.2 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 70

4.2.1 Accessing the Cortex-M0 NVIC registers using CMSIS . . . . . . . . . . . . 70

4.2.2 Interrupt set-enable register (ISER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.2.3 Interrupt clear-enable register (ICER) . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.2.4 Interrupt set-pending register (ISPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.2.5 Interrupt clear-pending register (ICPR) . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.2.6 Interrupt priority register (IPR0-IPR7) . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.2.7 Level-sensitive and pulse interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.2.8 NVIC design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.2.9 NVIC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.3 System control block (SCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.3.1 CPUID base register (CPUID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.3.2 Interrupt control and state register (ICSR) . . . . . . . . . . . . . . . . . . . . . . . 78

4.3.3 Application interrupt and reset control register (AIRCR) . . . . . . . . . . . . 80

4.3.4 System control register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.3.5 Configuration and control register (CCR) . . . . . . . . . . . . . . . . . . . . . . . 82

4.3.6 System handler priority registers (SHPRx) . . . . . . . . . . . . . . . . . . . . . . 83

4.3.7 SCB usage hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.3.8 SCB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.4 SysTick timer (STK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.4.1 SysTick control and status register (STK_CSR) . . . . . . . . . . . . . . . . . . 86

4.4.2 SysTick reload value register (STK_RVR) . . . . . . . . . . . . . . . . . . . . . . . 87

4.4.3 SysTick current value register (STK_CVR) . . . . . . . . . . . . . . . . . . . . . . 87

4.4.4 SysTick calibration value register (STK_CALIB) . . . . . . . . . . . . . . . . . . 88

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4.4.5 SysTick design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.4.6 SysTick register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

List of tables PM0215

6/91 Doc ID 022979 Rev 1

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Summary of processor mode and stack usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Core register set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. PSR register combinations and attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. APSR bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. IPSR bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. EPSR bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. PRIMASK register bit definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. CONTROL register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 10. Ordering of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11. Memory access behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 12. Properties of the different exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Exception return behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 14. Cortex-M0 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 15. CMSIS intrinsic functions to generate some Cortex-M0 instructions . . . . . . . . . . . . . . . . . 35

Table 16. CMSIS intrinsic functions to access the special registers. . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 17. Condition code suffixes and their relationship with the flags . . . . . . . . . . . . . . . . . . . . . . . 40

Table 18. Memory access instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 19. Data processing instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 20. ADCS, ADD, RSBS, SBCS and SUB operand restrictions. . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 21. Branch and control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 22. Branch ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 23. Miscellaneous instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 24. STM32 core peripheral register regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 25. NVIC register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 26. CMSIS access NVIC functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 27. IPR bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 28. CMSIS functions for NVIC control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 29. NVIC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 30. Summary of the system control block registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 31. System fault handler priority fields and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 32. SCB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 33. System timer registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 34. SysTick register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 35. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

PM0215 List of figures

Doc ID 022979 Rev 1 7/91

List of figures

Figure 1. STM32 Cortex-M0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2. Processor core registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3. APSR, IPSR and EPSR bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 4. PRIMASK register bit assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5. CONTROL register bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. Little-endian example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8. Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 9. Cortex-M0 stack frame layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10. ASR#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 11. LSR#3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12. LSL#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 13. ROR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 14. IPR register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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1 About this document

This document provides the information required for application and system-level software

development. It does not provide information on debug components, features, or operation.

This material is for microcontroller software and hardware engineers, including those who

have no experience of ARM products.

1.1 Typographical conventions

The typographical conventions used in this document are:

1.2 List of abbreviations for registers

The following abbreviations are used in register descriptions:

italic Highlights important notes, introduces special terminology, denotes

internal cross-references, and citations.

< and > Enclose replaceable terms for assembler syntax where they appear in

code or code fragments. For example:

LDRSB<cond> <Rt>, [<Rn>, #<offset>]

bold Highlights interface elements, such as menu names. Denotes signal

names. Also used for terms in descriptive lists, where appropriate.

monospace Denotes text that you can enter at the keyboard, such as commands,

file and program names, and source code.

monospace Denotes a permitted abbreviation for a command or option. You can

enter the underlined text instead of the full command or option name.

monospace italic Denotes arguments to monospace text where the argument is to be

replaced by a specific value.

monospace bold Denotes language keywords when used outside example code.

read/write (rw) Software can read and write to these bits.

read-only (r) Software can only read these bits.

write-only (w) Software can only write to this bit.

Reading the bit returns the reset value.

read/clear (rc_w1) Software can read as well as clear this bit by writing 1.

Writing ‘0’ has no effect on the bit value.

read/clear (rc_w0) Software can read as well as clear this bit by writing 0.

Writing ‘1’ has no effect on the bit value.

toggle (t) Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.

Reserved (Res.) Reserved bit, must be kept at reset value.

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1.3 About the STM32 Cortex-M0 processor and core peripherals

The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed for a

broad range of embedded applications. It offers significant benefits to developers, including:

●a simple architecture that is easy to learn and program

●ultra-low power, energy efficient operation

●excellent code density

●deterministic, high-performance interrupt handling

●upward compatibility with Cortex-M processor family.

The Cortex-M0 processor is built on a highly area and power optimized 32-bit processor

core, with a 3-stage pipeline von Neumann architecture. The processor delivers exceptional

energy efficiency through a small but powerful instruction set and extensively optimized

design, providing high-end processing hardware including a single-cycle multiplier.

The Cortex-M0 processor implements the ARMv6-M architecture, which is based on the 16-

bit Thumb® instruction set and includes Thumb-2 technology. This provides the exceptional

performance expected of a modern 32-bit architecture, with a higher code density than other

8-bit and 16-bit microcontrollers.

Figure 1. STM32 Cortex-M0 implementation

The Cortex-M0 processor closely integrates a configurable nested vectored interrupt

controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:

●includes a non-maskable interrupt (NMI)

●provides zero jitter interrupt option

●provides four interrupt priority levels.

The tight integration of the processor core and NVIC provides fast execution of interrupt

service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through

the hardware stacking of registers, and the ability to abandon and restart load-multiple and

store-multiple operations. Interrupt handlers do not require any assembler wrapper code,

removing any code overhead from the ISRs. Tail-chaining optimization also significantly

reduces the overhead when switching from one ISR to another. To optimize low-power

designs, the NVIC integrates with the sleep modes, including a deep sleep function that

enables the entire device to be rapidly powered down.

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1.3.1 System level interface

The Cortex-M0 processor provides a single system-level interface using AMBA®technology

to provide high speed, low latency memory accesses.

1.3.2 Integrated configurable debug

The Cortex-M0 processor implements a complete hardware debug solution, with extensive

hardware breakpoint and watchpoint options. This provides high system visibility of the

processor, memory and peripherals through a 2-pin Serial Wire Debug (SWD) port that is

ideal for small package devices.

1.3.3 Cortex-M0 processor features and benefits summary

●High code density with 32-bit performance

●Tools and binary upwards compatible with Cortex-M processor family

●Integrated ultra low-power sleep modes

●Efficient code execution permits slower processor clock or increases sleep mode time

●Single-cycle 32-bit hardware multiplier

●Zero jitter interrupt handling

●Extensive debug capabilities

1.3.4 Cortex-M0 core peripherals

The peripherals are:

●Nested vectored interrupt controller: The NVIC is an embedded interrupt controller that

supports low latency interrupt processing.

●System control block: The SCB is the programmers model interface to the processor. It

provides system implementation information and system control, including

configuration, control, and reporting of system exceptions.

●System timer: SysTick is a 24-bit count-down timer. Use this as a Real Time Operating

System (RTOS) tick timer or as a simple counter.

Otros manuales para STM32F0 Series

Tabla de contenidos

Otros manuales de Microcontrolador de ST

ST STM32F401 Discovery Manual de usuario

ST STR9 Manual de usuario

ST STM32F40 Series Manual de usuario

ST STM32 Nucleo-64-P Series Manual de usuario

ST STR71xF Manual de usuario

ST STM32F746IGT6 Manual de usuario

ST STM32G4 Series Manual de usuario

ST STM32Cube Manual de usuario

ST L638E Series Guía del usuario

ST STM32 Nucleo Instrucciones de instalación y funcionamiento

ST STM32 Nucleo Manual de usuario

ST STM32F2 Series Manual de usuario

ST ST10F276E Manual de usuario

ST STM32F105 series Instrucciones de instalación y funcionamiento

ST STM32F4DISCOVERY Manual de usuario

ST STM32H745I-DISCO Manual de usuario

ST STM32F072 Manual de usuario

ST UM0250 Manual de usuario

ST STEVAL-IDB007V1M SPBTLE-1S Manual de usuario

ST STM8S Manual de usuario

ST STM32F7 Series Suplemento

ST STM32L053 Manual de usuario

ST STM32G4 Series Manual de usuario

ST STM32 Series Instrucciones de instalación y funcionamiento

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AMS

AMS AS7261 Demo Kit Manual de usuario

Novatek

Novatek NT6861 Manual de usuario

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Espressif Systems ESP8266 SDK Guía de configuración

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Nuvoton ISD61S00 ChipCorder Guía

STMicrolectronics

STMicrolectronics ST7 Assembler Linker Manual de usuario

Texas Instruments

Texas Instruments Chipcon CC2420DK Manual de usuario

Lantronix

Lantronix Intrinsyc Open-Q 865XR SOM Manual de usuario

NEC

NEC 78GK0S/K 1+ Series Instrucciones de instalación y funcionamiento

Mikroe

Mikroe SEMITECH N-PLC Click Instrucciones de instalación y funcionamiento

Intel

Intel Agilex Manual de usuario

Cypress

Cypress CY4607 HX2VL Manual de usuario

DIGITAL-LOGIC

DIGITAL-LOGIC MICROSPACE Manual de usuario

Texas Instruments

Texas Instruments TMS320F2837 D Series Manual de usuario

CYPRES

CYPRES CY14NVSRAMKIT-001 Manual de usuario

Texas Instruments

Texas Instruments INA-DUAL-2AMP-EVM Manual de usuario

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