Renesas M65881AFP Manual de usuario

Rev.1.00 2003.05.08

page 1of 23

Digital Amplifier Processor of S-Master* Technology

M65881AFP REJ03F0004-0100Z

Rev.1.00

2003.05.08

DESCRIPTION

The M65881AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal

to high precise switching-pulse digital output without analog processing.

The M65881AFP has built-in 24bit sampling rate converter and digital-gain-controller.

The M65881AFP enables to realize high precise ( X`tal oscillation accuracy.) full digital amplifier systems combining with power

driver IC.

FEATURES

•Built-in 24bit Sampling Rate Converter.

Input Signal Sampling Rate from 32KHz to 192KHz (24bit Maximum).

4 kinds of Digital Input Format.

•Built-in L/R Independent Digital Gain Control.

•Built-in Soft Mute Function with Exponential Approximate-Curve.

•Correspondence to Output for Headphone.

SYSTEM BLOCK DIAGRAM)

APPLICATION

DVD Receiver, AV Amplifier

RECOMMENDED OPERATING CONDITIONS

Logic Block:1.8V±10%,PWM Buffer Block :3.3V±10%

MAIN SPECIFICATION

•Master Clock

Primary Clock: 256Fsi/512Fsi Secondary Clock: 1024Fso/512Fso

•Input Signal Format:

MSB First Right Justified(16/20/24bit),MSB First Left Justified(24bit)

LSB First Right Justified(24bit),I2S(24bit)

•Input Signal Sampling Rate from 32kHz to 192kHz.

•Gain Control Function:

+30dB~-∞dB (0.1dB Step until -96dB, -138dB Minimum)

•Third Order ∆Σ (16Fso:6bit/5bit,32Fso:5bit)

* "S-Master" is the digital amplifier technology developed by Sony Corporation. "S-Master" is a trademark of Sony Corporation.

Sampling

Rate

Converter

Clock

Stream

Power

Driver

LRCK

BCK

DATA

256fsi/512fsi MCU I/F

M65881AFP

Level

Control

+30dB

-∞

24bit

32kHz

192kHz

∆Σ

Filter

Stream

Power

Driver

1024fso/512fso

DVD Audio

etc. PWM

Clock Output

for Headphone

OUTLINE : 42P2R

0.8mm pitch 42pin SSOP

Rev.1.00 2003.05.08

page 2of 23

M65881AFP

PIN CONFIGURATION

VddL

VssRVssL

OUTL2

XOVdd

XfsoOUT

XOVss

DVdd

DVss

MCKSEL

SCDT

SCSHIFT

SCLATCH

NSPMUTE

INIT

LRCK

BCK

DATA

BFVdd SFLAG

TEST2

TEST1

HPOUTR2

HPVssR

HPOUTR1

HPVddR

HPOUTL2

HPVssL

HPOUTL1

HPVddL

XVss

XfsoIN

XVdd

VssLR

OUTR2

OUTR1

VddR

1.8V

system

OUTL1

BFVss

XfsiIN FsoCKO

FsoI

3.3V

system

3.3V

system

3.3V

system

PWM output

for Power Stage

PWM output

for Headphone

Rev.1.00 2003.05.08

page 3of 23

M65881AFP

BLOCK DIAGRAM

OUTR1

OUTL1

OUTR2

OUTL2

Sampling

Rate Converter Gain Control

DATA

BCK

LRCK

Clock

Generator

( Primary )

Clock

Generator

( Secondary )

INIT/MUTE

Serial

Control

HPOUTR1

HPOUTL1

HPOUTR2

HPOUTL2

PWM

15 14

11 12 13

21 23 2210 636

∆Σ

S⇒P

Rev.1.00 2003.05.08

page 4of 23

M65881AFP

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

(Ta=25ºC,PWMVdd=3.3V, DVdd=1.8V : Unless otherwise specified.)

ELECTRICAL CHARACTERISTICS

Symbol Condition Min. Typ.Max Unit

BFVdd 3.3V system -0.3 –3.8 V

DVdd 1.8V system -0.3 –2.5 V

Vi -0.3 –Vdd+0.3 V

Pd Ta=75ºC350 mW

Tstg -40 – 125 ºC

Parameter

Supply Voltage PWMVdd V

Power Dissipation

Storage Temperature

Input Voltage Range

-0.3 –3.8

3.3V system (XVdd,XOVdd, PWM Output

for Power Stage & Headphone)

Symbol Condition Min. Typ.Max Unit

BFVdd 3.3V system 3.0 3.3 3.6 V

DVdd 1.8V system 1.6 1.8 2.0 V

Ta -20 –75

XfsoIN 16 52.5 MHz

XfsiIN 8 25 MHz

Operating Temperature

3.6

Operating Frequency

PWMVdd 3.0 3.3

Supply Voltage

3.3V system (XVdd,XOVdd, PWM Output

for Power Stage & Headphone) V

Parameter

Symbol Conditions Min. Typ.MUnit

VIH3 BFVdd=3.0 to 3.6V 0.75Vdd ––V

VIH3 BFVdd=3.0 to 3.6V – – 0.25Vdd V

Ileak – – 10 µA

"H" Level Output XfsoOUT BFVdd=3.0 to 3.6V

Voltage SFLAG IOH3=-4.0mA (SFLAG,FsoCKO)

FsoCKO IOH3=-2.0mA (XfsoOUT,OUTL1,2,OUTR1,2)

OUTL1,2 IOH3=-1.0mA (HPOUTL1,2,HPOUTR1,2)

OUTR1,2

HPOUTL1,2

HPOUTR1,2

"L" Level Output XfsoOUT BFVdd=3.0 to 3.6V

Voltage SFLAG IOL3=4.0mA (SFLAG, FsoCKO)

FsoCKO IOL3=2.0mA (XfsoOUT,OUTL1,2,OUTR1,2)

OUTL1,2 IOL3=1.0mA (HPOUTL1,2,HPOUTR1,2)

OUTR1,2

HPOUTL1,2

HPOUTR1,2 Idd2 1.8V system (DVdd)–3.5 –mA

3.3V system (PWMVdd, BFVdd)

OUTxx, HPOUTxx="OPEN"

"L" Level Input Voltage

Parameter

"H" Level Input Voltage

Input Leek Current

VOH3 Vdd-0.5 – – V

VOL3 – – 0.5 V

–mA

Power Supply Current Idd3 –2.5

–

ºC

Rev.1.00 2003.05.08

page 5of 23

M65881AFP

CHARACTERISTICS EVALUATION CIRCUIT

OUTR2

OUTR1

M65881AFP

OUTL1

OUTL2

HPOUTL1

HPOUTL2

HPOUTR2

HPOUTR1

GND

Power Supply

GND

Reference characteristic

S/N

THD+N 102dB(typ)

0.002%(typ)

Conditions

•Input :1kHz 0dB Full scale sine wave

•FS :Primary clock 44.1kHz, Secondary clock 48kHz

•PWM Output format 1 •AC dithering E •DC dithering : 0.1%

•Gain data setting : (Index) 10000b/ (Mantissa) 10000000b

•THD+N: Filter 20kHz LPF S/N: Filter 22kHz LPF + JIS-A

S/N

THD+N 100dB(typ)

0.006%(typ)

Output for

Power Stage

Output for

Headphone

LRCK

BCK

DATA

Rev.1.00 2003.05.08

page 6of 23

M65881AFP

PIN DESCRIPTION

Pin No. Name I/O

Output

Current

on 3.3V Signal Level

1VddL Power Supply for Lch PWM Power Stage (3.3V) –

2OUTL1 OLch PWM1 Output for Power Stage 3.3V

3VssL GND for Lch PWM Power Stage

4OUTL2 OLch PWM2 Output for Power Stage 3.3V

5XOVdd Power Supply for Secondary Master Clock Buffer ( 3.3V )

6XfsoOUT OBuffered Output of Secondary Master Clock (1024/512fso) 2mA 3.3V

7XOVss GND for Secondary Master Clock Buffer

8DVdd Power Supply for Digital Block (1.8V)

9DVss GND for Digital Block

10 MCKSEL ISecondary Master Clock Selector "L":1024fso, "H":512fso 3.3V

11 SCDT ISerial Control •Data Input 3.3V

12 SCSHIFT ISerial Control •Shift Clock Input 3.3V

13 SCLATCH ISerial Control •Latch Signal Input 3.3V

14 NSPMUTE IPWM Duty 50% Mute ( "L": Active ) 3.3V

15 INIT IInitialize Input ( Power Supply Reset ) ; "L" : Reset, "H" : Release 3.3V

16 LRCK ILRCK Input (PCM Signal ) 3.3V

17 BCK IBCK Input ( PCM Signal ) 3.3V

18 DATA IDATA Input ( PCM Signal ) 3.3V

19 BFVdd Power Supply for Input/Output 3.3V Buffer

20 BFVss GND for Input/Output 3.3V Buffer

21 XfsiIN IPrimary Master Clock Input (256fsi/512fsi ) 3.3V

22 FsoCKO OSecondary Fso Clock Output 4mA 3.3V

23 FsoI ISecondary Fso Clock Input 3.3V

24 SFLAG OAsynchronous Flag ( H: Active ) 4mA 3.3V

25 TEST2 ITest2 must be connected to GND 3.3V

26 TEST1 ITest1 must be connected to GND 3.3V

27 HPOUTR2 ORch PWM2 Output for Headphone 3.3V

28 HPVssR GND for Rch Headphone

29 HPOUTR1 ORch PWM1 Output for Headphone 3.3V

30 HPVddR Power Supply for Rch Headphone ( 3.3V )

31 HPOUTL2 OLch PWM2 Output for Headphone 3.3V

32 HPVssL GND for Lch Headphone

33 HPOUTL1 OLch PWM1 Output for Headphone 3.3V

34 HPVddL Power Supply for Lch Headphone ( 3.3V )

35 XVss GND for Secondary Master Clock Input Buffer

36 XfsoIN ISecondary Master Clock Input (1024fso/512fso) 3.3V

37 XVdd Power Supply for Secondary Master Clock Buffer ( 3.3V )

38 VssLR GND for PWM Power Stage

39 OUTR2 ORch PWM 2 Output for Power Stage 3.3V

40 VssR GND for Rch PWM Power Stage

41 OUTR1 ORch PWM 1 Output for Power Stage 3.3V

42 VddR Power Supply for Rch PWM Power Stage ( 3.3V)

Description –

––

–

––

–

Rev.1.00 2003.05.08

page 7of 23

M65881AFP

EXPLANATION OF OPERATION

DATA,BCK, and LRCK are input pins for Digital Audio Signal of CD, MD, DVD etc..

Input formats are supported by 4 ways, and are set by Serial Control, "System1 Mode, bit3 and bit4".

Input data length are selectable in a case of "MSB First Right Justified"

(Serial Control "System1 Mode,bit5 and bit6").

•Input formats are shown in following figures.

LRCK

BCK

MSB

16 cycle

DATA

(16bit)

MSB

16 cycle

1/fsi, 1/2fsi, 1/4fsi

Left Right

DATA

(24bit)

MSB

24 cycle 24 cycle

MSB

DATA

(20bit)

MSB

20 cycle 20 cycle

LSB

MSB first right justified

(16bit, 20bit, 24bit)

MSB first left justified

(24bit) LRCK

BCK

DATA

(24bit)

Left Right

MSB

24cycle

LSB LSB

1/fsi, 1/2fsi, 1/4fsi

24cycle

LSB first right justified

(24bit)

LSBLSB

LRCK

BCK

DATA

(24bit)

Left Right

24 cycle 24 cycle

MSB MSB

1/fsi, 1/2fsi, 1/4fsi

I2S(24bit)

LRCK

BCK

DATA

(24bit)

MSBMSB

24 cycle 24 cycle

1/fsi, 1/2fsi, 1/4fsi

Left Right

1 BCK

LSB LSB

1 BCK

1. DATA,BCK,LRCK

Rev.1.00 2003.05.08

page 8of 23

M65881AFP

SCDT, SCSHIFT and SCLATCH are input pins for setting M65881AFP's operation.

Input format of SCDT, SCSHIFT and SCLATCH is shown below.

Input Format of SCDT, SCSHIFT and SCLATCH

•Mode Setting

The operating mode are classified in four and assigned by bit1 and bit2. These four functions are shown below.

( bit1 and bit2 )= ( "L" and "L" ) Gain control mode: Gain control.

( bit1 and bit2 ) = ( "L "and "H" ) System1 Mode: Primary block initialization, etc.

( bit1 and bit2 )= ( H and "L" ) System2 Mode : Secondary block initialization, etc.

( bit1 and bit2 ) = ("H" and "H" ) Test mode ( setting prohibition )

Refer to Page13 about these four setting in detail.

3. MCKSEL, XfsoIN,XfsoOUT

XfsoIN pin is secondary master clock input.

The setting of MCKSEL pin selects secondary master clock.

XfsoOUT pin is buffered-output from XfsoIN pin's input clock.

4. XfsiIN XfsiIN pin is primary master clock input.

The frequency of primary master clock must be selected by serial control “System2 mode :bit3 (IMCKSEL)”

The relations between input signal sampling rate and master clock frequency.

Input signal and primary clock are related to synchronization. The primary clock frequency are

512 or 256 times as much as the input signal fsi ( 32k, 44.1k and 48k.)

The primary and secondary clock are related to independence. ( asynchronization )

At 1024fso setting, secondary clock= frequency range from 32.768MHz to 49.152MHz.

At 512fso setting, secondary clock = frequency range from 16.384MHz to 24.576MHz.

*Primary clock

This clock means input side clock system of sampling rate converter.

*Secondary clock

This clock means output side clock system of sampling rate converter.

This clock makes to operate after sampling rate converter block.

(Gain Control Block and PWM Block, etc.)

*“fsi”and “fso”are defined as following stated in this specification.

fsi : Primary sampling frequency

fso : Secondary sampling frequency

Primary clock Secondary clock

512fsi/256fsi[Hz] 1024fso/512fso[Hz]

16.384M/8.192M

22.579M/11.290M

24.576M/12.288M

32.768M/16.384M

| / |

49.152M/24.576M

1fsi : 32k / 2fsi : 64k / 4fsi : 128k

1fsi : 44.1k / 2fsi : 88.2k / 4fsi : 176.4k

1fsi :48k / 2fsi : 96k / 4fsi : 192k

Input sampling rate

MCKSEL XfsoIN

"L" 1024fso

"H" 512fso

bit3 (IMCKSEL) XfsiIN

"H" 512fsi

"L" 256fsi

2. SCDT, SCSHIFT, SCLATCH

bit1

SCDT

SCSHIFT

SCLATCH

1510152024

Rev.1.00 2003.05.08

page 9of 23

M65881AFP

FsoCKO is clock output pin of 1fso frequency. The output is divided-clock of XfsoIN, and frequency

is free-running at power on. FsoCKO pin's clock is utilized for a synchronization in case that

have used plural M65881AFP, take a synchronization between M65881AFP and other external

devices.

Refer to the following Chapter 6. in detail.

6. FsoI, SFLAG

M65881AFP synchronizes in clock input from the external source devices. So it makes synchronized

operation between source devices or another M65881AFP ( in case of Multi channel Operation ).

The primary side operation ( input side of sampling rate converter ) are synchronized in LRCK, and the

secondary side operation ( output side of sampling rate converter ) are synchronized in FsoI.

M65881AFP detects rise edge of these synchronized clock in normal operation, and the M65881AFP

does operation of resynchronization in case that the cycle has changed.

In addition, the M65881AFP re-synchronizes for a synchronized clock, in case that M65881AFP detects

SYNC flag (Serial Control, System2 Mode,bit6) rise edge, too.

While re-synchronizing, SFLAG pin outputs "H" and data is muted inside.

In case of using Multiplex ( for multi channel application) and Single ( for 2ch application ), detail

explanation is shown below.

Multiplex use

Primary side: Synchronize with LRCK. All ICs synchronize with an source device by connecting

common LRCK.

Secondary side: Synchronize with FsoCKO of Master IC. One of M65881AFP becomes a master IC,

and the synchronization between ICs is carried out by FsoCKO of Master IC.

FsoCKO pin outputted from this master IC is entered each Fsol pins of master

and slave ICs.

Multiplex use (6ch)

Single use

Primary side: Synchronize with LRCK. Therefore M65881AFP synchronizes with source devices.

Secondary side: There is no need for external devices and other ICs to synchronize,

therefore FsoCKO is connected to FsoI, In other way,

By setting secondary side asynchronous detection to “disable”with

“ASYNCEN2”flag (Serial Control, System2 mode,bit8),

FsoI can also be considered as fixation.

LRCK (Primary side) FsoCKO(Secondary side)

LRCK

Fsol

Master

Slave

LRCK

Fsol

ASYNCEN2=enable

LRCK (Primary) LRCKFsol

ASYNCEN2=disable

LRCK (Primary) LRCK Fsol

ASYNCEN2=enable

FsoCKO

5. FsoCKO

Rev.1.00 2003.05.08

page 10 of 23

M65881AFP

OUTL1, OUTL2, OUTR1 and OUTR2 are pulse output modulated ∆Σ output to PWM signal.

These pins are connected to external Power Driver ICs.The PWM output can be selected

PWM Output Format 1, 2, 3 and 4 by serial control data(System1 mode, bit22,23 ).

PWM Output Form1 : General Modulation

PWM Output Form2 : Symmetrical Modulation

PWM Output Form3 : Modulation returned with time domain.

( The rise and fall edge of Lch and Rch in a term are reverse.)

PWM Output Form4: Modulation returned with time domain.

( The rise and fall edge of Lch and Rch in a term are same timing.)

In each 4 forms, the rate and bit length of PWM Output can be changed.

Moreover, an output mute function and an output pins reverse function

can be controlled by the pin setting or serial control.

Refer to pin setting of the following page about a phase of the PWM output

for Power Stage and Headphone.

The PWM output control is shown in the following table.

PWM output control

Item Operation Setting Operation

Output Form

Operating Rate

and Data Bit Length

( Common setting for

Power Stage and

Headphone )

Output Muting

Reverse Output

Pins Function

Output Form Selection

1,2,3,4

Select to

16fso/6bit ,16fso/5bit ,32fso/5bit

from operating rate and data bit

length of ∆Σ.

PWM operation are synchronized

by this setting.

Duty 50% Mute

( Selectable common and

independent setting for Lch/Rch.)

Absolute Zero Mute

Reverse on Lch and Rch of

output pins (Common setting for

Power Stage and Headphone)

Set up by the serial control system 1 mode

bit 22,23 (PWM MODE 0 and 1).

(Refer to system 1 mode(Page16) for details)

Set up by the serial control system 2 mode bit16

and bit17.

( Refer to system 2 mode(Page 18) for details.)

< Common setting for Lch /Rch >

Set NSPMUTE pin "L" or set up by serial control "

System 2 mode bit14 (NSPMUTE) "H".

< Independent Setting for Lch /Rch >

Set up by serial control Gain Control Mode bit9,10

(NSPMUTEL,NSPMUTER) "H" .

( Refer to Page 11,18 and 13 for details)

Set up by serial control system2 mode

bit15(PGMUTE) "H".

(See system2 mode(Page 18) )

Set up by serial control system2 mode bit9

(CHSEL).

Set up by serial control system2 mode bit12

(CHRSEL).

( Common setting for Power

Stage and Headphone)

Reverse for R1 and R2 of

output pins.

( Only enable for Power Stage.)

7. OUTL1, OUTL2, OUTR1, OUTR2

( Common setting for

Power Stage and

Headphone )

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