Renesas ForgeFPGA Manual de usuario

User Manual

ForgeFPGA Configuration Guide

Rev.1.0

May 31, 2022

Page 1

This document describes how to configure the ForgeFPGA core from three different configuration bitstream

sources: External SPI/QSPI Flash, Internal OTP, MCU as a host.

Contents

1. Terms and Definitions................................................................................................................................... 1

2. References...................................................................................................................................................... 1

3. Introduction.................................................................................................................................................... 2

4. General SPI Interface..................................................................................................................................... 2

4.1 SPI Modes with Clock Polarity and Clock Phase .................................................................................. 3

5. Development Board....................................................................................................................................... 4

6. OTP Read/Write.............................................................................................................................................. 7

6.1 Writing the OTP Block ........................................................................................................................... 9

6.2 Reading the OTP Block....................................................................................................................... 10

6.3Read Command Structure................................................................................................................... 11

7. QSPI Programming (Master Mode) ............................................................................................................ 11

8. MCU Programming (Slave Mode)............................................................................................................... 13

Conclusion ........................................................................................................................................................... 14

9. Revision History .......................................................................................................................................... 15

1. Terms and Definitions

OTP One Time Programmable on chip NVM

QSPI Quad Serial Programming Interface

MCU Micro Controller Unit

FPGA Field-Programmable Gate Array

CPOL Clock Polarity

CPHA Clock Phase

2. References

[1] SLG47910, Datasheet, Renesas Electronics Corporation

[2] ForgeFPGA Designer Software, Software Download and User Guide, Renesas Electronics Corporation

[3] ForgeFPGA Dev. Board R1.1 User Guide

[4] ForgeFPGA Socket Adapter Quick Start Guide R1.0

ForgeFPGA Configuration Guide

Rev.1.0

May 31, 2022

Page 2

3. Introduction

An internal Configuration Wrapper is used to configure the ForgeFPGA core. The configuration can be done

from three different configuration bitstream sources:

–External SPI/QSPI Flash

–Internal OTP

–MCU as a host

The ForgeFPGA Designer Software is used to generate bitstreams. The schematic in Figure 1 shows a block

diagram of the SLG47910 configuration block and the external MCU Host and QSPI Flash interface. The four

Configuration pins are GPIO3 (SPI_CLK), GPIO4(SPI_SS, Chip Select), GPIO5(SPI_SI, serial input) and

GPIO6(SPI_SO, serial output). GPIO9 is used as a Config Done signal. Table 1 shows which modes activate the

SPI Master and SPI Slave blocks during configuration.

MCU

Host

QSPI

Flash

OTP

SPI

Master

SPI

Slave Config Loader FPGA Core

OTP

Programmer

Configuration Wrapper

conf

SPI

otp_data_rd

otp_ctrl

op_data_wr

ctrl

tx_data

ctrl

tx_data

Figure 1: SLG47910 Programming Interface

Table 1: Configuration Modes

Configuration Mode

SPI Block Activated

Clock Source

QSPI/SPI

Master

FPGA

MCU

Slave

MCU

READ OTP

Slave

External to FPGA

Write OTP

Slave

External to FPGA

4. General SPI Interface

A 4-wire SPI device has four signals (see Figure 2):

1. SCLK: Serial Clock (output from Master). When the master communicates with the slave, the data on MOSI

or MISO pin will be synchronized with the Serial Clock. In the SPI protocol, the master produces the clock. The

slave will only receive the clock, so the slave has no control over the serial clock, which is produced by the

master.

2. MOSI: Master-Out Slave-In (data output from master). MOSI is a data pin. This pin is used to transmit data

from the Master to the Slave device. Whenever the master sends data, that data will be collected over the MOSI

pin by the slave.

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Rev.1.0

May 31, 2022

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3. MISO: Master-In Slave-Out (data output from slave). MISO is a data pin. This pin is used to transmit data

from the slave to the master. Whenever the slave sends data, that data will be collected over the MISO pin by

the master.

4. SS: Slave-Select (often active low, the output from master). Depending on the SPI and slave select setting,

the SS pin used to select an individual slave device for communication. When there is one master and one slave

device, then the SS pin is not required. This slave select pin will make sense only when the master is

communicating with the different slaves. So, the master can select the slave to which the master wants to

convey. For choosing the slave, the SS pin dedicated.

Figure 2: SPI Interface

4.1 SPI Modes with Clock Polarity and Clock Phase

In SPI, the master can select the Clock Polarity (CPOL) and Clock Phase (CPHA). The CPOL bit sets the

polarity of the clock signal during the idle state. The idle state is defined as the period when SS is transitioning.

The CPHA bit selects the clock phase. Depending on the CPHA bit, the rising or falling clock edge is used to

sample and/or shift the data. Depending on the CPOL and CPHA bit selection, four SPI modes are available.

(See Table 2)

Table 2: SPI Modes

SPI

Modes

CPOL

CPHA

Clock

Polarity in

Idle State

Clock Phase Used to Sample and/or Shift the Data

Logic Low

Data sampled on rising edge and shifted out on the falling edge

Logic Low

Data sampled on the falling edge and shifted out on the rising

edge

Logic High

Data sampled on the falling edge and shifted out on the rising

edge

Logic High

Data sampled on the rising edge and shifted out on the falling

edge

Figure 3 shows the data on the MOSI and MISO line. The green dotted lines show, the end and the beginning of

the transmission. Also, the data sampling is shown with orange line which corresponds to the rising or falling

edge depending on SPI Mode. The shifting edge of the data is depicted using the blue doted lines. Figure 3

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May 31, 2022

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depicts the SPI Mode 0 with CPOL = 0 and CPHA = 0 with the clk idle state = 0 and hence the data is sampled

on rising edge and the shifted on falling edge according to Table 2.

Figure 3: SPI Mode 0

5. Development Board

There are two pre-requisite steps that need to be performed before the design is sent to the device and can be

further configured with the development board.

a. RTL Synthesis : After creating your desired Verilog Code in the HDL Editor Window of the ForgeFPGA

Workshop, the next step is to create a Netlist of your design. This can be done with the help of the built-

in Synthesis tool that takes input design and produces a Netlist out of it. While performing synthesis, the

input design is analyzed and converted into gate-level representation.

b. Generating Bitstream: To prepare your design to be sent to the device you need to perform the Place-

and-Route procedure, that takes the elements of the synthesized netlist and maps its primitives to FPGA

physical resources. You can do this after successfully generating netlist and pressing Generate

Bitstream button on the control panel. Completing these two steps would have successfully sent the

design to the device.

To enter the debug controls of the development board, we need to select the correct platform on which we need

to configure our device. Under the "Debug" button on the toolbar, select the ForgeFPGA Development Board as

the platform (see Figure 4)

Figure 4: ForgeFPGA Development Platform Selection

The FPGA Development Board (see Figure 5) is a multi-functional tool that allows the user to develop their

FPGA designs with ease by providing on board power source, digital and analog signal generation, and logic

analysis capabilities. The FPGA Development Board can connect additional external boards called socket

adapters (see Figure 7). The function of the socket adapter board is to implement a stable electrical connection

between the pins of the chip under test and the FPGA Development Board. To implement this, the FPGA

Development Board has a Dual PCIe connector. This connector has 40 differential pairs (80 digital channels), 32

analog pins, service pins, and power pins. Dual PCIe connector is universal and can be applied to multiple

socket adapter boards.

ForgeFPGA Configuration Guide

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Driven by the free software, the FPGA Development Board can be configured to work as any one of several

traditional instruments, which include:

–Logic Analyzer

–Digital pattern generator

–8-channel analog Arbitrary Waveform Generator (AWG)

–Precision ADC

–Three programmable power supplies (+0.6 V…+3.3 V). The maximum available output current 2 A.

The same voltage is supplied to the GPIO, for keeping the logic level compatibility with the circuit

under test.

Also, the board can be used as an independent unit. The chip can be powered through the EXT PWR connector

and signals can be read through the through-hole 12-pin connectors (Pmod connectors).

Figure 5: ForgeFPGA Development Board Overview

To configure the development board and read the desired output, connect the Development Board with the

Socket Adapter through the PCIe connectors. Put the SLG47910 part in the socket. Then connect the USB cable

from the laptop to the USB Type-C Connector (see Figure 8). Connect the power cord that was supplied with the

development board to the power supply connection on the development board. If all the connections are correct,

then the RED LED( PWR) and BLUE LED(STS) should light up and the software would have recognized the

SLG47910 part in the socket.

The user can now either program the chip with the design by clicking on the "Program" button else, the user can

use the "Emulation" button under the Debugging Controls Panel (see Figure 6) to observe the output and

manipulate it by connecting the Development Board to Oscilloscope, or any PMOD if required.

ForgeFPGA Configuration Guide

Rev.1.0

May 31, 2022

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Figure 6: Debugging Controls Panel

Figure 7: ForgeFPGA Socket Adapter, Top View

ForgeFPGA Configuration Guide

Rev.1.0

May 31, 2022

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Figure 8: Assembled Equipment for Working with the Chip

6. OTP Read/Write

The configuration for the FPGA is stored in the Configuration RAM. The Configuration RAM is a volatile memory

that stores the FPGA design. The OTP memory loads the Configuration RAM. The SLG47910 contains three

blocks of 4k x 32-bit One-Time Programmable (OTP) Non-Volatile Memory (NVM), which are interfaced via the

dedicated SPI Slave circuit block (Figure 9).

The user can read or write the OTP block through the SPI interface pins on the SLG47910. If the OTP block of

the SLG47910 has been programmed, upon POR, the contents of the NVM will be loaded into the device’s

internal configuration RAM.

ForgeFPGA Configuration Guide

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Figure 9. SLG47910 Block Diagram

The loading of the data through different bitstream sources follow a particular flow and different values of the

signal help in determining the mode of operation. The Figure 10 below showcases a part of that flow.

ForgeFPGA Configuration Guide

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May 31, 2022

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Figure 10: Power Sequencing through Different Modes

6.1 Writing the OTP Block

The OTP is written using the SPI Slave interface. The OTP write starts with ramp up of the voltage signals

VDDC to 1.1 V and VDDIO to 2.9 V which sets the NVM into write program mode. There is an otp_controller that

sequences the internal signals to enable the OTP write.

Once the overdrive and program mode inputs are active, the otp_controller will decode the spi_slave data, and

give, data address and control information to the otp_write_controller block to initiate the OTP write. Table 3

shows the OTP Write Packet format. Table 4 shows the Write/Read options bits. The last Write packet is

indicated by setting Byte8 bit[6]. Reserve bits are indicated by R and the parity bit by P. After writing the OTP the

write data should be checked using the OTP read command. Once the SLG47910 OTP has been written and

after POR or bringing the PWR pin low, MCU, QSPI, OTP write, and OTP read will be disabled. The SLG47910

will only load program data from the OTP. This is a design security feature.

Writing to the OTP has the following steps:

1. Wait for POR and PLL lock time (1300 us), then send the Signature Bytes through SPI_MOSI (GPIO_5) by

keeping SPI_SS (GPIO_4) low.

2. After the Signature bytes match, GPIO_9 (Config-Sig match) goes high and giving delay of 80 us and then

sending the OTP write command packets with delay gap between 1st and 2nd packet is 18 us delay and

consecutive packets is 10.11us delay. (S13)

3. In the last write packet Byte8[6] =1 which indicates the last write.

4. When done writing OTP bring PWR =L which resets the device, then at S5 chk_otp_en will be one.

ForgeFPGA Configuration Guide

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May 31, 2022

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Table 3: OTP Write Packet Format (Incoming)

Bits

Byte 1

W/Rn (1)

SP/AP (0)

O1_A[15]

O1_A[14]

O1_A[13]

Byte 2

O1_A[12]

O1_A[11]

O1_A[10]

O1_A[8]

O1_A[7]

O1_A[6]

O1_A[5]

O1_A[4]

Byte 3

O1_A[3]

O1_A[2]

O1_A[1]

O1_A[0]

O1_D[3]

O1_D[2]

O1_D[1]

O1_D[0]

Byte 4

O2_A[15]

O2_A[14]

O2_A[13]

O2_A[12]

O2_A[11]

O2_A[10]

O2_A[8]

O2_A[7]

Byte 5

O2_A[6]

O2_A[5]

O2_A[4]

O2_A[3]

O2_A[2]

O2_A[1]

O2_A[0]

O2_D[3]

Byte 6

O2_D[2]

O2_D[1]

O2_D[0]

O3_A[15]

O3_A[14]

O3_A[13]

O3_A[12]

O3_A[11]

Byte 7

O3_A[10]

O3_A[8]

O3_A[7]

O3_A[6]

O3_A[5]

O3_A[4]

O3_A[3]

O3_A[2]

Byte 8

O3_A[1]

O3_A[0]

O3_D[3]

O3_D[2]

O3_D[1]

O3_D[0]

Last

Address and Data

OTP1

OTP2

OTP3

Figure 11: OTP Write Waveforms

Table 4: Read/Write Option Bits

Byte 1 [0:1] of OTP Packet format

Comments

2’b00: Read mode

Follows format in Table 5

2’b01: Reserved

Not Used

2’b10: Write mode

Follows format in Table 3

2’b11: Return

Exit Read/Write OTP

6.2 Reading the OTP Block

Reading of the NVM via SPI is done by sending a three-byte command packet, which is met with a five-byte

response packet containing the requested NVM data. A diagram of the read command packet structure is given

in Figure 12.

Reading to the OTP has the following steps:

1. Waiting for POR and PLL lock time (1300 us), after that we are sending the Signature bytes through

SPI_MOSI (GPIO_5) by keeping SPI_SS (GPIO_4) low.

2. After Signature bytes matches, GPIO_9 (Config-Sig match) goes high and giving delay of 80 us and then

sending the OTP Read command packet on SPI_MOSI (GPIO_5) by keeping low SPI_SS (GPIO_4) and OTP

read data will come on SPI_MISO (GPIO_6).

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