National Instruments PXIe-6569 Manual de usuario

PXIe-6569

Getting

Started Guide

2023-09-11

Contents

Getting Started Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

ni.com

PXIe-6569 Getting Started Guide

Getting Started Guide

Note Before you begin, install and configure your chassis and controller.

This document explains how to install, configure, test, and use the PXIe-6569. You

can program the PXIe-6569 with the following soware options.

■NI-FlexRIO driver soware

■NI LabVIEW Instrument Design Libraries for FlexRIO (instrument design

libraries)

Note Adapter modules are not installable or interchangeable on the

PXIe-6569 device.

The PXIe-6569 is available in the following fixed LVDS configurations:

■ PXIe-6569 with 32 LVDS In, 32 LVDS Out

■ PXIe-6569 with 64 LVDS In

■ PXIe-6569 with 64 LVDS Out

Note In this document, all variants are referred to inclusively as the

PXIe-6569.

FlexRIO Documentation and Resources

Use the following resources to find more information about the PXIe-6569.

All documentation can be found at ni.com/manuals or in LabVIEW by clicking Help.

PXIe-6569 Getting Started Guide

Table 1. FlexRIO Documentation and Resources

Document Contents

PXIe-6569 Getting Started Guide (this

document) ■Installation instructions

■Basic programming information

PXIe-6569 Specifications ■Operating environment requirements

■DIO specifications

■Clocking specifications

■Physical and mechanical specifications

PXIe-6569 Safety, Environmental, and

Regulatory Information ■Safety and compliance information

■Environmental information

LabVIEW FPGA Module Help ■Basic functionality of the FPGA module

■Instructions for developing and

debugging custom hardware logic

FlexRIO 21.7 Readme ■Minimum system requirements

■Supported Application Development

Environments (ADEs)

■Known issues and bug fixes

■Recent updates

FlexRIO Help ■FlexRIO driver API and programming

information

■I/O Component Level IP (CLIP)

development information

LabVIEW Examples ■Examples showing how to run FPGA VIs

on your device

■Examples showing how to run host VIs

on your device

ni.com

PXIe-6569 Getting Started Guide

Unpacking the Kit

Notice To prevent electrostatic discharge (ESD) from damaging the

module, ground yourself using a grounding strap or by holding a grounded

object, such as your computer chassis.

1. Touch the antistatic package to a metal part of the computer chassis.

2. Remove the module from the package and inspect it for loose components or

other signs of damage.

Notice Never touch the exposed pins of connectors.

Note Do not install a module if it appears damaged in any way.

3. Unpack any other items and documentation from the kit.

Store the module in the antistatic package when the module is not in use.

What You Need to Get Started

Kit Contents

Verify that the following items are included in the PXIe-6569 kit.

■ PXIe-6569 hardware

■Documentation

■PXIe-6569 Getting Started Guide (this document)

■PXIe-6569 Safety, Environmental, and Regulatory Information

PXIe-6569 Getting Started Guide

Recommended Cables

NI oers two lengths of optional SEARAY™ to SEARAY cables for connecting to the

pins on the front panel. The following table shows the details for each.

Model Name Part Number

SR240M-SR240M Cable, LVDS with SE, 0.5m 787317-0R5

SR240M-SR240M Cable, LVDS with SE, 1.0m 787317-01

Installing the Software

You must be an Administrator to install NI soware on your computer.

1. Install an ADE, such as LabVIEW or LabWindows™/CVI™.

2. Download the driver soware installer from ni.com/downloads.

NI Package Manager downloads with the driver soware to handle the

installation. Refer to the NI Package Manager Manual for more information

about installing, removing, and upgrading NI soware using NI Package

Manager.

3. Follow the instructions in the installation prompts.

Note Windows users may see access and security messages during

installation. Accept the prompts to complete the installation.

4. When the installer completes, select Restart in the dialog box that prompts

you to restart, shut down, or restart later.

Installing FlexRIO Modules

This section contains general installation instructions for installing a FlexRIO

module in a PXI Express chassis. Refer to your chassis user manual for specific

instructions and warnings. To install a module, complete the following steps:

ni.com

PXIe-6569 Getting Started Guide

1. Connect the AC power source to the PXI Express chassis before installing the

module. The AC power cord grounds the chassis and protects it from electrical

damage while you install the module.

2. Ensure that the chassis is powered o.

3. Install a module into a chassis slot by first placing the module card PCB into

the front of the card guides (top and bottom), as shown in the following figure.

Slide the module to the rear of the chassis, making sure that the injector/

ejector handle is pushed down, as shown in the following figure.

4. When you begin to feel resistance, push up on the injector/ejector handle to

fully seat the module into the chassis frame. Secure the module front panel to

the chassis using the module front-panel mounting screws.

Figure 1. Installing PXI Express Modules

8899

22HHHHHHHHHHHHHHHH

LOWLOW POWERPOWER

PPXXIIe-1088e-1088

a. Injector/Ejector Handle

b. FlexRIO Module

c. Front Panel Mounting Screws (2x)

d. PXI Express Chassis

e. Injector/Ejector Rail

PXIe-6569 Getting Started Guide

PXIe-6569 Front Panel and Connectors

The following figure shows the front panel and pin layout of the Digital Data &

Control (DDC) connector on the PXIe-6569.

Figure 2. PXIe-6569 Front Panel Layout

PXIe-6569

DIGITAL DATA & CONTROL

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

F30

F31

F32

F33

F34

F35

F36

F37

F38

F39

F40

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

E32

E33

E34

E35

E36

E37

E38

E39

E40

The following figures show the pinout of the DDC connector on the PXIe-6569 for

each connector type. Clock-capable pins are denoted in bold.

ni.com

PXIe-6569 Getting Started Guide

Figure 3. PXIe-6569 with 32 LVDS In, 32 LVDS Out, Rows F-E

Bank 46

Connector SignalFPGA Signal Connector Signal FPGA Signal

aSeGpio(1)

To clocking

circuitry

aDiﬀGpio_p(46)

aDiﬀGpio_n(46)

aDiﬀGpio_p(48)

aDiﬀGpio_n(48)

aDiﬀGpio_p(47)

aDiﬀGpio_n(47)

aDiﬀGpio_p(51)

aDiﬀGpio_n(51)

aDiﬀGpio_p(69)

aDiﬀGpio_n(69)

aDiﬀGpio_p(63)

aDiﬀGpio_n(63)

aDiﬀGpio_p(56)

aDiﬀGpio_n(56)

aDiﬀGpio_p(61)

aDiﬀGpio_n(61)

aDiﬀGpio_p(64)

aDiﬀGpio_n(64)

aDiﬀGpio_p(66)

aDiﬀGpio_n(66)

aDiﬀGpio_p(55)

aDiﬀGpio_n(55)

aSeGpio(3)

aDiﬀGpio_p(58)*

aDiﬀGpio_n(58)*

aDiﬀGpio_p(50)

aDiﬀGpio_n(50)

aDiﬀGpio_p(49)

aDiﬀGpio_n(49)

aDiﬀGpio_p(53)*

aDiﬀGpio_n(53)*

aDiﬀGpio_p(67)

aDiﬀGpio_n(67)

aDiﬀGpio_p(65)

aDiﬀGpio_n(65)

aDiﬀGpio_p(59)

aDiﬀGpio_n(59)

aDiﬀGpio_p(57)*

aDiﬀGpio_n(57)*

aDiﬀGpio_p(60)

aDiﬀGpio_n(60)

aDiﬀGpio_p(62)

aDiﬀGpio_n(62)

aDiﬀGpio_p(68)

aDiﬀGpio_n(68)

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

E32

E33

E34

E35

E36

E37

E38

E39

E40

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

F30

F31

F32

F33

F34

F35

F36

F37

F38

F39

F40

GND

SE 1

SE_GND_TERM

DI 10+*

DI 10-*

DI 11+

DI 11-

GND

DI 12+

DI 12-

GND

DI 13+*

DI 13-*

GND

DI 14+

DI 14-

GND

DI 15+

DI 15-

GND

DI 16+

DI 16-

GND

DI 17+*

DI 17-*

GND

DI 18+

DI 18-

GND

DI 19+

DI 19-

GND

DI 20+

DI 20-

GND

RSVD

GND

SE 0

SE_GND_TERM

CLK IN+

CLK IN-

DI 0+

DI 0-

GND

DI 1+

DI 1-

GND

DI 2+

DI 2-

GND

DI 3+

DI 3-

GND

DI 4+

DI 4-

GND

DI 5+

DI 5-

GND

DI 6+

DI 6-

GND

DI 7+

DI 7-

GND

DI 8+

DI 8-

GND

DI 9+

DI 9-

GND

PFI 0+

PFI 0-

GND

PXIe-6569 Getting Started Guide

Figure 4. PXIe-6569 with 32 LVDS In, 32 LVDS Out, Rows D-C

Connector SignalFPGA Signal

GND

SE 6

SE_GND_TERM

SE 7

SE_GND_TERM

DO 21+

DO 21-

GND

DO 22+

DO 22-

GND

DO 23+

DO 23-

GND

DO 24+

DO 24-

GND

DO 25+

DO 25-

GND

DO 26+

DO 26-

GND

DO 27+

DO 27-

GND

DO 28+

DO 28-

GND

DO 29+

DO 29-

GND

DO 30+

DO 30-

GND

DO 31+

DO 31-

GND

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

Connector Signal FPGA Signal

aSeGpio(5)

aSeGpio(7)

aDiﬀGpio_p(0)

aDiﬀGpio_n(0)

aDiﬀGpio_p(1)

aDiﬀGpio_n(1)

aDiﬀGpio_p(3)

aDiﬀGpio_n(3)

aDiﬀGpio_p(5)

aDiﬀGpio_n(5)

aDiﬀGpio_p(9)

aDiﬀGpio_n(9)

aDiﬀGpio_p(7)

aDiﬀGpio_n(7)

aDiﬀGpio_p(2)

aDiﬀGpio_n(2)

aDiﬀGpio_p(10)

aDiﬀGpio_n(10)

aDiﬀGpio_p(15)*

aDiﬀGpio_n(15)*

aDiﬀGpio_p(13)

aDiﬀGpio_n(13)

aDiﬀGpio_p(6)

aDiﬀGpio_n(6)

GND

SE 2

SE_GND_TERM

SE 3

SE_GND_TERM

DI 21+

DI 21-

GND

DI 22+

DI 22-

GND

DI 23+

DI 23-

GND

DI 24+

DI 24-

GND

DI 25+

DI 25-

GND

DI 26+

DI 26-

GND

DI 27+

DI 27-

GND

DI 28+

DI 28-

GND

DI 29+*

DI 29-*

GND

DI 30+

DI 30-

GND

DI 31+

DI 31-

GND

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

Bank 45

aSeGpio(13)

aSeGpio(15)

aDiﬀGpio_p(4)

aDiﬀGpio_n(4)

aDiﬀGpio_p(8)

aDiﬀGpio_n(8)

aDiﬀGpio_p(12)

aDiﬀGpio_n(12)

aDiﬀGpio_p(11)

aDiﬀGpio_n(11)

aDiﬀGpio_p(16)

aDiﬀGpio_n(16)

aDiﬀGpio_p(14)

aDiﬀGpio_n(14)

aDiﬀGpio_p(19)

aDiﬀGpio_n(19)

aDiﬀGpio_p(17)

aDiﬀGpio_n(17)

aDiﬀGpio_p(21)

aDiﬀGpio_n(21)

aDiﬀGpio_p(20)

aDiﬀGpio_n(20)

aDiﬀGpio_p(18)

aDiﬀGpio_n(18)

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PXIe-6569 Getting Started Guide

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