Intel Pentium M Processor Guía

Intel®Pentium®M Processor and

the Intel®E7501 Chipset Platform

For use with the Intel®Pentium®M Processor and the Intel®

Pentium®M Processor on the 90 nm process with 2-MB L2 cache

Design Guide

January 2007

Order Number: 273871-007

2 Design Guide

Intel®Pentium®M Processor and Intel®E7501 Chipset Platform

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Design Guide 3

Intel®Pentium®M Processor and Intel®E7501 Chipset Platform

Contents

1 Introduction..................................................................................................................................19

1.1 Reference Documents........................................................................................................19

1.2 Terminology........................................................................................................................21

1.3 System Overview................................................................................................................24

1.3.1 Intel®Pentium®M Processor ................................................................................24

1.3.1.1 Architectural Features............................................................................25

1.3.1.2 Packaging/Power...................................................................................25

1.3.1.3 Enhanced Intel®SpeedStep®Technology ............................................25

1.3.2 Intel®Pentium®M Processor on the 90 nm process with 2-MB L2 Cache ...........26

1.3.3 Intel®E7501 Chipset .............................................................................................27

1.3.3.1 Intel®E7501 Memory Controller Hub (MCH).........................................27

1.3.3.2 I/O Controller Hub 3 (Intel®82801CA ICH3-S) Features.......................28

1.3.3.3 PCI/PCI-X 64-bit Hub 2 (Intel®P64H2) Features ..................................28

1.3.4 Peak Bandwidth Summary ....................................................................................29

1.3.5 System Configurations...........................................................................................29

2 Component Quadrant Layout.....................................................................................................31

2.1 Intel®Pentium®M Processor Quadrant Layout..................................................................32

2.2 Intel®E7501 Chipset MCH Quadrant Layout .....................................................................33

2.3 Intel®ICH3-S Quadrant Layout ..........................................................................................34

2.4 Intel®P64H2 Quadrant Layout...........................................................................................35

3 Baseboard Requirements...........................................................................................................37

3.1 Platform Stack-Up...............................................................................................................37

3.2 Processor Thermal Solution Placement and Recommended Keep-Outs...........................38

4 Platform Clock Routing Guidelines ...........................................................................................39

4.1 Platform Clock ....................................................................................................................39

4.2 HOST_CLK Clock Group....................................................................................................42

4.2.1 HOST_CLK Clock Topology..................................................................................42

4.2.1.1 BCLK Length Matching Requirements (mFCPGA)................................45

4.2.2 HOST_CLK General Routing Guidelines...............................................................45

4.2.3 CK408 vs. CK408B Requirement ..........................................................................46

4.3 CLK66 Clock Group............................................................................................................47

4.3.1 CLK66 Skew Requirements...................................................................................48

4.4 CLK33_ICH3-S Clock Group..............................................................................................50

4.5 CLK33 Clock Group............................................................................................................50

4.6 CLK14 Clock Group............................................................................................................52

4.7 USBCLK Clock Group ........................................................................................................53

4.8 Clock Driver Decoupling .....................................................................................................54

4.9 Clock Driver Power Delivery...............................................................................................55

5 System Bus Routing Guidelines................................................................................................57

5.1 Intel®Pentium®M Processor System Bus

Design Recommendations..................................................................................................57

5.1.1 System Bus Signals...............................................................................................57

5.1.2 Processor System Bus Termination.......................................................................58

4 Design Guide

Intel®Pentium®M Processor and Intel®E7501 Chipset Platform

Contents

5.1.3 Recommended Stack-up Routing and Spacing Assumptions...............................59

5.1.4 Trace Space to Trace - Reference Plane Separation Ratio ..................................59

5.1.4.1 Trace Space to Trace Width Ratio.........................................................59

5.1.4.2 Processor RESET# Signal.....................................................................60

5.1.5 Source Synchronous Signals.................................................................................61

5.1.5.1 Source Synchronous General Routing Guidelines ................................61

5.1.5.2 Source Synchronous – Data..................................................................62

5.1.5.3 Source Synchronous – Address ............................................................63

5.1.6 Common Clock Signals .........................................................................................64

5.1.7 Asynchronous Signals...........................................................................................65

5.1.7.1 Topologies .............................................................................................65

5.1.7.2 Voltage Translation Logic ......................................................................69

5.1.8 AGTL+ I/O Buffer Compensation...........................................................................70

5.1.8.1 Intel®Pentium®M Processor AGTL+ I/O Buffer Compensation ...........70

5.1.8.2 Intel®E7501 Chipset AGTL+ I/O Buffer Compensation ........................70

5.1.9 Intel®Pentium®M Processor System Bus Strapping............................................71

5.1.10 Intel®Pentium®M Processor VCCSENSE/VSSSENSE

Design Recommendations.....................................................................................72

6 Memory Interface Routing Guidelines.......................................................................................73

6.1 DDR Channel Impedance Requirements ...........................................................................74

6.2 DIMM Types.......................................................................................................................75

6.3 Dual Channel DDR Overview.............................................................................................76

6.3.1 Dual Channel Source Synchronous Signal Group Routing...................................78

6.3.2 Dual Channel Command Clock Routing................................................................82

6.3.3 Dual Channel Source Clocked Signal Group Routing...........................................83

6.3.4 Dual Channel Chip Select Routing........................................................................84

6.3.5 Dual Channel Clock Enable Routing .....................................................................85

6.3.6 Dual Channel DC Biasing Signals.........................................................................86

6.3.6.1 Dual Channel Receive Enable Signal (RCVEN#)..................................87

6.3.6.2 Dual Channel DDRCOMP......................................................................87

6.3.6.3 Dual Channel DDRVREF and ODTCOMP ............................................88

6.3.6.4 Dual Channel DDRCVO.........................................................................90

6.3.7 Dual Channel DDR Signal Termination and Decoupling.......................................90

6.3.8 2.5 Volt Decoupling Requirements........................................................................91

6.4 Single Channel DDR Overview...........................................................................................94

6.4.1 Unused Channel Termination................................................................................96

6.4.2 Single Channel Source Synchronous Signal Group Routing.................................97

6.4.3 Single Channel Command Clock Routing ...........................................................100

6.4.4 Single Channel Source Clocked Signal Group Routing.......................................101

6.4.5 Single Channel Chip Select Routing....................................................................102

6.4.6 Single Channel Clock Enable Routing.................................................................103

6.4.7 Single Channel DC Biasing Signals.....................................................................104

6.4.7.1 Single Channel Receive Enable Signal (RCVEN#) .............................104

6.4.7.2 Single Channel DDRCOMP.................................................................104

6.4.7.3 Single Channel DDRVREF and ODTCOMP........................................105

6.4.7.4 Single Channel DDRCVO....................................................................107

6.4.8 Single Channel DDR Signal Termination and Decoupling...................................108

6.4.9 2.5 V Decoupling Requirements..........................................................................109

Design Guide 5

Intel®Pentium®M Processor and Intel®E7501 Chipset Platform

Contents

7HubInterface..............................................................................................................................113

7.1 Signal Naming Convention ...............................................................................................113

7.2 Hub Interface 2.0 Implementation.....................................................................................114

7.2.1 Hub Interface 2.0 High-Speed Routing Guidelines..............................................114

7.2.2 Hub Interface 2.0 Generation/Distribution of Reference Voltages.......................117

7.2.3 Hub Interface 2.0 Resistive Compensation..........................................................118

7.2.4 Hub Interface 2.0 Decoupling Guidelines ............................................................119

7.2.5 Unused Hub Interface 2.0 Interfaces...................................................................119

7.3 Hub Interface 1.5 Implementation.....................................................................................120

7.3.1 Hub Interface 1.5 High-Speed Routing Guidelines..............................................120

7.3.2 Hub Interface 1.5 Generation/Distribution of Reference Voltages.......................121

7.3.3 Hub Interface 1.5 Resistive Compensation..........................................................122

7.3.4 Hub Interface 1.5 Decoupling Guidelines ............................................................122

8Intel

®82870P2 (Intel P64H2).....................................................................................................123

8.1 PCI/PCI-X Design Guidelines...........................................................................................123

8.1.1 General PCI-X Routing Guidelines......................................................................124

8.1.2 PCI/PCI-X Routing Requirements (No Hot-Plug Switch).....................................125

8.1.3 PCI/PCI-X Hot-Plug Switch Routing Requirements.............................................125

8.1.4 Riser Card Topologies.........................................................................................126

8.1.5 PCI-X Two Devices Down-Routing Requirements...............................................128

8.1.6 Clock Configuration .............................................................................................129

8.1.7 Loop Clock Configuration ....................................................................................130

8.1.8 IDSEL Implementation.........................................................................................131

8.1.9 SMBus Address...................................................................................................131

8.2 Hot-Plug Implementation ..................................................................................................132

8.2.1 Standard Usage Model........................................................................................132

8.2.1.1 Hot-Removals ......................................................................................133

8.2.1.2 Hot-Insertions.......................................................................................133

8.2.2 Hot-Plug Switch Implementation..........................................................................134

8.2.2.1 Manually-Operated Retention Latch Sensor........................................134

8.2.2.2 Optional Attention Button.....................................................................135

8.2.3 LED Indicator Outputs .........................................................................................135

8.2.4 Hot Plug Interrupt Routing Requirements............................................................135

8.2.5 Hot-Plug Interrupt Routing Requirements............................................................136

8.2.6 Disabling/Enabling an Intel® P64H2 Hot-Plug Controller.....................................136

8.2.6.1 Hot-Plug Strapping Options .................................................................136

8.2.6.2 Hot-Plug Registers’ Visibility................................................................136

8.2.7 Single-Slot Parallel Mode ....................................................................................136

8.2.7.1 Required Additional Logic....................................................................136

8.2.7.2 PCI Clock.............................................................................................137

8.2.7.3 Debounced Hot-Plug Switch Input.......................................................137

8.2.7.4 Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins............................137

8.2.7.5 Tri-State Buffer or 2:1 Multiplexer for HPx_SLOT[2:0].........................137

8.2.7.6 Hot-Plug Multiplexed Signals in Single-Slot Parallel Mode..................138

8.2.7.7 SMBus Address Considerations ..........................................................139

8.2.7.8 Single-Slot Parallel SMBus Circuit.......................................................140

8.2.7.9 Pull-Ups/Pull-Downs in Single-Slot Parallel Mode...............................140

8.2.7.10 Reference Schematic for Single-Slot Parallel Mode............................140

8.2.8 Dual-Slot Parallel Mode.......................................................................................141

8.2.8.1 Required Additional Logic....................................................................141

6 Design Guide

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Contents

8.2.8.2 Debounced Hot-Plug Switch Input.......................................................142

8.2.8.3 Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins............................142

8.2.8.4 Tri-State Buffer or 2:1 Multiplexer for HPx_SLOT[2:0].........................142

8.2.8.5 HPx_SID Output Signal .......................................................................142

8.2.8.6 Pull-Ups/Pull-Downs in Dual-Slot Parallel Mode..................................142

8.2.8.7 Hot-Plug Multiplexed Signals in Dual-Slot Parallel Mode ....................142

8.2.8.8 SMBus Address Considerations..........................................................144

8.2.8.9 Reference Schematic for Dual-Slot Parallel Mode...............................144

8.2.9 Three or More Slot Serial Mode...........................................................................145

8.2.9.1 Hot-Plug and Non-Hot-Plug Combinations..........................................145

8.2.9.2 Required Additional Logic....................................................................146

8.2.9.3 Debounced Hot-Plug Switch Input.......................................................146

8.2.9.4 Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins............................146

8.2.9.5 HPx_SLOT[2:0]....................................................................................146

8.2.9.6 Stutter Logic for Implementing Fewer Than Six Slots..........................146

8.2.9.7 Pull-Ups/Pull-Downs in Three or More Slot Serial Mode.....................147

8.2.9.8 Reference Schematic for Serial Mode.................................................148

8.2.10 Intel® P64H2 PCI Interface PCIXCAP and M66EN Pins .....................................148

8.2.10.1 PCIXCAP Pin Requirements................................................................148

8.2.10.2 M66EN Pin Requirements ...................................................................149

9 I/O Controller Hub 3 (Intel®ICH3-S).........................................................................................153

9.1 IDE Interface.....................................................................................................................153

9.1.1 Cabling.................................................................................................................153

9.1.2 Cable Detection for Ultra ATA/66 and Ultra ATA/100..........................................153

9.1.2.1 Combination Host-Side/Device-Side Cable Detection.........................154

9.1.3 IDE Connector Requirements..............................................................................155

9.2 SPKR Pin Consideration...................................................................................................156

9.3 PCI....................................................................................................................................156

9.4 USB ..................................................................................................................................157

9.4.1 General Routing and Placement..........................................................................157

9.4.2 USB Routing Parameters ....................................................................................158

9.4.3 EMI Considerations .............................................................................................158

9.4.4 USB Power Line Layout Topologies....................................................................158

9.5 Intel®ICH3-S SMBus/SMLink Interface ...........................................................................159

9.5.1 SMBus Design Considerations............................................................................160

9.5.2 Unified VCC_CORE Architecture ........................................................................161

9.5.3 High Power/Low Power Mixed Architecture.........................................................161

9.5.4 Calculating The Physical Segment Pull-Up Resistor...........................................162

9.6 Real Time Clock (RTC).....................................................................................................163

9.6.1 RTC External Circuit............................................................................................164

9.6.2 RTC External RTCRST# Circuit ..........................................................................164

9.6.3 External Capacitors .............................................................................................165

9.6.3.1 Example with Load Capacitance..........................................................165

9.6.4 RTC Layout Considerations.................................................................................166

9.6.5 RTC External Battery Connection........................................................................166

9.6.6 VBIAS DC Voltage and Noise Measurements.....................................................166

9.6.7 SUSCLK ..............................................................................................................167

9.6.8 RTC-Well Input Strap Requirements...................................................................167

9.7 Internal LAN Layout Guidelines........................................................................................168

9.7.1 LCI (LAN Connect Interface) Guidelines .............................................................169

Design Guide 7

Intel®Pentium®M Processor and Intel®E7501 Chipset Platform

Contents

9.7.1.1 Bus Topology.......................................................................................169

9.7.1.2 LCI Routing Parameters ......................................................................169

9.7.2 General LAN Routing Guidelines and Considerations.........................................170

9.7.2.1 General Trace Routing Considerations................................................170

9.7.2.2 Trace Geometry and Length................................................................171

9.7.2.3 Signal Isolation.....................................................................................171

9.7.2.4 Power and Ground Connections..........................................................172

9.7.2.5 General Power and Ground Plane Consideration................................172

9.7.2.6 Board Design.......................................................................................173

9.7.2.7 Common Physical Layout Issues.........................................................173

9.7.3 Intel®82562ET/Intel®82562EM Guidelines........................................................175

9.7.3.1 Intel®82562ET/Intel®82562EM Component Placement Guidelines...175

9.7.3.2 Crystals and Oscillators .......................................................................175

9.7.3.3 Intel®82562ET/Intel®82562EM Termination Resistors ......................176

9.7.4 Critical Dimensions..............................................................................................176

9.7.4.1 Distance from Magnetics Module to RJ45 (Distance A) ......................177

9.7.4.2 Distance from Intel® 82562ET to Magnetics Module (Distance B)......177

9.7.5 Terminating Unused Connections .......................................................................177

9.7.5.1 Termination Plane Capacitance...........................................................178

10 Debug Port and Logic Analyzer Interface ...............................................................................179

10.1 ITP Support.......................................................................................................................179

10.1.1 Overview..............................................................................................................179

10.1.2 Implementation ....................................................................................................179

10.2 Recommended Onboard ITP700FLEX Implementation ...................................................180

10.2.1 ITP Signal Routing Guidelines.............................................................................180

10.2.1.1 TDI, TMS and TRST# Routing Requirements .....................................180

10.2.1.2 TCK and TDO Routing Requirements .................................................181

10.2.1.3 BPMx# Routing Requirements.............................................................181

10.2.1.4 RESET# Routing Guidelines................................................................182

10.2.1.5 BCLK Routing Requirements...............................................................182

10.2.1.6 ITPFLEX Routing Requirement Summary...........................................182

10.3 Intel®Pentium®M Processor Logic Analyzer Support .....................................................184

10.3.1 Overview..............................................................................................................184

10.3.2 Implementation ....................................................................................................184

10.4 Logic Analyzer Interface (LAI) ..........................................................................................184

10.4.1 Mechanical Considerations..................................................................................185

10.4.2 Electrical Considerations .....................................................................................185

11 Platform Power Delivery Guidelines........................................................................................187

11.1 Processor Voltage Regulator Power Delivery Architectural Block Diagram .....................188

11.2 Customer Reference Board Power Delivery.....................................................................188

11.2.1 Processor Core Voltage (VCC_CORE) ...............................................................190

11.2.2 System Bus Voltage (VCCP 1.05 V)....................................................................190

11.2.3 2.5 V ....................................................................................................................190

11.2.4 1.25 V ..................................................................................................................190

11.2.5 1.8 V ....................................................................................................................191

11.2.6 1.2 V ....................................................................................................................191

11.2.7 5 VSB...................................................................................................................191

11.2.8 3.3 VSB................................................................................................................191

11.2.9 1.8 VSB................................................................................................................191

11.2.10 Power Summary ..................................................................................................191

8 Design Guide

Intel®Pentium®M Processor and Intel®E7501 Chipset Platform

Contents

11.3 Processor Power Delivery Design Guidelines..................................................................192

11.3.1 Processor PLL Power Delivery............................................................................192

11.3.2 Voltage Identification for Intel®Pentium®M Processor.......................................192

11.3.3 VCC_CORE Power Sequencing.............................................................................194

11.3.4 VCCP Output Requirements................................................................................194

11.3.5 Thermal Power Dissipation..................................................................................195

11.3.6 Voltage Regulator Topology................................................................................196

11.3.7 Voltage Regulator Design Recommendations.....................................................197

11.3.7.1 High Current Path, Top MOSFET Turned ON.....................................197

11.3.7.2 High Current Paths During Abrupt Load Current Changes..................198

11.3.7.3 High Current Paths During Switching Dead Time................................198

11.3.7.4 High Current Path With Bottom MOSFET(s) Turned ON.....................199

11.3.7.5 General Layout Recommendations .....................................................199

11.3.8 Processor Decoupling Recommendations...........................................................201

11.3.8.1 Transient Response.............................................................................201

11.3.8.2 High/Mid Frequency and Bulk Decoupling...........................................201

11.3.8.3 Processor Core Voltage Plane and Decoupling...................................201

11.3.8.4 Processor Side Bus Voltage Plane Decoupling...................................202

11.3.8.5 GTLREF Layout and Routing Recommendations................................202

11.4 MCH Power Delivery Guidelines ......................................................................................203

11.4.1 DDR_VTT (1.25 V) Decoupling ...........................................................................203

11.4.2 CPU_VCC (1.05 V Power Plane)........................................................................203

11.4.3 DDR (2.5 V Power Plane)....................................................................................204

11.4.4 Hub Interface (1.2 V Power Plane)......................................................................205

11.4.5 Intel®E7501 Chipset Filter Specifications (1.2 V Power Plane)..........................205

11.4.6 MCH Power Sequencing Requirement................................................................206

11.5 Intel®ICH3-S Power Delivery Guidelines.........................................................................207

11.5.1 1.8 V/3.3 V Power Sequencing............................................................................207

11.5.2 3.3V / V5REF Sequencing...................................................................................209

11.5.3 Intel®ICH3-S Power Rails...................................................................................210

11.5.4 Intel®ICH3-S Decoupling Recommendations.....................................................210

11.6 Intel®P64H2 Power Requirements..................................................................................212

11.6.1 Intel®P64H2 Current Requirements ...................................................................212

11.6.2 Intel®P64H2 Decoupling Requirements .............................................................212

11.6.3 PCIRST# Implementation....................................................................................213

11.6.4 Intel®P64H2 Power Sequencing Requirement...................................................213

12 High-Speed Design Concerns..................................................................................................215

12.1 Return Path.......................................................................................................................215

12.2 Decoupling Theory............................................................................................................215

12.2.1 Bulk Decoupling...................................................................................................216

12.2.2 High-Frequency Decoupling................................................................................216

12.3 Serpentine Routing...........................................................................................................217

12.4 EMI Design Considerations..............................................................................................218

12.4.1 Brief EMI Theory..................................................................................................218

12.4.2 EMI Regulations and Certifications......................................................................218

12.5 EMI Design Considerations..............................................................................................219

12.5.1 Spread Spectrum Clocking (SSC).......................................................................219

12.5.2 Differential Clocking.............................................................................................220

12.5.3 PCI Bus Clock Control.........................................................................................221

12.5.4 EMI Test Capabilities...........................................................................................221

Design Guide 9

Intel®Pentium®M Processor and Intel®E7501 Chipset Platform

Contents

12.6 Length Tuning...................................................................................................................222

12.6.1 Signal to Strobe Flight Time Relationships..........................................................222

12.6.2 Flight Time Segment Analysis .............................................................................225

12.6.3 Length Tuning Equation Derivation .....................................................................226

12.6.4 Bus Length Tuning Methodology.........................................................................228

12.7 Processor Bus Tuning ......................................................................................................228

12.7.1 Compensating for Package Trace Length Differences........................................228

12.7.2 Length Matching Equation...................................................................................229

12.7.3 System Bus Length Matching Example...............................................................231

12.8 Intel®Pentium®M Processor Signal Package Lengths....................................................232

12.9 Common Layout Pitfalls....................................................................................................233

12.9.1 Group Like Signals Under BGAs.........................................................................233

12.9.2 Fill Areas Under BGAs.........................................................................................235

12.9.3 Signal Parallelism ................................................................................................236

12.9.4 Via Sharing..........................................................................................................237

12.9.5 Necking Down......................................................................................................239

12.9.6 Signals Crossing Plane Splits..............................................................................241

13 Schematic Checklist..................................................................................................................243

13.1 Processor Schematic Checklist ........................................................................................243

13.2 MCH Schematic Checklist ................................................................................................248

13.3 Intel®ICH3-S Schematic Checklist...................................................................................252

13.4 Intel®82870P2 (Intel P64H2) Schematic Checklist..........................................................260

13.5 CK408 Schematic Checklist .............................................................................................265

14 Layout Checklist........................................................................................................................267

14.1 Processor Checklist..........................................................................................................267

14.2 Intel®E7501 MCH Layout Checklist.................................................................................271

14.3 Intel®ICH3-S Layout Checklist.........................................................................................275

14.4 Intel®P64H2 Layout Checklist..........................................................................................279

10 Design Guide

Intel®Pentium®M Processor and Intel®E7501 Chipset Platform

Contents

Figures

1Intel

®Pentium®M Processor and Intel®E7501Chipset-Based System

Configuration Example ...............................................................................................................30

2Intel

®Pentium®M Processor Quadrant Layout (Top View).......................................................32

3Intel

®E7501 Chipset MCH Quadrant Layout (Top View)...........................................................33

4Intel

®ICH3-S Quadrant Layout (Top View)................................................................................34

5Intel

® P64H2 Quadrant Layout (Top View).................................................................................35

6 Ten Layer Stack-up, 50 ΩBoard with 5-Mil Traces....................................................................37

7 System Clocking Diagram Example...........................................................................................41

8 Shunt Source Termination..........................................................................................................42

9 Clock Skew As Measured from Agent to Agent..........................................................................44

10 Trace Spacing for HOST_CLK Clocks .......................................................................................45

11 Stuffing Options for CK408 and CK408B ...................................................................................46

12 Topology for CLK66....................................................................................................................47

13 Clock Skew Requirements .........................................................................................................48

14 Example of Adding a Single Connector......................................................................................49

15 Example of Adding Two Connectors and/or a Riser...................................................................49

16 Topology for CLK33_ICH3-S......................................................................................................50

17 Topology for CLK33 to PCI Device Down ..................................................................................50

18 Topology for CLK33 to PCI Slot .................................................................................................51

19 Topology for CLK14....................................................................................................................52

20 Topology for USB_CLK..............................................................................................................53

21 Decoupling Capacitors Placement and Connectivity .................................................................54

22 Processor System Bus Topology ...............................................................................................58

23 Trace Spacing vs. Trace-Reference Plane Example..................................................................59

24 Trace Spacing vs. Trace Width Example ...................................................................................60

25 Processor RESET# Signal Routing Topology With NO ITP700FLEX Connector ......................60

26 Processor RESET# Signal Routing Topology With ITP700FLEX Connector.............................61

27 Routing Illustration for Topology 1A ...........................................................................................66

28 Routing Illustration for Topology 1B ...........................................................................................66

29 Routing Illustration for Topology 1C ...........................................................................................67

30 Routing Illustration for Topology 2A ...........................................................................................68

31 Routing Illustration for Topology 3..............................................................................................69

32 Voltage Translation Circuit .........................................................................................................70

33 Resistor Divider Circuit For The MCH’s HXSWNG And HYSWNG............................................71

34 Trace Width and Spacing for All DDR Signals Except CMDCLK_x[3:0]/CMDCLK_x[3:0]# .......75

35 DIMM Connector Styles Supported............................................................................................76

36 1-DIMM per Channel Implementation.........................................................................................77

37 2-DIMMs per Channel Implementation.......................................................................................77

38 Example of Proper Single and Dual Rank Mixing.......................................................................78

39 Example of Incorrect Single and Dual Rank Mixing ...................................................................78

40 Dual Channel Source Synchronous Topology DIMM Solution...................................................81

41 Trace Length Matching Requirements for Source Synchronous Routing ..................................81

42 Dual Channel 2-DIMM Command Clock Topology.....................................................................83

43 Dual Channel Source Clocked Signal Topology.........................................................................84

44 Dual Channel Chip Select Topology...........................................................................................85

45 Dual Channel CKE Topology......................................................................................................86

46 Dual Channel Receive Enable Signal Routing Guidelines .........................................................87

47 Dual Channel DDRCOMP Resistive Compensation ..................................................................88

48 DDR VREF Voltage Regulator ...................................................................................................88

Este manual sirve para los siguientes modelos

Tabla de contenidos

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