Freescale Semiconductor ColdFire MCF5213 Manual de usuario

MCF5213 ColdFire®Integrated

Microcontroller Reference Manual

Devices Supported:

MCF5211

MCF5212

MCF5213

Document Number: MCF5213RM

Rev. 3

03/2007

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Document Number: MCF5213RM

Rev. 3

03/2007

Overview

Signal Descriptions

ColdFire Core

Multiply-Accumulate Unit (MAC)

Static RAM (SRAM)

Clock Module

Power Management

Chip Configuration Module (CCM)

Reset Controller Module

System Control Module (SCM)

General Purpose I/O Module

Interrupt Controller Module

Edge Port Module (EPORT)

DMA Controller Module

ColdFire Flash Module (CFM)

EzPort

Programmable Interrupt Timers (PIT0–PIT1)

General Purpose Timer Module (GPT)

DMA Timers (DTIM0–DTIM3)

Queued Serial Peripheral Interface (QSPI)

UART Modules

I2C Interface

Analog-to-Digital Converter (ADC)

Pulse-Width Modulation (PWM) Module

FlexCAN

Debug Module

IEEE 1149.1 Test Access Port (JTAG)

Overview

Signal Descriptions

ColdFire Core

Multiply-Accumulate Unit (MAC)

Static RAM (SRAM)

Clock Module

Power Management

Chip Configuration Module (CCM)

Reset Controller Module

System Control Module (SCM)

General Purpose I/O Module

Interrupt Controller Module

Edge Port Module (EPORT)

DMA Controller Module

ColdFire Flash Module (CFM)

EzPort

Programmable Interrupt Timers (PIT0–PIT1)

General Purpose Timer Module (GPT)

DMA Timers (DTIM0–DTIM3)

Queued Serial Peripheral Interface (QSPI)

UART Modules

I2C Interface

Analog-to-Digital Converter (ADC)

Pulse-Width Modulation (PWM) Module

FlexCAN

Debug Module

IEEE 1149.1 Test Access Port (JTAG)

MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3

Freescale Semiconductor v

Contents

Paragraph

Number Title Page

Number

About This Book

Audience ...................................................................................................................... xxvii

Organization ................................................................................................................. xxvii

Conventions .................................................................................................................. xxix

Acronyms and Abbreviations ....................................................................................... xxxi

Terminology Conventions ............................................................................................ xxxii

Chapter 1

Overview

1.1 MCF5213 Family Configurations ................................................................................... 1-2

1.2 Block Diagram ................................................................................................................ 1-3

1.3 Part Numbers and Packaging .......................................................................................... 1-3

1.4 Features ........................................................................................................................... 1-4

1.4.1 V2 Core Overview ...................................................................................................... 1-8

1.4.2 Integrated Debug Module ........................................................................................... 1-9

1.4.3 JTAG ........................................................................................................................... 1-9

1.4.4 On-Chip Memories ................................................................................................... 1-10

1.4.4.1 SRAM ................................................................................................................... 1-10

1.4.4.2 Flash Memory ....................................................................................................... 1-10

1.4.5 Power Management .................................................................................................. 1-10

1.4.6 FlexCAN ...................................................................................................................1-10

1.4.7 UARTs ...................................................................................................................... 1-11

1.4.8 I2C Bus ...................................................................................................................... 1-11

1.4.9 QSPI .......................................................................................................................... 1-11

1.4.10 Fast ADC .................................................................................................................. 1-11

1.4.11 DMA Timers (DTIM0–DTIM3) ............................................................................... 1-11

1.4.12 General Purpose Timer (GPT) .................................................................................. 1-12

1.4.13 Periodic Interrupt Timers (PIT0 and PIT1) .............................................................. 1-12

1.4.14 Pulse-Width Modulation (PWM) Timers ................................................................. 1-12

1.4.15 Software Watchdog Timer ........................................................................................ 1-12

1.4.16 Phase-Locked Loop (PLL) ........................................................................................ 1-12

1.4.17 Interrupt Controller (INTC) ...................................................................................... 1-13

1.4.18 DMA Controller ........................................................................................................ 1-13

1.4.19 Reset .......................................................................................................................... 1-13

1.4.20 GPIO ......................................................................................................................... 1-13

Contents

MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3

vi Freescale Semiconductor

Contents

Paragraph

Number Title Page

Number

Chapter 2

Signal Descriptions

2.1 Introduction ..................................................................................................................... 2-1

2.2 Overview ......................................................................................................................... 2-1

2.3 Reset Signals ................................................................................................................... 2-7

2.4 PLL and Clock Signals ................................................................................................... 2-7

2.5 Mode Selection ............................................................................................................... 2-7

2.6 External Interrupt Signals ............................................................................................... 2-8

2.7 Queued Serial Peripheral Interface (QSPI) ..................................................................... 2-8

2.8 I2C I/O Signals ................................................................................................................ 2-9

2.9 UART Module Signals ................................................................................................... 2-9

2.10 DMA Timer Signals ........................................................................................................ 2-9

2.11 ADC Signals ................................................................................................................. 2-10

2.12 General Purpose Timer Signals .................................................................................... 2-10

2.13 Pulse-Width Modulator Signals .................................................................................... 2-10

2.14 Debug Support Signals ................................................................................................. 2-10

2.15 EzPort Signal Descriptions ........................................................................................... 2-12

2.16 Power and Ground Pins ................................................................................................ 2-12

Chapter 3

ColdFire Core

3.1 Processor Pipelines .........................................................................................................3-1

3.2 Memory Map/Register Description ................................................................................ 3-2

3.2.1 Data Registers (D0–D7) .............................................................................................. 3-4

3.2.2 Address Registers (A0–A6) ........................................................................................ 3-4

3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) .............................................. 3-4

3.2.4 Condition Code Register (CCR) ................................................................................. 3-5

3.2.5 Program Counter (PC) ................................................................................................ 3-6

3.2.6 Vector Base Register (VBR) ....................................................................................... 3-6

3.2.7 Status Register (SR) .................................................................................................... 3-7

3.2.8 Memory Base Address Registers (RAMBAR, FLASHBAR) .................................... 3-8

3.3 Instruction Set Architecture (ISA_A+) ........................................................................... 3-8

3.4 Exception Processing Overview ..................................................................................... 3-9

3.4.1 Exception Stack Frame Definition ............................................................................ 3-10

3.5 Processor Exceptions .................................................................................................... 3-12

3.5.1 Access Error Exception ............................................................................................ 3-12

3.5.2 Address Error Exception ........................................................................................... 3-12

3.5.3 Illegal Instruction Exception ..................................................................................... 3-12

3.5.4 Divide-By-Zero ......................................................................................................... 3-13

MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3

Freescale Semiconductor vii

Contents

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Number

3.5.5 Privilege Violation .................................................................................................... 3-14

3.5.6 Trace Exception ........................................................................................................ 3-14

3.5.7 Unimplemented Line-A Opcode ............................................................................... 3-14

3.5.8 Unimplemented Line-F Opcode ............................................................................... 3-14

3.5.9 Debug Interrupt ......................................................................................................... 3-15

3.5.10 RTE and Format Error Exception ............................................................................. 3-15

3.5.11 TRAP Instruction Exception ..................................................................................... 3-15

3.5.12 Interrupt Exception ................................................................................................... 3-15

3.5.13 Fault-on-Fault Halt ................................................................................................... 3-15

3.5.14 Reset Exception ........................................................................................................ 3-15

3.6 Instruction Execution Timing ....................................................................................... 3-19

3.6.1 Timing Assumptions ................................................................................................. 3-19

3.6.2 MOVE Instruction Execution Times ........................................................................ 3-20

3.6.3 Standard One Operand Instruction Execution Times ............................................... 3-21

3.6.4 Standard Two Operand Instruction Execution Times ............................................... 3-22

3.6.5 Miscellaneous Instruction Execution Times ............................................................. 3-23

3.6.6 MAC Instruction Execution Times ........................................................................... 3-24

3.6.7 Branch Instruction Execution Times ........................................................................ 3-25

Chapter 4

Multiply-Accumulate Unit (MAC)

4.1 Multiply-Accumulate Unit .............................................................................................. 4-1

4.2 Introduction to the MAC ................................................................................................. 4-1

4.3 General Operation ...........................................................................................................4-2

4.4 Memory Map/Register Definition .................................................................................. 4-3

4.4.1 MAC Status Register (MACSR) ................................................................................. 4-3

4.4.1.1 Fractional Operation Mode ..................................................................................... 4-5

4.4.1.1.1 Rounding ............................................................................................................ 4-5

4.4.1.1.2 Saving and Restoring the MAC Programming Model ....................................... 4-6

4.4.1.1.3 MULS/MULU .................................................................................................... 4-6

4.4.1.1.4 Scale Factor in MAC or MSAC Instructions ...................................................... 4-6

4.4.2 Mask Register (MASK) .............................................................................................. 4-7

4.4.3 Accumulator Register (ACC) ..................................................................................... 4-8

4.5 MAC Instruction Set Summary ...................................................................................... 4-8

4.5.1 MAC Instruction Execution Times ............................................................................. 4-9

4.5.2 Data Representation .................................................................................................... 4-9

4.5.3 MAC Opcodes ............................................................................................................ 4-9

MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3

viii Freescale Semiconductor

Contents

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Number

Chapter 5

Static RAM (SRAM)

5.1 Introduction ..................................................................................................................... 5-1

5.1.1 Overview ..................................................................................................................... 5-1

5.1.2 Features ....................................................................................................................... 5-1

5.2 Memory Map/Register Description ................................................................................ 5-1

5.2.1 SRAM Base Address Register (RAMBAR) ............................................................... 5-2

5.3 Initialization/Application Information ............................................................................ 5-3

5.3.1 SRAM Initialization Code .......................................................................................... 5-4

5.3.2 Power Management .................................................................................................... 5-4

Chapter 6

Clock Module

6.1 Introduction ..................................................................................................................... 6-1

6.2 Features ........................................................................................................................... 6-1

6.3 Modes of Operation ........................................................................................................ 6-1

6.3.1 Normal PLL Mode ...................................................................................................... 6-1

6.3.2 1:1 PLL Mode ............................................................................................................. 6-2

6.3.3 External Clock Mode .................................................................................................. 6-2

6.4 Low-Power Mode Operation .......................................................................................... 6-2

6.5 Block Diagram ................................................................................................................ 6-2

6.6 Signal Descriptions .........................................................................................................6-4

6.6.1 EXTAL ....................................................................................................................... 6-4

6.6.2 XTAL .......................................................................................................................... 6-4

6.6.3 CLKOUT ....................................................................................................................6-4

6.6.4 CLKMOD[1:0] ........................................................................................................... 6-4

6.6.5 RSTO .......................................................................................................................... 6-5

6.7 Memory Map and Registers ............................................................................................ 6-5

6.7.1 Register Descriptions .................................................................................................. 6-5

6.7.1.1 Synthesizer Control Register (SYNCR) ................................................................. 6-5

6.7.1.2 Synthesizer Status Register (SYNSR) .................................................................... 6-7

6.7.1.3 Low-Power Divider Register (LPDR) .................................................................... 6-9

6.8 Functional Description .................................................................................................. 6-10

6.8.1 System Clock Modes ................................................................................................ 6-10

6.8.2 Clock Operation During Reset .................................................................................. 6-10

6.8.3 System Clock Generation ......................................................................................... 6-11

6.8.4 PLL Operation .......................................................................................................... 6-11

6.8.4.1 Phase and Frequency Detector (PFD) ................................................................... 6-12

6.8.4.2 Charge Pump/Loop Filter ..................................................................................... 6-12

MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3

Freescale Semiconductor ix

Contents

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Number

6.8.4.3 Voltage Control Output (VCO) ............................................................................ 6-13

6.8.4.4 Multiplication Factor Divider (MFD) ................................................................... 6-13

6.8.4.5 PLL Lock Detection ............................................................................................. 6-13

6.8.4.6 PLL Loss of Lock Conditions ............................................................................... 6-14

6.8.4.7 PLL Loss of Lock Reset ....................................................................................... 6-14

6.8.4.8 Loss of Clock Detection ....................................................................................... 6-15

6.8.4.9 Loss of Clock Reset .............................................................................................. 6-15

6.8.4.10 Alternate Clock Selection ..................................................................................... 6-15

6.8.4.11 Loss of Clock in Stop Mode ................................................................................. 6-16

Chapter 7

Power Management

7.1 Introduction ..................................................................................................................... 7-1

7.1.1 Features ....................................................................................................................... 7-1

7.2 Memory Map/Register Definition .................................................................................. 7-1

7.2.1 Peripheral Power Management Registers (PPMRH, PPMRL) ................................... 7-2

7.2.1.1 Peripheral Power Management Register Low (PPMRL) ....................................... 7-4

7.2.2 Low-Power Interrupt Control Register (LPICR) ........................................................ 7-5

7.2.3 Peripheral Power Management Set Register (PPMRS) .............................................. 7-7

7.2.4 Peripheral Power Management Clear Register (PPMRC) .......................................... 7-7

7.2.5 Low-Power Control Register (LPCR) ........................................................................ 7-8

7.3 IPS Bus Timeout Monitor ............................................................................................... 7-9

7.4 Functional Description .................................................................................................. 7-10

7.4.1 Low-Power Modes .................................................................................................... 7-10

7.4.1.1 Run Mode ............................................................................................................. 7-11

7.4.1.2 Wait Mode ............................................................................................................ 7-11

7.4.1.3 Doze Mode ............................................................................................................ 7-11

7.4.1.4 Stop Mode ............................................................................................................. 7-11

7.4.1.5 Peripheral Shut Down ........................................................................................... 7-11

7.4.2 Peripheral Behavior in Low-Power Modes .............................................................. 7-12

7.4.2.1 ColdFire Core ....................................................................................................... 7-12

7.4.2.2 Static Random-Access Memory (SRAM) ............................................................ 7-12

7.4.2.3 Flash ...................................................................................................................... 7-12

7.4.2.4 System Control Module (SCM) ............................................................................ 7-12

7.4.2.5 DMA Controller (DMA0–DMA3) ....................................................................... 7-12

7.4.2.6 UART Modules (UART0, UART1, and UART2) ............................................... 7-12

7.4.2.7 I2C Module ........................................................................................................... 7-13

7.4.2.8 Queued Serial Peripheral Interface (QSPI) ........................................................... 7-13

7.4.2.9 DMA Timers (DTIM0–DTIM3) ........................................................................... 7-13

7.4.2.10 Interrupt Controllers (INTC0, INTC1) ................................................................. 7-13

MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3

xFreescale Semiconductor

Contents

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Number

7.4.2.11 I/O Ports ................................................................................................................ 7-14

7.4.2.12 Reset Controller .................................................................................................... 7-14

7.4.2.13 Chip Configuration Module .................................................................................. 7-14

7.4.2.14 Clock Module ....................................................................................................... 7-14

7.4.2.15 Edge Port ..............................................................................................................7-15

7.4.2.16 Programmable Interrupt Timers (PIT0–PIT1) ..................................................... 7-15

7.4.2.17 FlexCAN ............................................................................................................... 7-15

7.4.2.18 PWM Module ....................................................................................................... 7-17

7.4.2.19 BDM ..................................................................................................................... 7-17

7.4.2.20 JTAG ..................................................................................................................... 7-17

7.4.3 Summary of Peripheral State During Low-Power Modes ........................................ 7-17

Chapter 8

Chip Configuration Module (CCM)

8.1 Introduction ..................................................................................................................... 8-1

8.1.1 Features ....................................................................................................................... 8-1

8.2 External Signal Descriptions .......................................................................................... 8-1

8.2.1 RCON ......................................................................................................................... 8-2

8.2.2 CLKMOD[1:0] ........................................................................................................... 8-2

8.2.3 JTAG_EN ...................................................................................................................8-2

8.2.4 TEST ........................................................................................................................... 8-2

8.3 Memory Map/Register Definition .................................................................................. 8-2

8.3.1 Programming Model ................................................................................................... 8-2

8.3.2 Memory Map .............................................................................................................. 8-3

8.3.3 Register Descriptions .................................................................................................. 8-3

8.3.3.1 Chip Configuration Register (CCR) ....................................................................... 8-3

8.3.3.2 Reset Configuration Register (RCON) ................................................................... 8-4

8.3.3.3 Chip Identification Register (CIR) ......................................................................... 8-4

Chapter 9

Reset Controller Module

9.1 Introduction ..................................................................................................................... 9-1

9.2 Features ........................................................................................................................... 9-1

9.3 Block Diagram ................................................................................................................ 9-1

9.4 Signals ............................................................................................................................. 9-2

9.4.1 RSTI ............................................................................................................................ 9-2

9.4.2 RSTO .......................................................................................................................... 9-2

9.5 Memory Map and Registers ............................................................................................ 9-2

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