DFI G586OPC/E Manual de usuario

G586OPC/E

Rev. 0 +

System Board

User’s Manual

-D28451207-

No part of this document may be copied, reproduced in

any form or by any means or used to make any trans-

formation/adaptation without the prior written consent

of DFI, Inc.

DFI, Inc. makes no warranties with respect to this

documentation and disclaims any implied warranties of

merchantability, quality, or fitness for any particular

purpose. The information in this document is subject to

change without notice. DFI, Inc. reserves the right to

make revisions to this publication and to make changes

to any and/or all parts of its content, at any time,

without obligation to notify any person or entity of such

changes. Further, DFI, Inc. assumes no responsibility

for any errors that may appear in this document.

DFI is a registered trademark, and G586OPC/E is a

trademark of Diamond Flower, Inc. All other product

names mentioned are trademarks or registered trade-

marks of their respective companies.

vFCC Statement on Class B

This equipment has been tested and found to comply

with the limits for a Class B digital device, pursuant to

Part 15 of the FCC rules. These limits are designed to

provide reasonable protection against harmful interfer-

ence when the equipment is operated in a residential

installation. This equipment generates, uses and can

radiate radio frequency energy and, if not installed and

used in accordance with the instruction manual, may

cause harmful interference to radio communications.

However, there is no guarantee that interference will

not occur in a particular installation. If this equipment

does cause harmful interference to radio or television

reception, which can be determined by turning the

equipment off and on, the user is encouraged to try to

correct the interference by one or more of the following

measures:

•Reorient or relocate the receiving antenna.

•Increase the separation between the equipment and

the receiver.

•Connect the equipment into an outlet on a circuit

different from that to which the receiver is

connected.

•Consult the dealer or an experienced radio TV

technician for help.

Notice:

1. The changes or modifications not expressly

approved by the party responsible for compliance

could void the user's authority to operate the

equipment.

2. Shielded interface cables must be used in order to

comply with the emission limits.

v Table of Contentsv

Introdution ................................................................................

Features and Specifications ................................................

Package Checklist ...............................................................

Installation Overview ...............................................................

Preparing the Area ..............................................................

Handling the System Board ................................................

Tips in Handling the System Board ....................................

Hardware Installation...........................................................

Memory Installation .......................................................

Installing theModules ....................................................

BoardConfiguration .......................................................

Jumper Settings for Display Type and

CMOS Clean .................................................................

Cache Configuration .....................................................

Installing Asynchronous SRAM .....................................

Jumper Settings for Cache Memory .............................

256KB Cache SRAM .............................................

512KB Cache SRAM .............................................

1MB Cache SRAM ................................................

Installing the Synchronous Cache Module ...................

Jumper Settings ............................................................

VRM Header .................................................................

VRM Header and 3.3V Pentium Processor ..................

VRM Header and Future Low-Voltage CPUs ...............

CPU Installation ............................................................

Jumper Settings for CPU ..............................................

Jumpers JP3, JP4, JP5,JP6, JP9, JP10, JP18, JP19,

JP20, JP21 and JP24 ...................................................

Installing Upgrade CPUs ..............................................

Built-in Ports ..................................................................

Serial Ports ............................................................

PS/2 Mouse Port ....................................................

Parallel Port ...........................................................

Floppy Disk Drive Connector ........................................

IDE Hard Disk Interface ................................................

Installing Expansion Cards ...........................................

Installing the System Board ..........................................

BIOS Setup Guide ...................................................................

Award BIOS CMOS Setup Utility ........................................

Standard CMOS Setup .......................................................

BIOS Features Setup ..........................................................

Chipset Features Setup .......................................................

Power Management Setup ..................................................

PCI Configuration Setup .....................................................

Load BIOS Default ..............................................................

Load Setup Default .............................................................

Password Setting ................................................................

IDE HDD Auto Detection .....................................................

Save and Exit Setup ...........................................................

Exit Without Saving .............................................................

Troubleshooting Checklist .....................................................

Appendix A:PCI I/O Pin Assignments ..................................

Appendix B:ISA I/O Pin Assignments ..................................

Appendix C:Connector Pin Assignments ............................

Appendix D:System Error Report .........................................

Appendix E:Award BIOS Hard Disk Table ...........................

G586OPC/E

Rev. 0 +

System Board

User’s Manual

G586OPC/E

Rev. 0 +

System Board

User’s Manual

-28451207-

G586OPC/E

Rev. 0 +

System Board

User’s Manual

G586OPC/E

vIntroduction

The G586OPC/E system board offers several advanced

features integrated into the system board. Its design is

based on the new Peripheral Component Interconnect

(PCI) local bus and Industry Standard Architecture

(ISA) standards.

The G586OPC provides a 321-pin Zero Insertion Force

(ZIF) CPU socket for PentiumTM processors running at

75MHz, 90MHz, 100MHz, 120MHz, 133MHz or

150MHz frequency. This ZIF socket allows users to

easily upgrade their CPUs. It also provides a VRM

(Voltage Regulation Module) header allowing you to

upgrade to future low-voltage CPUs.

The G586OPC/E is equipped with three PCI slots, three

ISA slots and one shared PCI/ISA slot.

The G586OPC/E board has two bus master PCI IDE

connectors. Bus mastering reduces CPU use during disk

transfer. The system board is also equipped with two

NS16C550A-compatible serial ports, an SPP/EPP/ECP

parallel port, a floppy disk drive controller, one PS/2

mouse port and one PS/2 keyboard connector.

The G586OPC/E can support 2MB to 128MB of

memory using 256Kx36, 512Kx36, 1Mx36, 2Mx36,

4Mx36 and 8Mx36 72-pin SIM modules.

PCI/ISASystemBoard

Product Specifications

Processor

•Intel Pentium™ processor 75/90/100/120/133/

150MHz

•Future Intel Pentium™ processor and Pentium™

OverDrive processor

Chipset

•OPTi Viper-M chipset

Cache Memory

•256KB, 512KB or 1MB direct map write-back or

write-through cache

•32Kx8, 64Kx8 or 128Kx8 asynchronous SRAM

(supports 5V/3.3V mixed voltage SRAM)

•160-pin SRAM upgrade slot for optional synchronous

pipeline burst cache module

System Memory

•Up to 128MB

•Four 72-pin DRAM SIMM sockets

•Supports single and/or double density SIMMs

•256Kx36, 512Kx36, 1Mx36, 4Mx36 or 8Mx36 parity

SIMMs x32 non-parity SIMMs supported

•Supports 60ns or 70ns fast page mode DRAM or

EDO DRAM

BIOS

•Award Plug and Play BIOS

•Supports Enhanced IDE devices

•Supports Enhanced IDE HDDs larger than 528MB

(LBA mode only)

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