Atmel AVR XMEGA D Series Manual de usuario

This document contains complete and detailed description of all modules included in

the Atmel®AVR®XMEGA®D microcontroller family. The Atmel AVR XMEGA D is a

family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcon-

trollers based on the AVR enhanced RISC architecture. The available Atmel AVR

XMEGA D modules described in this manual are:

•Atmel AVR CPU

•Memories

•Event system

•System clock and clock options

•Power management and sleep modes

•System control and reset

•WDT - Watchdog timer

•Interrupts and programmable multilevel interrupt controller

•PORT - I/O ports

•TC - 16-bit timer/counter

•AWeX - Advanced waveform extension

•Hi-Res - High resolution extension

•RTC - Real-time counter

•TWI - Two-wire serial interface

•SPI - Serial peripheral interface

•USART - Universal synchronous and asynchronous serial receiver and transmitter

•IRCOM - Infrared communication module

•CRC - Cyclic redundancy check

•ADC - Analog-to-digital converter

•AC - Analog comparator

•PDI - Program and debug interface

•Memory programming

•Peripheral address map

•Register summary

•Interrupt vector summary

•Instruction set summary

8210C- AVR-09/11

8-bit Atmel

XMEGA D

Microcontroller

XMEGA D

MANUAL

8210C–AVR–09/11

Atmel AVR XMEGA D

1. About the Manual

This document contains in-depth documentation of all peripherals and modules available for the

Atmel AVR XMEGA D microcontroller family. All features are documented on a functional level

and described in a general sense. All peripherals and modules described in this manual may not

be present in all Atmel AVR XMEGA D devices.

For all device-specific information such as characterization data, memory sizes, modules,

peripherals available and their absolute memory addresses, refer to the device datasheets.

When several instances of a peripheral exists in one device, each instance will have a unique

name. For example each port module (PORT) have unique name, such as PORTA, PORTB,etc.

For more details on applied use and code examples for peripherals and modules, refer to the

Atmel AVR XMEGA D specific application notes available from http://www.atmel.com/avr.

1.1 Reading the Manual

The main sections describe the various modules and peripherals. Each section contains a short

feature list and overview describing the module. The remaining section describes the features

and functions in more detail.

The register description sections list all registers and describe each register, bit and flag with

their function. This includes details on how to set up and enable various features in the module.

When multiple bits are needed for a configuration setting, these are grouped together in a bit

group. The possible bit group configurations are listed for all bit groups together with their asso-

ciated Group Configuration and a short description. The Group Configuration refers to the

defined configuration name used in the Atmel AVR XMEGA D and assembler header files and

application note source code.

The register summary sections list the internal register map for each module type.

The interrupt vector summary sections list the interrupt vectors and offset address for each mod-

ule type.

1.2 Resources

A comprehensive set of development tools, application notes, and datasheets are available for

download from http://www.atmel.com/avr.

1.3 Recommended Reading

• Atmel AVR XMEGA D device datasheets

• XMEGA application notes

This manual contains general modules and peripheral descriptions. The AVR XMEGA D device

datasheets contains the device-specific information. The XMEGA application notes and AVR

Software Framework contain example code and show applied use of the modules and peripher-

als.

For new users, it is recommended to read the AVR1000 - Getting Started Writing C Code for

Atmel XMEGA, and AVR1900 - Getting Started with Atmel ATxmega128A1 application notes.

8210C–AVR–09/11

Atmel AVR XMEGA D

2. Overview

The AVR XMEGA D microcontrollers is a family of low-power, high-performance, and peripheral-

rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By execut-

ing powerful instructions in a single clock cycle, the Atmel AVR XMEGA D devices achieve

throughputs approaching one million instructions per second (MIPS) per megahertz, allowing the

system designer to optimize power consumption versus processing speed.

The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32

registers are directly connected to the arithmetic logic unit (ALU), allowing two independent reg-

isters to be accessed in a single instruction, executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs many times faster than conven-

tional single-accumulator or CISC based microcontrollers.

The Atmel AVR XMEGA D devices provide the following features: in-system programmable

flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel event system

and programmable multilevel interrupt controller; up to 78 general purpose I/O lines; 16-bit real-

time counter (RTC); up to five flexible, 16-bit timer/counters with capture, compare and PWM

modes; up to four USARTs; up to two I2C and SMBUS compatible two-wire serial interfaces

(TWIs); up to two serial peripheral interfaces (SPIs); CRC module; one 8-channel, 12-bit ADCs

with programmable gain; up to two analog comparators with window mode; programmable

watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and pres-

caler; and programmable brown-out detection.

The program and debug interface (PDI), a fast, two-pin interface for programming and debug-

ging, is available.

The Atmel AVR XMEGA D devices have five software selectable power saving modes. The idle

mode stops the CPU while allowing the event system, interrupt controller, and all peripherals to

continue functioning. The power-down mode saves the SRAM and register contents, but stops

the oscillators, disabling all other functions until the next TWI, or pin-change interrupt, or reset.

In power-save mode, the asynchronous real-time counter continues to run, allowing the applica-

tion to maintain a timer base while the rest of the device is sleeping. In standby mode, the

external crystal oscillator keeps running while the rest of the device is sleeping. This allows very

fast startup from the external crystal, combined with low power consumption. In extended

standby mode, both the main oscillator and the asynchronous timer continue to run. To further

reduce power consumption, the peripheral clock to each individual peripheral can optionally be

stopped in active mode and idle sleep mode.

The devices are manufactured using Atmel high-density, nonvolatile memory technology. The

program flash memory can be reprogrammed in-system through the PDI interfaces. A boot

loader running in the device can use any interface to download the application program to the

flash memory. The boot loader software in the boot flash section will continue to run while the

application flash section is updated, providing true read-while-write operation. By combining an

8/16-bit RISC CPU with In-system, self-programmable flash, the AVR XMEGA D is a powerful

microcontroller family that provides a highly flexible and cost effective solution for many embed-

ded applications.

The Atmel AVR XMEGA D devices are supported with a full suite of program and system devel-

opment tools, including C compilers, macro assemblers, program debugger/simulators,

programmers, and evaluation kits.

8210C–AVR–09/11

Atmel AVR XMEGA D

2.1 Block Diagram

Figure 2-1. Atmel AVR XMEGA D block diagram.

Power

Supervision

POR/BOD &

RESET

PORT A (8)

PORT B (8)

EVENT ROUTING NETWORK

BUS

Matrix

SRAM

ADCA

ACA

OCD

PDI

PA[0..7]

PB[0..7]

Watchdog

Timer

Watchdog

Oscillator

Interrupt

Controller

DATA BUS

Prog/Debug

Controller

VCC

GND

PORT R (2)

XTAL1

XTAL2

PR[0..1]

TOSC1

TOSC2

PQ[0..7]

Oscillator

Circuits/

Clock

Generation

Oscillator

Control

Real Time

Counter

Event System

Controller

PDI_DATA

RESET/

PDI_CLK

Sleep

Controller

CRC

IRCOM

PORT Q (8)

PORT C (8)

PC[0..7]

TCC0:1

USARTC0

TWIC

SPIC

PD[0..7] PE[0..7] PF[0..7]

PORT D (8)

TCD0

USARTD0

SPID

TCF0

USARTF0

TCE0

USARTE0

TWIE

PORT E (8) PORT F (8)

EVENT ROUTING NETWORK

Int. Refs.

AREFA

AREFB

Tempref

VCC/10

CPU

NVM Controller

MORPEE

sal

DATA BUS

8210C–AVR–09/11

Atmel AVR XMEGA D

3. AVR CPU

3.1 Features

•8/16-bit, high-performance Atmel AVR RISC CPU

– 142 instructions

– Hardware multiplier

•32x8-bit registers directly connected to the ALU

•Stack in RAM

•Stack pointer accessible in I/O memory space

•Direct addressing of up to 16MB of program memory and 16MB of data memory

•True 16/24-bit access to 16/24-bit I/O registers

•Efficient support for 8-, 16-, and 32-bit arithmetic

•Configuration change protection of system-critical features

3.2 Overview

All AVR XMEGA AU devices use the 8/16-bit AVR CPU. The main function of the CPU is to exe-

cute the code and perform all calculations. The CPU is able to access memories, perform

calculations, control peripherals, and execute the program in the flash memory. Interrupt han-

dling is described in a separate section, ”Interrupts and Programmable Multilevel Interrupt

Controller” on page 101.

3.3 Architectural Overview

In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture

with separate memories and buses for program and data. Instructions in the program memory

are executed with single-level pipelining. While one instruction is being executed, the next

instruction is pre-fetched from the program memory. This enables instructions to be executed on

every clock cycle. For a summary of all AVR instructions, refer to ”Instruction Set Summary” on

page 317. For details of all AVR instructions, refer to http://www.atmel.com/avr.

Figure 3-1. Block diagram of the AVR CPU architecture.

8210C–AVR–09/11

Atmel AVR XMEGA D

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or

between a constant and a register. Single-register operations can also be executed in the ALU.

After an arithmetic operation, the status register is updated to reflect information about the result

of the operation.

The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose

working registers all have single clock cycle access time allowing single-cycle arithmetic logic

unit (ALU) operation between registers or between a register and an immediate. Six of the 32

registers can be used as three 16-bit address pointers for program and data space addressing,

enabling efficient address calculations.

The memory spaces are linear. The data memory space and the program memory space are

two different memory spaces.

The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the

EEPROM can be memory mapped in the data memory.

All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This

is referred to as the I/O memory space. The lowest 64 addresses can be accessed directly, or as

the data space locations from 0x00 to 0x3F. The rest is the extended I/O memory space, ranging

from 0x0040 to 0x0FFF. I/O registers here must be accessed as data space locations using load

(LD/LDS/LDD) and store (ST/STS/STD) instructions.

The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed

through the five different addressing modes supported in the AVR architecture. The first SRAM

address is 0x2000.

Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.

The program memory is divided in two sections, the application program section and the boot

program section. Both sections have dedicated lock bits for write and read/write protection. The

SPM instruction that is used for self-programming of the application flash memory must reside in

the boot program section. The application section contains an application table section with sep-

arate lock bits for write and read/write protection. The application table section can be used

forsave storing of nonvolatile data in the program memory.

3.4 ALU - Arithmetic Logic Unit

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or

between a constant and a register. Single-register operations can also be executed. The ALU

operates in direct connection with all 32 general purpose registers. In a single clock cycle, arith-

metic operations between general purpose registers or between a register and an immediate are

executed and the result is stored in the register file. After an arithmetic or logic operation, the

status register is updated to reflect information about the result of the operation.

ALU operations are divided into three main categories – arithmetic, logical, and bit functions.

Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementa-

tion of 32-bit aritmetic. The hardware multiplier supports signed and unsigned multiplication and

fractional format.

8210C–AVR–09/11

Atmel AVR XMEGA D

3.4.1 Hardware Multiplier

The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware mul-

tiplier supports different variations of signed and unsigned integer and fractional numbers:

• Multiplication of unsigned integers

• Multiplication of signed integers

• Multiplication of a signed integer with an unsigned integer

• Multiplication of unsigned fractional numbers

• Multiplication of signed fractional numbers

• Multiplication of a signed fractional number with an unsigned one

A multiplication takes two CPU clock cycles.

3.5 Program Flow

After reset, the CPU starts to execute instructions from the lowest address in the flash program-

memory ‘0.’ The program counter (PC) addresses the next instruction to be fetched.

Program flow is provided by conditional and unconditional jump and call instructions capable of

addressing the whole address space directly. Most AVR instructions use a 16-bit word format,

while a limited number use a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is

allocated in the general data SRAM, and consequently the stack size is only limited by the total

SRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highest

address in the internal SRAM. The SP is read/write accessible in the I/O memory space,

enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be

accessed through the five different addressing modes supported in the AVR CPU.

3.6 Instruction Execution Timing

The AVR CPU is clocked by the CPU clock, clkCPU. No internal clock division is used. Figure 3-2

on page 7 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access register file concept. This is the basic pipelining concept

used to obtain up to 1MIPS/MHz performance with high power efficiency.

Figure 3-2. The parallel instruction fetches and instruction executions.

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

8210C–AVR–09/11

Atmel AVR XMEGA D

Figure 3-3 on page 8 shows the internal timing concept for the register file. In a single clock

cycle, an ALU operation using two register operands is executed and the result is stored back to

the destination register.

Figure 3-3. Single Cycle ALU Operation

3.7 Status Register

The status register (SREG) contains information about the result of the most recently executed

arithmetic or logic instruction. This information can be used for altering program flow in order to

perform conditional operations. Note that the status register is updated after all ALU operations,

as specified in the instruction set reference. This will in many cases remove the need for using

the dedicated compare instructions, resulting in faster and more compact code.

The status register is not automatically stored when entering an interrupt routine nor restored

when returning from an interrupt. This must be handled by software.

The status register is accessible in the I/O memory space.

3.8 Stack and Stack Pointer

The stack is used for storing return addresses after interrupts and subroutine calls. It can also be

used for storing temporary data. The stack pointer (SP) register always points to the top of the

stack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Data

are pushed and popped from the stack using the PUSH and POP instructions. The stack grows

from a higher memory location to a lower memory location. This implies that pushing data onto

the stack decreases the SP, and popping data off the stack increases the SP. The SP is auto-

matically loaded after reset, and the initial value is the highest address of the internal SRAM. If

the SP is changed, it must be set to point above address 0x2000, and it must be defined before

any subroutine calls are executed or before interrupts are enabled.

During interrupts or subroutine calls, the return address is automatically pushed on the stack.

The return address can be two or three bytes, depending on program memory size of the device.

For devices with 128KB or less of program memory, the return address is two bytes, and hence

the stack pointer is decremented/incremented by two. For devices with more than 128KB of pro-

gram memory, the return address is three bytes, and hence the SP is decremented/incremented

by three. The return address is popped off the stack when returning from interrupts using the

RETI instruction, and from subroutine calls using the RET instruction.

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

8210C–AVR–09/11

Atmel AVR XMEGA D

The SP is decremented by one when data are pushed on the stack with the PUSH instruction,

and incremented by one when data is popped off the stack using the POP instruction.

To prevent corruption when updating the stack pointer from software, a write to SPL will auto-

matically disable interrupts for up to four instructions or until the next I/O memory write.

3.9 Register File

The register file consists of 32 x 8-bit general purpose working registers with single clock cycle

access time. The register file supports the following input/output schemes:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Six of the 32 registers can be used as three 16-bit address register pointers for data space

addressing, enabling efficient address calculations. One of these address pointers can also be

used as an address pointer for lookup tables in flash program memory.

Figure 3-4. AVR CPU general purpose working registers.

The register file is located in a separate address space, and so the registers are not accessible

as data memory.

3.9.1 The X-, Y-, and Z- Registers

Registers R26..R31 have added functions besides their general-purpose usage.

These registers can form 16-bit address pointers for addressing data memory. These three

address registers are called the X-register, Y-register, and Z-register. The Z-register can also be

used as an address pointer to read from and/or write to the flash program memory, signature

rows, fuses, and lock bits.

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

8210C–AVR–09/11

Atmel AVR XMEGA D

Figure 3-5. The X-, Y- and Z-registers.

The lowest register address holds the least-significant byte (LSB), and the highest register

address holds the most-significant byte (MSB). In the different addressing modes, these address

registers function as fixed displacement, automatic increment, and automatic decrement (see

the instruction set reference for details).

3.10 RAMP and Extended Indirect Registers

In order to access program memory above 64KB, the address pointer must be larger than 16

bits. This is done by concatenating one register to the Z-register. This register then holds the

most-significant byte (MSB) in a 24-bit address or address pointer.

These registers are available only on devices with external bus interface and/or more than 64KB

of program or data memory space. For these devices, only the number of bits required to

address the whole program and data memory space in the device is implemented in the

registers.

3.10.1 RAMPZ Registers

The RAMPZ registers are concatenated with the X-, Y-, and Z-registers, respectively, to enable

indirect addressing of the whole data memory space above 64KB and up to 16MB.

Figure 3-6. The combined RAMPZ + Z registers.

When reading (ELPM) and writing (SPM) program memory locations above the first 128KB of

the program memory, RAMPZ is concatenated with the Z-register to form the 24-bit address.

LPM is not affected by the RAMPZ setting.

3.10.2 EIND - Extended Indirect Register

EIND is concatenated with the Z-register to enable indirect jump and call to locations above the

first 128KB (64K words) of the program memory.

Figure 3-7. The combined EIND + Z register.

Bit (individually) 7R27 07 R26 0

X-register XH XL

Bit (X-register) 15 8 7 0

Bit (individually) 7R29 07 R28 0

Y-register YH YL

Bit (Y-register) 15 8 7 0

Bit (individually) 7R31 07 R30 0

Z-register ZH ZL

Bit (Z-register) 15 8 7 0

Bit (Individually) 7 0 7 0 7 0

RAMPZ ZH ZL

Bit (Z-pointer) 23 16 15 8 7 0

Bit (Individually) 7 0 7 0 7 0

EIND ZH ZL

Bit (D-pointer) 23 16 15 8 7 0

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