Atmel XMEGA A3 series Manual de usuario

Features

•High-performance, Low-power AVR 8/16-bit XMEGA Microcontroller

•Non-volatile Program and Data Memories

– 64K - 256K Bytes of In-System Self-Programmable Flash

– 4K - 8K Boot Code Section with Independent Lock Bits

– 2K - 4K Bytes EEPROM

– 4K - 16K Bytes Internal SRAM

External Bus Interface for up to 16M bytes SRAM

External Bus Interface for up to 128M Bytes SDRAM

•Peripheral Features

– Four-channel DMA Controller with support for external requests

– Eight-channel Event System

– Seven 16-bit Timer/Counters

Four Timer/Counters with 4 Output Compare or Input Capture channels

Three Timer/Counters with 2 Output Compare or Input Capture channels

High Resolution Extensions on all Timer/Counters

Advanced Waveform Extension on one Timer/Counter

– Seven USARTs

IrDA Extension on 1 USART

– AES and DES Crypto Engine

– Two Two-wire Interfaces with dual address match(I2C and SMBus compatible)

– Three SPI (Serial Peripheral Interfaces)

– 16-bit Real Time Counter with Separate Oscillator

– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters

– One Two-channel, 12-bit, 1 Msps Digital to Analog Converter

– Four Analog Comparators with Window compare function

– External Interrupts on all General Purpose I/O pins

– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal and External Clock Options with PLL

– Programmable Multi-level Interrupt Controller

– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby

– Advanced Programming, Test and Debugging Interfaces

JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming

PDI (Program and Debug Interface) for programming, test and debugging

•I/O and Packages

– 50 Programmable I/O Lines

– 64-lead TQFP

– 64-pad MLF

•Operating Voltage

– 1.6 – 3.6V

•Speed performance

– 0 – 12 MHz @ 1.6 – 3.6V

– 0 – 32 MHz @ 2.7 – 3.6V

Typical Applications

•Industrial control •Climate control •Hand-held battery applications

•Factory automation •ZigBee •Power tools

•Building control •Motor control •HVAC

•Board control •Networking •Metering

•White Goods •Optical •Medical Applications

8/16-bit

XMEGA A3

Microcontroller

ATxmega256A3

ATxmega192A3

ATxmega128A3

ATxmega64A3

Preliminary

8068C–AVR–06/08

XMEGA A3

1. Ordering Information

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

3. For packaging information, see ”Packaging information” on page 63.

2. Pinout/Block Diagram

Figure 2-1. Block diagram and TQFP-pinout.

Note: 1. For full details on pinout and alternate pin functions refer to ”Pinout and Pin Functions” on page 48.

Ordering Code Flash (B) E2(B) SRAM (B) Speed (MHz) Power Supply Package(1)(2)(3) Temp

ATxmega256A3-AU 256K + 8K 4K 16K 32 1.8 - 3.6V

64A

-40°- 85°C

ATxmega192A3-AU 192K + 8K 4K 16K 32 1.8 - 3.6V

ATxmega128A3-AU 128K + 8K 2K 8K 32 1.8 - 3.6V

ATxmega64A3-AU 64K + 4K 2K 4K 32 1.8 - 3.6V

ATxmega256A3-MU 256K + 8K 4K 16K 32 1.8 - 3.6V

64M1

ATxmega192A3-MU 192K + 8K 4K 16K 32 1.8 - 3.6V

ATxmega128A3-MU 128K + 8K 2K 8K 32 1.8 - 3.6V

ATxmega64A3-MU 64K + 4K 2K 4K 32 1.8 - 3.6V

Package Type

64A 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

64M1 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

INDEX CORNER

PF2

PF1

PF0

VCC

GND

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

VCC

GND

PD7

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

GND

VCC

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

GND

VCC

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PA2

PA1

PA0

AVCC

GND

PR1

PR0

RESET/PDI_CLK

PDI_DATA

PF7

PF6

VCC

GND

PF5

PF4

PF3

FLASH

RAM

PROM

DMA

Interrupt Controller

OCD

ADC A

ADC B

DAC B

AC A0

AC A1

AC B0

AC B1

Por t A

Por t B

Event System ctrl

Por t R

Power

Control

Reset

Control

Watchdog

OSC/CLK

Control BOD POR

RTC

EVENT ROUTING NETWORK

DATA BU S

VREF

TEMP

Port C Port D Port E Port F

CPU

T/C0:1

USART0:1

SPI

TWI

T/C0:1

USART0:1

SPI

T/C0:1

USART0:1

SPI

TWI

T/C0

USART0

8068C–AVR–06/08

XMEGA A3

3. Overview

The XMEGA A3 is a family of low power, high performance and peripheral rich CMOS 8/16-bit

microcontrollers based on the AVR®enhanced RISC architecture. By executing powerful

instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching 1 Million

Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power con-

sumption versus processing speed.

The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction, executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs many times faster than conven-

tional single-accumulator or CISC based microcontrollers.

The XMEGA A3 devices provide the following features: In-System Programmable Flash with

Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,

eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose

I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare

modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Periph-

eral Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional

differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators

with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate

internal oscillators with PLL and prescaler and programmable Brown-Out Detection.

The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,

is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this

can also be used for On-chip Debug and programming.

The XMEGA A3 devices have five software selectable power saving modes. The Idle mode

stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and

all peripherals to continue functioning. The Power-down mode saves the SRAM and register

contents but stops the oscillators, disabling all other functions until the next TWI or pin-change

interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,

allowing the application to maintain a timer base while the rest of the device is sleeping. In

Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is

sleeping. This allows very fast start-up from external crystal combined with low power consump-

tion. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue

to run. To further reduce power consumption, the peripheral clock for each individual peripheral

can optionally be stopped in Active mode and Idle sleep mode.

The device is manufactured using Atmel's high-density nonvolatile memory technology. The pro-

gram Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader

running in the device can use any interface to download the application program to the Flash

memory. The Bootloader software in the Boot Flash section will continue to run while the Appli-

cation Flash section is updated, providing true Read-While-Write operation. By combining an

8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3 is a power-

ful microcontroller family that provides a highly flexible and cost effective solution for many

embedded applications.

The XMEGA A3 devices are supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, programmers,

and evaluation kits.

8068C–AVR–06/08

XMEGA A3

3.1 Block Diagram

Figure 3-1. XMEGA A3 Block Diagram

PE[0..6]

PORT E (8)

TCE0:1

USARTE0:1

TWIE

SPIE

TCF0

USARTF0

PORT F (8)

Power

Supervision

POR/BOD &

RESET

PORT A (8)

PORT B (8)

DMA

Controller

BUS

Controller

SRAM

ADCA

ACA

DACB

ADCB

ACB

OCD

Internal

Reference

PDI

CPU

PA[0..7]

PB[0..7]/

JTAG

Watchdog

Timer

Watchdog

Oscillator

Interrupt

Controller

DATA BUS

Prog/Debug

Controller

VCC

GND

Oscillator

Circuits/

Clock

Generation

Oscillator

Control

Real Time

Counter

Event System

Controller

JTAG

AREFA

AREFB

PDI_DATA

RESET/

PDI_CLK

PORT B

Sleep

Controller

Flash EEPROM

NVM Controller

DES

AES

IRCOM

PORT C (8)

PC[0..7]

TCC0:1

USARTC0:1

TWIC

SPIC

PD[0..7]

PORT R (2)

XTAL1

XTAL2

PR[0..1]

PORT D (8)

TCD0:1

USARTD0:1

SPID

TOSC1

TOSC2

EVENT ROUTING NETWORK

PF[0..7]

To Clock

Generator

8068C–AVR–06/08

XMEGA A3

4. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

4.1 Recommended reading

• XMEGA A Manual

• XMEGA A Application Notes

This device data sheet only contains part specific information and a short description of each

peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth.

The XMEGA A application notes contain example code and show applied use of the modules

and peripherals.

The XMEGA A Manual and Application Notes are available from http://www.atmel.com/avr.

5. Disclaimer

For devices that are not available yet, typical values contained in this datasheet are based on

simulations and characterization of other AVR XMEGA microcontrollers manufactured on the

same process technology. Min. and Max values will be available after the device is

characterized.

8068C–AVR–06/08

XMEGA A3

6. AVR CPU

6.1 Features

•8/16-bit high performance AVR RISC Architecture

– 138 instructions

– Hardware multiplier

•32x8-bit registers directly connected to the ALU

•Stack in RAM

•Stack Pointer accessible in I/O memory space

•Direct addressing of up to 16M bytes of program and data memory

•True 16/24-bit access to 16/24-bit I/O registers

•Support for 8-, 16- and 32-bit Arithmetic

•Configuration Change Protection of system critical features

6.2 Overview

The XMEGA A3 uses an 8/16-bit AVR CPU. The main function of the AVR CPU is to ensure cor-

rect program execution. The CPU must therefore be able to access memories, perform

calculations and control peripherals. Interrupt handling is described in a separate section. Figure

6-1 on page 6 shows the CPU block diagram.

Figure 6-1. CPU block diagram

The AVR uses a Harvard architecture - with separate memories and buses for program and

data. Instructions in the program memory are executed with a single level pipeline. While one

instruction is being executed, the next instruction is pre-fetched from the program memory.

Flash

Program

Memory

Instruction

Decode

Program

Counter

OCD

32 x 8 General

Purpose

Registers

ALU Multiplier/

DES

Instruction

STATUS/

CONTROL

Peripheral

Module 1 Peripheral

Module 2 EEPROM PMICSRAM

DATA BUS

8068C–AVR–06/08

XMEGA A3

This concept enables instructions to be executed in every clock cycle. The program memory is

In-System Re-programmable Flash memory.

6.3 Register File

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File - in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing - enabling efficient address calculations. One of these address pointers can

also be used as an address pointer for look up tables in Flash program memory.

6.4 ALU - Arithmetic Logic Unit

The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations

between registers or between a constant and a register. Single register operations can also be

executed. Within a single clock cycle, arithmetic operations between general purpose registers

or between a register and an immediate are executed. After an arithmetic or logic operation, the

Status Register is updated to reflect information about the result of the operation.

The ALU operations are divided into three main categories – arithmetic, logical, and bit-func-

tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy

implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both

signed and unsigned multiplication and fractional format.

6.5 Program Flow

When the device is powered on, the CPU starts to execute instructions from the lowest address

in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to

be fetched. After a reset, the PC is set to location ‘0’.

Program flow is provided by conditional and unconditional jump and call instructions, capable of

addressing the whole address space directly. Most AVR instructions use a 16-bit word format,

while a limited number uses a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack

is effectively allocated in the general data SRAM, and consequently the Stack size is only limited

by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to

the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory

space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can

easily be accessed through the five different addressing modes supported in the AVR CPU.

8068C–AVR–06/08

XMEGA A3

7. Memories

7.1 Features

•Flash Program Memory

– One linear address space

– In-System programmable

– Self-Programming and Bootloader support

– Application Section for application code

– Application Table Section for application code or data storage

– Boot Section for application code or bootloader code

– Separate lock bits and protection for all sections

•Data Memory

– One linear address space

– Single cycle access from CPU

– SRAM

– EEPROM

Byte or page accessible

Optional memory mapping for direct load and store

– I/O Memory

Configuration and Status register for all peripherals and modules

16-bit accessible General Purpose Register for global variables or flags

– External Memory support

– Bus arbitration

Safe and deterministic handling of CPU and DMA Controller priority

– Separate buses for SRAM, EEPROM, I/O Memory and External Memory access

Simultaneous bus access for CPU and DMA Controller

•Calibration Row Memory for factory programmed data

Oscillator calibration bytes

Serial number

Device ID for each device type

•User Signature Row

One flash page in size

Can be read and written from software

Data is kept after Chip Erase

7.2 Overview

The AVR architecture has two main memory spaces, the Program Memory and the Data Mem-

ory. In addition, the XMEGA A3 features an EEPROM Memory for non-volatile data storage. All

three memory spaces are linear and require no paging. The available memory size configura-

tions are shown in ”Ordering Information” on page 2. In addition each device has a Flash

memory signature row for calibration data, device identification, serial number etc.

Non-volatile memory spaces can be locked for further write or read/write operations. This pre-

vents unrestricted access to the application software.

8068C–AVR–06/08

XMEGA A3

7.3 In-System Programmable Flash Program Memory

The XMEGA A3 devices contains On-chip In-System Programmable Flash memory for program

storage, see Figure 7-1 on page 9. Since all AVR instructions are 16- or 32-bits wide, each Flash

address location is 16 bits.

The Program Flash memory space is divided into Application and Boot sections. Both sections

have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Pro-

gram Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash

memory.

A third section inside the Application section is referred to as the Application Table section which

has separate Lock bits for storage of write or read/write protection. The Application Table sec-

tion can be used for storing non-volatile data or application software.

The Application Table Section and Boot Section can also be used for general application

software.

Figure 7-1. Flash Program Memory (Hexadecimal address)

Word Address

0Application Section

(256K/192K/128K/64K)

...

1EFFF / 16FFF / EFFF / 77FF

1F000 / 17000 / F000 / 7800 Application Table Section

(8K/8K/8K/4K)

1FFFF / 17FFF / FFFF / 7FFF

20000 / 18000 / 10000 / 8000 Boot Section

(8K/8K/8K/4K)

20FFF / 18FFF / 10FFF / 87FF

8068C–AVR–06/08

XMEGA A3

7.4 Data Memory

The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one lin-

ear address space, see Figure 7-2 on page 10. To simplify development, the memory map for all

devices in the family is identical and with empty, reserved memory space for smaller devices.

Figure 7-2. Data Memory Map (Hexadecimal address)

Byte Address ATxmega192A3 Byte Address ATxmega128A3 Byte Address ATxmega64A3

0I/O Registers

(4KB)

0I/O Registers

(4KB)

0I/O Registers

(4KB)

FFF FFF FFF

1000

EEPROM

(4K)

1000 EEPROM

(2K)

1000 EEPROM

(2K)

17FF 17FF

1FFF RESERVED RESERVED

2000 Internal SRAM

(16K)

2000 Internal SRAM

(8K)

2000 Internal SRAM

(4K)

5FFF 3FFF 2FFF

6000 External Memory

(0 - 16 MB)

4000 External Memory

(0 - 16 MB)

3000 External Memory

(0 - 16 MB)

FFFFFF FFFFFF FFFFFF

Byte Address ATxmega256A3

0I/O Registers

(4KB)

FFF

1000

EEPROM

(4K)

1FFF

2000 Internal SRAM

(16K)

5FFF

6000 External Memory

(0 - 16 MB)

FFFFFF

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