Atmel AT40K Instrucciones de instalación y funcionamiento

AT40K Series Configuration

Configuration is the process by which a design is loaded into an AT40K series field

programmable gate array (FPGA). AT40K series devices are SRAM based and can be

configured any number of times. The entire device or select portions can be config-

ured. Sections can be configured while others continue to operate undisturbed. Full

configuration takes only milliseconds. Partial configuration takes even less time and is

a function of design density.

Configuration data is transferred to the device in one of six modes, see Table 1. Three

dedicated input pins, M0,M

1,andM

2, determine the configuration mode. There is one

auto-configuring Master Mode, four Slave modes, and a Synchronous RAM Mode for

accessing the SRAM-based configuration memory directly from a parallel micropro-

cessor port.

Configuration States

There are four basic configuration states of operation. The first, power-on-reset,

occurs when power is first applied to the part. The FPGA initiates a complete clearing

of all internal configuration SRAM (configuration clear cycle).

The second, manual reset, occurs when the RESET pin is driven Low by the user.

Again, the FPGA initiates a configuration clear cycle.

The third is configuration download. In this state the configuration mode is active. The

FPGA accepts serial or parallel data from an outside source and configures the con-

figuration SRAM appropriately.

The fourth is idle, when there is no configuration activity.

Table 1. AT40K Series Configuration Modes

Mode Description M2M1M0CCLK Data Notes

0 Master Serial 0 0 0 Output Serial Auto-Configuration,

Serial EEPROM

1 SlaveSerial 001InputSerial Microprocessoror

Serial EEPROM

7 SlaveSerial 111InputSerial Microprocessoror

Serial EEPROM

2 SlaveParallel 010Input8-or16-bit

Word

Microprocessor or

Parallel EEPROM

6 SlaveParallelUP110Input8-or16-bit

Word

20-bit Address Out,

Parallel EPROM

4 Synchronous

RAM

100Input8-or16-bit

Word

24-bit Address In,

Parallel Port of

Microprocessor

AT40K FPGA

Application

Note

Rev. 1009B–FPGA–03/02

2AT40K Series Configuration

1009B–FPGA–03/02

Master Mode The Master Mode is auto-configuring; that is, after power-on-reset (POR) and the clear-

ing of configuration memory, it self-initiates configuration. The Master Mode uses an

internal oscillator to provide CCLK for clocking the external EEPROMs (configurators)

which contain the configuration data. CCLK also drives the downstream devices

(Slaves) in the configuration cascade chain. Master Serial Mode clocks and receives

data from an EEPROM Serial Configuration Memory (AT17C65, AT17C128, AT17C256,

AT17C512, AT17C010). After auto-configuration is complete, re-configuration can be

initiated manually by the user.

Slave Modes In slave modes, configuration is always initiated by an external signal. Data is applied to

the device on the rising edge of CCLK. In Slave Serial Mode, the device receives serial

configuration data. In Slave Parallel Mode, the device receives either 8-bit wide or 16-bit

wide parallel data. In Slave Parallel Up Mode, the device receives either 8-bit or 16-bit

wide parallel data and generates a 20-bit address up counter for use in addressing

memories. CCLK is not generated in slave modes.

Synchronous RAM Mode In Synchronous RAM Mode, the device receives a 32- or 40-bit wide bitstream com-

posed of a 24-bit address and either an 8-bit wide or 16-bit wide word of data. Address,

data and write enable are applied simultaneously at the rising edge of CCLK. In this

mode, designed to interface to a generic IO port of a microprocessor, the FPGA config-

uration SRAM is seen as a simple memory-mapped address space. The user has full

read and write access to the entire FPGA configuration SRAM. The overhead normally

associated with bitstreams is eliminated, resulting in faster re-configuration.

Configuration Pins During configuration, the flow of design data to and from the device is controlled by the

dedicated mode pins and a number of dual-function pins that double as user I/O under

normal programmed operation. The number of dual-function pins required for each

mode varies, see Table 2.

AT40K Series Configuration

1009B–FPGA–03/02

Table 2. Configuration Pins Interface Definition

Pins

State

Reset

Download

Mode 0

Download

Mode 1

Download

Mode 7

Download

Mode 2

Download

Mode 6

Download

Mode 4 Idle

(2:0)

TTL Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL Input

RESET TTL Input,

50K Pull-up

TTL Input,

50K Pull-up

TTL Input,

50K Pull-up

TTL Input,

50K Pull-up

TTL Input,

50K Pull-up

TTL Input,

50K Pull-up

TTL Input,

50K Pull-up

TTL Input,

50K Pull-up

INIT

Open Drain

Bi-directional,

20K Pull-up

Open Drain

Bi-directional,

20K Pull-up

Open Drain

Bi-directional,

20K Pull-up

Open Drain

Bi-directional,

20K Pull-up

Open Drain

Bi-directional,

20K Pull-up

Open Drain

Bi-directional,

20K Pull-up

Open Drain

Bi-directional,

20K Pull-up

User I/O

CON

Open Drain

Bi-directional,

10K Pull-up

Open Drain

Bi-directional,

10K Pull-up

Open Drain

Bi-directional,

10K Pull-up

Open Drain

Bi-directional,

10K Pull-up

Open Drain

Bi-directional,

10K Pull-up

Open Drain

Bi-directional,

10K Pull-up

Open Drain

Bi-directional,

10K Pull-up

Open Drain

Bi-directional,

10K Pull-up

CCLK

Schmitt

Trigger Input,

50K Pull-up

Output

Schmitt

Trigger Input,

50K Pull-up

Schmitt

Trigger Input,

50K Pull-up

Schmitt

Trigger Input,

50K Pull-up

Schmitt

Trigger Input,

50K Pull-up

Schmitt

Trigger Input,

50K Pull-up

Schmitt

Trigger Input,

50K Pull-up

HDC Output Output Output Output Output Output User I/O User I/O

LDC Output Output Output Output Output Output User I/O User I/O

CMOS

Input, 20K

Pull-up

Input Input Input Input Input Bi-directional User I/O

(7:1)

CMOS

Input, 20K

Pull-up

User I/O User I/O User I/O Input Input Bi-directional User I/O

(15:8)

CMOS

Input, 20K

Pull-up

User I/O User I/O User I/O Optional Input Optional Input Optional

Bi-directional User I/O

(19:0)

CMOS

Input, 20K

Pull-up

User I/O User I/O User I/O User I/O Output Input User I/O

(23:20)

CMOS

Input, 20K

Pull-up

User I/O User I/O User I/O User I/O User I/O Input User I/O

CS0

CMOS

Input, 20K

Pull-up

User I/O Input User I/O User I/O User I/O Input User I/O

CS1

CMOS

Input, 20K

Pull-up

User I/O User I/O User I/O Input User I/O User I/O User I/O

CSOUT

CMOS

Input, 20K

Pull-up

Optional Output Optional

Output

Optional

Output

Optional

Output

Optional

Output User I/O User I/O

CHECK

CMOS

Input, 20K

Pull-up

Check Input

or User I/O

Check Input

or User I/O

Check Input

or User I/O

Check Input

or User I/O

Check Input

or User I/O

Check Input

or User I/O User I/O

OTS

CMOS

Input, 20K

Pull-up

OTS Input

or User I/O

OTS Input

or User I/O

OTS Input

or User I/O

OTS Input

or User I/O

OTS Input

or User I/O

OTS Input

or User I/O

OTS Input

or User I/O

4AT40K Series Configuration

1009B–FPGA–03/02

M0,M

1,M

2The mode pins are dedicated TTL threshold inputs that determine the configuration

mode to be used. Table 1 lists the states for each configuration mode. The mode pins

should not be changed during power-on-reset, manual reset, or configuration download.

The user may change the mode pins during configuration idle. These pins have no pull-

up resistors to VDD, so they need to be driven by the user or tied off.

CCLK CCLK is the configuration clock pin. It is an input or output depending on the mode of

operation. During power-on-reset or manual reset, it is a tri-stated output. During config-

uration download and in Mode 0, it is an output with a typical frequency of 1 MHz. During

configuration download and in all other modes, it is a Schmitt trigger input with approxi-

mately 1V of hysteresis for noise immunity. It is an input during configuration idle, but is

ignored. It is pulled to VDD with a nominal 50K internal resistor.

RESET RESET is the FPGA configuration manual reset pin. It is available during all configura-

tion states. It initiates a configuration clear cycle and, if operating in Mode 0, an auto-

configuration. It is a dedicated Schmitt trigger input with approximately 1V of hysteresis

for noise immunity. It is pulled to VDD with a nominal 50K internal resistor.

INIT INIT is a multi-function pin. During power-on-reset and manual reset, the pin functions

as an open drain bi-directional I/O which releases High when the configuration clear

cycle is complete, but can be held Low to hold the configuration in a reset state. Once

released, the FPGA will proceed to either configuration download or idle, as appropriate.

During configuration download, the INIT pin is again an open drain bi-directional pin

which signals if an error is encountered during the download of a configuration bit-

stream. In addition, during the Check Function, the INIT pin drives Low for any

configuration SRAM mismatch (see the description of the Check Function on page 16

for more details). While in open drain mode, the pin is pulled to VDD with a nominal 20K

internal resistor. When not configuring, the INIT pin becomes a fully functional user I/O.

CON CON is the FPGA configuration start and status pin. It is a dedicated open drain bi-direc-

tional pin. During power-on-reset or manual reset, CON is driven Low by the FPGA. In

Modes 2, 6, or 7, when the FPGA has finished the configuration clear cycle, CON is

released to indicate the device is ready for the user to initiate configuration download.

The user may then drive CON Low to initiate a configuration download. After three clock

cycles, CON is then driven Low by the FPGA until it finishes the download, and it is then

released. In Mode 0, CON is not released by the FPGA at the end of power-on-reset or

manual reset. Instead, CON is controlled by the FPGA until the end of the auto-configu-

ration process. CON is released at the end of configuration download in Mode 0, and the

user may then initiate a manual configuration download by driving CON Low. While in

open drain mode, the pin is pulled to VDD with a nominal 10K internal resistor.

HDC HDC(1) is the FPGA “High During Configuration” pin. It is an output, driven High by the

FPGA during power-on-reset, manual reset, and configuration download. During config-

uration idle, the pin is a fully functional user I/O.

Note: 1. All user I/O default to inputs with pull-ups “on”. The HDC pin transitions from driving a

strong “1” to a pull-up “1” after reset. The HDC pin will transition from driving a strong

“1” to the user programmed state at the end of configuration download. If not pro-

grammed, the default state is input with pull-up.

AT40K Series Configuration

1009B–FPGA–03/02

LDC LDC is the FPGA “Low During Configuration” pin. It is an output driven Low by the

FPGA during power-on-reset, manual reset, and configuration download. During config-

uration idle, the pin is a fully functional user I/O.

Note: All user I/O pull-ups and put-downs are programmed by the user. The LDC pin transitions

from driving a strong “0” to a weak “1” after reset. The LDC pin will transition from driving

a strong “0” to the user programmed state at the end of configuration download. If not

programmed, the default state is input with pull-up.

D0D0is the lsb of the FPGA configuration data bus used to download configuration data to

the device. During power-on-reset or manual reset, D0is controlled by the configuration

SRAM. The D0pin will transition from the user programmed state to a CMOS input with

a nominal 20K internal pull-up resistor as the SRAM at that location is cleared by the

configuration clear cycle. D0becomes an input during configuration download.

D1:D7D1:D7are the upper 7 bits of the 8-bit parallel data bus used to download configuration

data to the device. During power-on-reset or manual reset, D1:D7are controlled by the

configuration SRAM. The D1:D7pins will transition from the user programmed state to

CMOS inputs with nominal 20K internal pull-up resistors as the SRAM at those locations

is cleared by the configuration clear cycle. When in Modes 2 or 6, D1:D7become inputs

during configuration download. D1:D7are not used in the serial Modes 0, 1 and 7.

D8:D15 D8:D15 are the upper 8 bits of the 16-bit parallel wide data bus used to download config-

uration data to the device. During power-on-reset or manual reset, D8:D15 are controlled

by the configuration SRAM. The D8:D15 pins will transition from the user programmed

state to CMOS inputs with nominal 20K internal pull-up resistors as the SRAM at those

locations is cleared by the configuration clear cycle. When in Modes 2 or 6, D8:D15

become optional inputs during configuration download. They become available as soon

as the appropriate bit in the configuration control register is set. D8:D15 are not used in

the serial Modes 0, 1 and 7.

A0:A19 A0:A19(1) are used to control external addressing of memories during downloads. During

power-on-reset or manual reset, A0:A19 are controlled by the configuration SRAM. The

A0:A19 pins will transition from the user programmed state to CMOS inputs with nominal

20K internal pull-up resistors as the SRAM at those locations is cleared by the configu-

ration clear cycle. When in Mode 6, A0:A19 become outputs during configuration

download. A0:A19 are used only in Mode 6.

Note: 1. Pin A2is also pin CS1, which is available only for Mode 2. See the description for CS1

on page 5 for more details.

CS0CS0is an FPGA configuration chip select. It is active Low. During power-on-reset or

manual reset, CS0is controlled by the configuration SRAM. The CS0pin will transition

from the user programmed state to a CMOS input with a nominal 20K internal pull-up

resistor as the SRAM at that location is cleared by the configuration clear cycle. In Mode

1, it is used as a chip select to enable configuration to begin. It is most often used as the

chip select of the downstream device in a cascade chain, and is usually driven by

CSOUT of the upstream device. Releasing CS0during configuration causes the Mode 1

FPGA to abort the download and release CON. CS0is used only in Mode 1.

CS1CS1(1) is an FPGA configuration chip select. It is active Low. During power-on-reset or

manual reset, CS1is controlled by the configuration SRAM. The CS1pin will transition

from the user programmed state to a CMOS input with a nominal 20K internal pull-up

6AT40K Series Configuration

1009B–FPGA–03/02

resistor as the SRAM at that location is cleared by the configuration clear cycle. In Mode

2, it is used as a chip select to enable configuration to begin. It is most often used as the

chip select of the downstream device in a cascade chain, and is usually driven by

CSOUT of the upstream device. Releasing CS1during configuration causes the Mode 2

FPGA to abort the download and release CON. CS1is used only in Mode 2.

Note: 1. Pin CS1is also pin A2, which is active only for Mode 6. See the description for A0:A19,

on page 5 for more details.

CSOUT CSOUT is the configuration pin used to enable the downstream device in a cascade

chain. During power-on-reset or manual reset, CSOUT is controlled by the configuration

SRAM. The CSOUT pin will transition from the user programmed state to a CMOS input

with a nominal 20K internal pull-up resistor as the SRAM at that location is cleared by

the configuration clear cycle. During configuration download, CSOUT becomes an

optional output. It is enabled by default after reset, and may be enabled or disabled via

the configuration control register. If the user has disabled the cascade function, the pin

remains a user I/O. If the cascade function is enabled, the CSOUT pin is driven High at

the start of configuration download. At the end of the device’s portion of the cascade bit-

stream, the CSOUT pin is driven Low (and into the CS0or CS1of the downstream

device) to enable the downstream device. CSOUT is released by the device at the end

of the cascade bitstream and becomes a fully functional user I/O.

CHECK CHECK is a configuration control pin used to control the Check Function. The Check

Function takes a bitstream and compares it to the contents of a previously loaded bit-

stream and notifies the user of any differences. Any differences causes the INIT pin to

go Low. During power-on-reset or manual reset, CHECK is controlled by the configura-

tion SRAM. The CHECK pin will transition from the user programmed state to a CMOS

input with a nominal 20K internal pull-up resistor as the SRAM at that location is cleared

by the configuration clear cycle. During configuration download, CHECK becomes an

optional input. It is enabled by default after reset, and may be enabled or disabled via

the configuration control register. If the user has disabled the Check Function, the pin

remains a user I/O.

OTS OTS is an input pin used to immediately tri-state all user I/O. It is enabled by a bit in the

configuration control register. Once activated, it is always an input. The OTS tri-state

control of Dual-use pins is superseded by the configuration logic’s claim on those pins. If

the user has disabled the OTS function, the pin remains as User I/O.

Dual-use I/O Any pin which functions as user I/O and configuration I/O is a dual-use I/O pin. INIT,

HDC, LDC, D0:D15,A

0:A19,CS

0,CS

1, CSOUT, CHECK, and OTS are all dual-use I/O

pins. It must be noted that while the configuration logic controls dual-use I/O pins during

a particular mode of operation, the configuration logic does not control the pull-up, pull-

down, CMOS/TTL threshold select, or Schmitt trigger selects. The user must be cau-

tioned to avoid possible system problems with the use of dual-use I/O pins. For

example, turning off the internal pull-up resistor for the open drain INIT pin would not

apply the weak High required of an open drain driver. Conversely, disabling the pull-up

and enabling the pull-down of the HDC pin might be a good idea, since the user may

then actually see the pin go Low at the end of configuration.

Dual-use pins share input buffers. It should be noted that even when the configuration

has claimed a pin for its own purposes, the user input buffer is still fully functional. This

implies that any user logic tied to the input buffers of the pins in question will remain

operational, see Figure 1.

AT40K Series Configuration

1009B–FPGA–03/02

Figure 1. Dual-use IO

Configuration States When power is first applied to an AT40K series FPGA, an internal power-on-reset circuit

senses VDD and activates at approximately 2.1V. The FPGA then enters the power-on-

reset state. During this state, INIT is driven Low, CON is driven Low, LDC is driven Low,

HDC is driven High, and all user I/O are tri-stated. I/O thresholds, pull-ups and put-

downs are at an indeterminate state. The FPGA configuration clear cycle begins and the

configuration SRAM is reset. The configuration clear cycle is repeated a nominal 150 ms

to allow VDD to rise to the minimum operational level for the device (3.0V).

This additional delay is only applied at power-on-reset, and is not needed for manual

reset.

Once the configuration clear cycle is complete, RESET is sampled. If High, INIT is

released. This open drain pin is sampled to make sure all other devices (if any) in a cas-

cade chain are also done with the configuration clear cycle. Once INIT goes High the

mode pins are sampled.

If Mode 0 is detected, the part proceeds to the configuration download state. CON is

held Low by the FPGA, HDC remains High, LDC remains Low, and CCLK is now driven

by the FPGA at a nominal frequency of approximately 1 MHz. The appropriate configu-

ration interface pins for Mode 0 become active.

If a slave mode is detected (i.e., Modes 1, 2, 6, or 7), then CON is released and pulled

High with the internal pull-up resistor. Once CON goes High, the part proceeds to the

idle state and LDC and HDC are released. The internal oscillator stops running. The part

is now available for configuration download.

When RESET is lowered, the manual reset state is entered. An internal oscillator begins

running, INIT, CON and LDC are driven Low, and HDC is driven High. During this state,

the FPGA configuration clear cycle begins and the configuration SRAM is reset. Once

this cycle is complete, RESET is sampled and the reset state machine proceeds as

above. The configuration reset state diagram is shown in Figure 2

To user logic

To configuration logic

From user logic

From Configuration

Configuration claim

From user logic

From configuration

8AT40K Series Configuration

1009B–FPGA–03/02

After a configuration clear cycle, the user logic of the FPGA is set to a benign state, see

Table 4.

There is no activity in either the user logic or the configuration logic and the device is in

a low power state.

Table 3. Configuration Clear Cycle Times

Device Array Size

Clear Cycle Time

UnitsMin Typ Max

AT40K05 16 x 16 137 228 365 µs

AT40K10 24 x 24 197 328 525 µs

AT40K20 32 x 32 257 428 685 µs

AT40K30 40 x 40 317 528 845 µs

AT40K40 48 x 48 377 628 1005 µs

Table 4. User Circuitry and Default States

User Circuitry Default State

Core Inputs tied off

Local drivers off

DFF set

Repeater All drivers off

Passgates off

I/O Output drivers off

CMOS threshold

Pull-up enabled

Pull-down disabled

Clocks Tied High

Resets Tied Low (active)

RAM Disabled

Contents cleared

AT40K Series Configuration

1009B–FPGA–03/02

Figure 2. Configuration Reset State Diagram

The AT40K FPGA allows complete re-configurability down to the byte level. The

CacheLogic®architecture lets users reconfigure part of the FPGA while the rest of the

FPGA continues to operate unaffected.

Control of the FPGA system level interface is possible on an AT40K series FPGA. User

I/O, internal Global Set/Reset, and Global and Fast Clocks can be enabled or disabled

during configuration downloads by setting bits in the control register.

User I/O become active as soon as the relevant I/O configuration SRAM is loaded. To

aid system level integration, a bit in the control register (CR31) may be set which com-

mands all I/O pins not part of the configuration interface to go tri-stated. This bit is set at

the start of configuration so the very first download can be affected.

Another bit in the control register (CR30) may be set to enable (drive Low) the global

reset net during configuration download.

Another set of bits in the control register (CR27:CR16) may be set to disable (drive High)

each of the global and fast clock input buffers which drive the global clock nets. The

user I/O portion of these buffers is not affected.

Configuration Idle

Configuration

Clear Cycle

RESET

= Low ?

RESET

= High?

Yes

Release INIT Errn

RESET

= Low ?

Yes

INIT

= High?

Yes

Sample Mode Pins

RESET

= Low ?

Yes

Device

= Master ?

Yes

Configuration Download

Yes

(Power-on-Reset) VDD

> 2.1V No

Manual Reset

Yes

10 AT40K Series Configuration

1009B–FPGA–03/02

Holding off

Auto-Configuration

There are two methods by which the user may delay a master Mode 0 auto-configura-

tion. The first is to drive RESET Low during power-on-reset or manual reset and hold the

signal Low until the user is ready to proceed with auto-configuration. The second is to

drive INIT Low with an open drain driver during power-on-reset or manual reset, and

release when the user is ready to proceed with auto-configuration. Both are valid in a

AT40K series device. Assuming the device has completed its configuration clear cycle

and that INIT and RESET are inactive (High), a Mode 0 FPGA starts CCLK and configu-

ration download.

Configuration

Control Register

The AT40K series devices have a 32-bit control register that is written at the beginning

of a configuration download. These bits control various configuration sequence parame-

ters. All bits are set to 0 during a configuration clear cycle. In parallel modes, byte 0 is

loaded first. In serial modes, bit-31 is loaded first. The control register settings are made

in the FPGA Designer IDS Software Options section

•Go to the Options menu on the IDS (Figaro) main window and select Options.

•Choose AT40K Bitstream from the topics list(1).

Note: 1. IDS uses names "B0" ~ "B31" for "CR0" ~ "CR31" for the Control Register.

CR0:0 = Reset Address Counter

1 = Retain Address Counter

CR0controls the value of the Mode 6 device’s memory address counter after each con-

figuration sequence. The default resets the address up-counter to 000000 after each

configuration download is completed. When this bit is set, the memory address counter

retains its last value. This allows multiple designs to be stored sequentially in an exter-

nal memory device for use in reconfigurable systems.

CR1:Not used (ignored)

CR2:0 = Enable Cascading

1 = Disable Cascading

CR2controls the operation of the dual-function I/O CSOUT. When CR2is set, the

CSOUT pin is not used by the configuration during downloads.

CR3:0 = Check Function enabled

1 = Check Function disabled

CR3controls the operation of the CHECK pin and enables the Check Function. When

CR3is set, the CHECK pin is not used by the configuration during downloads.

Table 5. Control Register

Byte 0 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24

Byte 1 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16

Byte 2 CR15 CR14 CR13 CR12 CR11 CR10 CR9CR8

Byte 3 CR7CR6CR5CR4CR3CR CR1CR0

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