Xilinx SP623 Manual de usuario

SP623 IBERT

Getting Started Guide

(ISE 11.4)

UG752 (v1.0.1) January 26, 2011

SP623 IBERT Getting Started Guide www.xilinx.com UG752 (v1.0.1) January 26, 2011

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Revision History

The following table shows the revision history for this document.

Date Version Revision

06/22/10 1.0 Initial Xilinx release.

01/26/11 1.0.1 Revised cover title. Was: “SP623 IBERT Getting Started Guide.” Is: “SP623 IBERT Getting

Started Guide (ISE 11.4).”

SP623 IBERT Getting Started Guide www.xilinx.com 3

UG752 (v1.0.1) January 26, 2011

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

SP623 IBERT

Getting Started Guide

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Extracting the IBERT Demonstration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Setting Up the SP623 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Connecting the GTP Transceivers and Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . 7

Running the IBERT Demonstration for Duals 101 and 123 . . . . . . . . . . . . . . . . . . . . . . . 9

GTP Transceiver Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

GTP TX/RX Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Setting Up the ChipScope Pro Analyzer Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Running the IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Running the IBERT Demonstration for Duals 245 and 267 . . . . . . . . . . . . . . . . . . . . . . 18

GTP Transceiver Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

GTP TX/RX Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Setting Up the ChipScope Pro Analyzer Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Running the IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Frequency Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Warranty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table of Contents

4www.xilinx.com SP623 IBERT Getting Started Guide

UG752 (v1.0.1) January 26, 2011

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UG752 (v1.0.1) January 26, 2011

SP623 IBERT

Getting Started Guide

Overview

This document provides a procedure for setting up the SP623 Spartan®-6 FPGA

GTP Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)

demonstration. The designs that are required to run the IBERT demonstration are stored in

the CompactFlash memory card that is provided with the SP623 board. The demonstration

shows the capabilities of the Spartan-6 XC6SLX150T FPGA GTP transceivers.

The IBERT demonstration is performed twice, once for each of the two designs included on

the CompactFlash memory card. The first design tests the transceivers located on the top

half of the FPGA (GTP Duals 101 and 123), the second design tests the transceivers on the

bottom half of the FPGA (GTP Duals 245 and 267). The procedure consists of:

1. Extracting the IBERT Demonstration Files.

2. Setting Up the SP623 Board.

3. Connecting the GTP Transceivers and Reference Clocks.

4. Configuring the FPGA.

5. Setting Up the ChipScope Pro Analyzer Tool.

6. Running the IBERT Demonstration.

The SP623 board is described in detail in UG751, SP623 Spartan-6 FPGA GTP Transceiver

Characterization Board User Guide.

Requirements

The equipment and software required to run the demonstration are:

• SP623 Spartan-6 FPGA GTP Transceiver Characterization Board including:

• CompactFlash memory card containing the IBERT demonstration designs

• GTP transceiver power supply module (installed on SP623 board)

• SuperClock-2 module (installed on SP623 board)

• 12 SMA to SMA cables

• One of these download cables:

•PlatformCableUSB-II(DLC10)

• Parallel IV Cable (PC4)

• Host PC with USB ports and a PCMCIA interface

6www.xilinx.com SP623 IBERT Getting Started Guide

UG752 (v1.0.1) January 26, 2011

Procedure

• CompactFlash PCMCIA adapter card

• Xilinx® ChipScope™ Pro analyzer software, version 11.4 or higher.

Software is available at: http://www.xilinx.com/chipscopepro

Caution! The SP623 board can be damaged by electrostatic discharge (ESD). Follow standard

ESD prevention measures when handling the board.

Procedure

Extracting the IBERT Demonstration Files

The ChipScope Pro Analyzer .cpj project files for the IBERT demonstration are located on

the CompactFlash memory card that is provided with the SP623 board. The project files are

used to load pre-saved MGT/IBERT and clock module control settings for the

demonstration. These files must be copied from the CompactFlash memory card to a

working directory on the host PC. To copy the project files:

1. Connect the CompactFlash memory card to the host computer.

Note: The CompactFlash memory card can be plugged into the host PC PCMCIA interface

using a PCMCIA adapter card.

2. Use Windows Explorer to locate sp623.zip on the Compact Flash memory card. The

ZIP file content is similar to the files shown in Figure 1.

3. Unzip the files to a working directory on the host PC.

X-Ref Target - Figure 1

Figure 1: ChipScope Software Project Files Included in the sp623.zip File

UG752_01_052410

SP623 IBERT Getting Started Guide www.xilinx.com 7

UG752 (v1.0.1) January 26, 2011

Procedure

Setting Up the SP623 Board

Caution! The SP623 board can be damaged by electrostatic discharge (ESD). Follow standard

ESD prevention measures when handling the board.

To set up the SP623 board:

1. Install the GTP transceiver power module:

a. Plug the module into connectors J34 and J179.

b. Remove DCPS ENABLE jumpers at J184 and J185 located on the SP623 board.

2. Verify the four SYSACE JTAG ENABLE jumpers are installed at locations J22, J23, J195,

and J196 on the SP623 board.

3. Place a jumper across pins 1–2 of the JTAG FMC BYPASS header at J162.

4. Enable the 200 MHz LVDS system clock by placing two jumpers (P, N) across pins 1–3

and pins 2–4 of J188.

5. Verify there is a 30 MHz oscillator in the SYSTEM ACE CLK oscillator socket at

location X1 on the SP623 board.

6. Enable the System ACE™ controller clock by placing the jumper on J4 to the ON

position.

7. Insert the CompactFlash memory card into the CF card connector (U24) located on the

underside of the SP623 board.

8. Install the SuperClock-2 module:

a. Align the three metal standoffs on the bottom side of the module with the three

mounting holes in the CLOCK MODULE interface of the SP623 board.

b. Using three 4-40 x 0.25 inch screws, firmly screw down the module from the

bottom of the SP623 board.

c. On the SuperClock-2 module, place a jumper across pins 1–2 (VCCO) of the

CONTROL VOLTAGE header, J18.

Connecting the GTP Transceivers and Reference Clocks

All GTP transceiver pins are connected to differential SMA connector pairs. The GTP

transceivers are grouped into four sets of two (referred to as Duals) which share two

differential reference clock pin-pairs. Figure 2 shows the SMA locations for the GTP

transceiver Duals (Dual 101, Dual 123, Dual 245, and Dual 267) and their associated

reference clocks (101 Clocks, 123 Clocks, 245 Clocks, and 267 Clocks).

8www.xilinx.com SP623 IBERT Getting Started Guide

UG752 (v1.0.1) January 26, 2011

Procedure

Note: The image in Figure 2 is for reference only and might not reflect the current revision of the

board.

The SuperClock-2 module clocks the GTP transceivers in the IBERT demonstration.

Figure 3 shows the location of the differential clock SMA connector pairs on the

SuperClock-2 module which connect to the GTP transceiver reference clocks on the SP623

board. For the IBERT demonstration, the frequencies of both output clocks from the

SuperClock-2 module are the same.

Note: The image in Figure 3 is for reference only and might not reflect the current revision of the

board.

X-Ref Target - Figure 2

Figure 2: GTP Transceiver and Reference Clock SMA Locations

UG752_02_052510

267 Clocks

Dual 267Dual 123

245 Clocks

Dual 245Dual 101

123 Clocks

101 Clocks

X-Ref Target - Figure 3

Figure 3: SuperClock-2 Module Output Clock SMA Locations

UG752_03_052810

CKOUT2_NCKOUT1_N

CKOUT2_PCKOUT1_P

SP623 IBERT Getting Started Guide www.xilinx.com 9

UG752 (v1.0.1) January 26, 2011

Procedure

Running the IBERT Demonstration for Duals 101 and 123

Running the IBERT demonstration for Duals 101 and 123 is described in this section. See

also Running the IBERT Demonstration for Duals 245 and 267, page 18.

GTP Transceiver Clock Connections

Refer to Table 1 and use four SMA cables to connect the output clock SMAs from the

SuperClock-2 module to the reference clock SMAs of GTP Duals 101 and 123 on the SP623

board. In other words, for each row in Table 1, connect the source SMA with its

corresponding destination SMA.

For example, connect CKOUT1_P (J5) to 101_REFCLK0_P (J59).

GTP TX/RX Connections

Refer to Table 2 and use eight SMA cables to connect the transmitter SMAs to the receiver

SMAs in GTP Duals 101 and 123. In other words, for each row in Table 2, connect the

transmitter SMA with its corresponding receiver SMA.

For example, connect 101_TX0_P (J53) to 101_RX0_P (J51) on the SP623 board.

Ta b le 1 : Duals 101 and 123 Reference Clock Connections

Source Destination

SuperClock-2 Module SP623 Board

Net Name SMA Connector Net Name SMA Connector

CKOUT1_P J5 101_REFCLK0_P J59

CKOUT1_N J6 101_REFCLK0_N J60

CKOUT2_P J7 123_REFCLK0_P J70

CKOUT2_N J8 123_REFCLK0_N J61

Ta b le 2 : Duals 101 and 123 TX/RX Connections

Transmitter Receiver

Net Name SMA Connector Net Name SMA Connector

101_TX0_P J53 101_RX0_P J51

101_TX0_N J54 101_RX0_N J52

101_TX1_P J57 101_RX1_P J55

101_TX1_N J58 101_RX1_N J56

123_TX0_P J67 123_RX0_P J68

123_TX0_N J66 123_RX0_N J69

123_TX1_P J63 123_RX1_P J65

123_TX1_N J62 123_RX1_N J64

10 www.xilinx.com SP623 IBERT Getting Started Guide

UG752 (v1.0.1) January 26, 2011

Procedure

The final SMA cable connections for Duals 101 and 123 are shown in Figure 4.

Configuring the FPGA

1. Plug the 12V output from the power supply into connector J122.

2. Connect the SP623 board to the Host PC. Either of these cables may be used for this

connection:

•PlatformCableUSB-II(DLC10)

• Parallel IV Cable (PC4)

Connect one end of the cable to the host PC. Connect the other end to the download

cable connector (J1) on the SP623 board.

3. To run the IBERT demonstration on Duals 101 and 123, set the System Ace Controller

Configuration Address switch SW3 to 000 as shown in Figure 5. The setting on SW3

determines which of the two bitstreams stored in the CompactFlash card configures

the FPGA.

X-Ref Target - Figure 4

Figure 4: SMA Cable Connections for Dual 101 and 123 Transceivers and Clocks

UG752_04_052510

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