Texas Instruments VLYNQ Port Manual de usuario

TMS320DM644x DMSoCVLYNQ Port

User's Guide

Literature Number: SPRUE36ASeptember 2007

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Contents

Preface ............................................................................................................................... 71 Introduction ................................................................................................................ 91.1 Purpose of the Peripheral ....................................................................................... 91.2 Features ........................................................................................................... 91.3 Functional Block Diagram ..................................................................................... 101.4 Industry Standard(s) Compliance Statement ............................................................... 102 Peripheral Architecture .............................................................................................. 112.1 Clock Control .................................................................................................... 112.2 Signal Descriptions ............................................................................................. 122.3 Pin Multiplexing ................................................................................................. 122.4 Protocol Description ............................................................................................ 122.5 VLYNQ Functional Description ............................................................................... 132.6 Initialization ...................................................................................................... 162.7 Auto-Negotiation ................................................................................................ 162.8 Serial Interface Width Configuration ......................................................................... 162.9 Address Translation ............................................................................................ 172.10 Flow Control ..................................................................................................... 202.11 Reset Considerations .......................................................................................... 212.12 Interrupt Support ................................................................................................ 212.13 DMA Event Support ............................................................................................ 232.14 Power Management ............................................................................................ 242.15 Emulation Considerations ..................................................................................... 243 VLYNQ Port Registers ................................................................................................ 253.1 Revision Register (REVID) .................................................................................... 263.2 Control Register (CTRL) ....................................................................................... 273.3 Status Register (STAT) ........................................................................................ 293.4 Interrupt Priority Vector Status/Clear Register (INTPRI) .................................................. 313.5 Interrupt Status/Clear Register (INTSTATCLR) ............................................................ 313.6 Interrupt Pending/Set Register (INTPENDSET) ............................................................ 323.7 Interrupt Pointer Register (INTPTR) ......................................................................... 323.8 Transmit Address Map Register (XAM)...................................................................... 333.9 Receive Address Map Size 1 Register (RAMS1) .......................................................... 343.10 Receive Address Map Offset 1 Register (RAMO1) ........................................................ 343.11 Receive Address Map Size 2 Register (RAMS2) .......................................................... 353.12 Receive Address Map Offset 2 Register (RAMO2) ........................................................ 353.13 Receive Address Map Size 3 Register (RAMS3) .......................................................... 363.14 Receive Address Map Offset 3 Register (RAMO3) ........................................................ 363.15 Receive Address Map Size 4 Register (RAMS4) .......................................................... 373.16 Receive Address Map Offset 4 Register (RAMO4) ........................................................ 373.17 Chip Version Register (CHIPVER) ........................................................................... 383.18 Auto Negotiation Register (AUTNGO) ....................................................................... 384 Remote Configuration Registers ................................................................................. 39Appendix A VLYNQ Protocol Specifications ........................................................................ 40A.1 Special 8b/10b Code Groups ................................................................................. 40

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A.2 Supported Ordered Sets ....................................................................................... 40A.3 VLYNQ 2.0 Packet Format .................................................................................... 41A.4 VLYNQ 2.X Packets ............................................................................................ 43Appendix B Write/Read Performance .................................................................................. 45B.1 Write Performance.............................................................................................. 45B.2 Read Performance ............................................................................................. 47Appendix C Revision History ............................................................................................. 48

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List of Figures

1 VLYNQ Port Functional Block Diagram ................................................................................. 102 External Clock Block Diagram ............................................................................................ 113 Internal Clock Block Diagram ............................................................................................. 114 VLYNQ Module Structure ................................................................................................. 135 Write Operations ........................................................................................................... 146 Read Operations ........................................................................................................... 157 Example Address Memory Map .......................................................................................... 188 Interrupt Generation Mechanism Block Diagram ....................................................................... 229 Revision Register (REVID) ................................................................................................ 2610 Control Register (CTRL) ................................................................................................... 2711 Status Register (STAT) .................................................................................................... 2912 Interrupt Priority Vector Status/Clear Register (INTPRI) .............................................................. 3113 Interrupt Status/Clear Register (INTSTATCLR) ........................................................................ 3114 Interrupt Pending/Set Register (INTPENDSET) ........................................................................ 3215 Interrupt Pointer Register (INTPTR) ..................................................................................... 3216 Transmit Address Map Register (XAM) ................................................................................. 3317 Receive Address Map Size 1 Register (RAMS1) ...................................................................... 3418 Receive Address Map Offset 1 Register (RAMO1) .................................................................... 3419 Receive Address Map Size 2 Register (RAMS2) ...................................................................... 3520 Receive Address Map Offset 2 Register (RAMO2) .................................................................... 3521 Receive Address Map Size 3 Register (RAMS3) ...................................................................... 3622 Receive Address Map Offset 3 Register (RAMO3) .................................................................... 3623 Receive Address Map Size 4 Register (RAMS4) ...................................................................... 3724 Receive Address Map Offset 4 Register (RAMO4) .................................................................... 3725 Chip Version Register (CHIPVER) ....................................................................................... 3826 Auto Negotiation Register (AUTNGO) ................................................................................... 38A-1 Packet Format (10-bit Symbol Representation) ........................................................................ 41

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List of Tables

1 VLYNQ Port Pins ........................................................................................................... 122 Serial Interface Width ...................................................................................................... 163 Address Translation Example (Single Mapped Region) .............................................................. 184 Address Translation Example (Single Mapped Region) .............................................................. 195 VLYNQ Register Address Space ......................................................................................... 256 VLYNQ Port Controller Registers ........................................................................................ 257 Revision Register (REVID) Field Descriptions ......................................................................... 268 Control Register (CTRL) Field Descriptions ............................................................................ 279 Status Register (STAT) Field Descriptions ............................................................................. 2910 Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions ........................................ 3111 Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions .................................................. 3112 Interrupt Pending/Set Register (INTPENDSET) Field Descriptions ................................................. 3213 Interrupt Pointer Register (INTPTR) Field Descriptions ............................................................... 3214 Address Map Register (XAM) Field Descriptions ...................................................................... 3315 Receive Address Map Size 1 Register (RAMS1) Field Descriptions ................................................ 3416 Receive Address Map Offset 1 Register (RAMO1) Field Descriptions .............................................. 3417 Receive Address Map Size 2 Register (RAMS2) Field Descriptions ................................................ 3518 Receive Address Map Offset 2 Register (RAMO2) Field Descriptions .............................................. 3519 Receive Address Map Size 3 Register (RAMS3) Field Descriptions ................................................ 3620 Receive Address Map Offset 3 Register (RAMO3) Field Descriptions .............................................. 3621 Receive Address Map Size 4 Register (RAMS4) Field Descriptions ................................................ 3722 Receive Address Map Offset 4 Register (RAMO4) Field Descriptions .............................................. 3723 Chip Version Register (CHIPVER) Field Descriptions................................................................. 3824 Auto Negotiation Register (AUTNGO) Field Descriptions ............................................................ 3825 VLYNQ Port Remote Controller Registers .............................................................................. 39A-1 Special 8b/10b Code Groups ............................................................................................. 40A-2 Supported Ordered Sets .................................................................................................. 40A-3 Packet Format (10-bit Symbol Representation) Description .......................................................... 42B-1 Scaling Factors ............................................................................................................. 46B-2 Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) .................................... 46B-3 Relative Performance with Various Latencies .......................................................................... 47C-1 Document Revision History ............................................................................................... 48

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PrefaceSPRUE36A – September 2007

Read This First

About This Document

This document describes the VLYNQ™ communications interface port in the TMS320DM644x DigitalMedia System-on-Chip (DMSoC).

Notational Conventions

This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM644x Digital Media System-on-Chip (DMSoC). Copiesof these documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com.

The current documentation that describes the DM644x DMSoC, related peripherals, and other technicalcollateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .

SPRUE14 —TMS320DM644x DMSoC ARM Subsystem Reference Guide. Describes the ARMsubsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the DSP subsystem, the videoprocessing subsystem, and a majority of the peripherals and external memories.

SPRUE15 —TMS320DM644x DMSoC DSP Subsystem Reference Guide. Describes the digital signalprocessor (DSP) subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC).

SPRUE19 —TMS320DM644x DMSoC Peripherals Overview Reference Guide. Provides an overviewand briefly describes the peripherals available on the TMS320DM644x Digital MediaSystem-on-Chip (DMSoC).

SPRAA84 —TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from theTexas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. Theobjective of this document is to indicate differences between the two cores. Functionality in thedevices that is identical is not included.

SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.

SPRU871 —TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.

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Related Documentation From Texas Instruments

SPRAAA6 —EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migratingfrom the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memoryaccess (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. Thisdocument summarizes the key differences between the EDMA3 and the EDMA2 and providesguidance for migrating from EDMA2 to EDMA3.Trademarks

VLYNQ is a trademark of Texas Instruments.

8Read This First SPRUE36A – September 2007Submit Documentation Feedback

1 Introduction

1.1 Purpose of the Peripheral

1.2 Features

User's GuideSPRUE36A – September 2007

VLYNQ Port

The VLYNQ™ communications interface port is a low pin count, high-speed, point-to-point serial interfacein the TMS320DM644x Digital Media System-on-Chip (DMSoC) used for connecting to host processorsand other VLYNQ-compatible devices. The VLYNQ port is a full-duplex serial bus where transmit andreceive operations occur separately and simultaneously without interference.

VLYNQ enables the extension of an internal bus segment to one or more external physical devices. Theexternal devices are mapped to local physical address space and appear as if they are on the internal busof the DM644x DMSoC. The external devices must also have a VLYNQ interface.

VLYNQ uses a simple block code (8b/10b) packet format and supports in-band flow control so that noextra terminals are needed to indicate that overflow conditions might occur.

The VLYNQ module on the DM644x DMSoC serializes a write transaction to the remote/external deviceand transfers the write via the VLYNQ port (TX pins). The remote VLYNQ module deserializes thetransaction on the other side.

The read transactions to the remote/external device follow the same process, but the remote device'sVLYNQ module serializes the read return data and transfers it to the VLYNQ port (RX pins). The readreturn data is finally deserialized and released to the device internal bus.

The external device can also initiate read and write transactions.

The general features of the VLYNQ port are:•Low pin count (10 pin interface, scalable to as low as 3 pins)•No tri-state signals– All signals are dedicated and driven by only one device– Necessary to allow support for high-speed PHYs•Scalable Performance

– Programmable frequency and 1 to 4 bits for TX and RX data– Performance increases linearly as the data port width increases•Simple packet-based transfer protocol for memory-mapped access– Write request/data packet– Read request packet– Read response data packet– Interrupt request packet•Auto width negotiation

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1.3 Functional Block Diagram

Slave

config

bus

Interface

Master

config

Interface

bus

VLYNQ module

VLYNQ register

access

CPU/EDMA initiated

transfers to

remote device

Off chip

(remote)

device access

ARM/EDMA

memory

System

VLYNQ_SCRUN

VLYNQ_CLOCK

VLYNQ_RXD[3:0]

VLYNQ_TXD[3:0]

INT31

ARM interrupt

controller

VLQINT

1.4 Industry Standard(s) Compliance Statement

Introduction

•Symmetric Operations– Transmit (TX) pins on the first device connect to the receive (RX) pins on the second device andvice-versa.

– Data pin widths are automatically detected after reset– Re-request packets, response packets, and flow control information are all multiplexed and sentacross the same physical pins.– Supports both host/peripheral and peer-to-peer communication models•Simple block code packet formatting (8b/10b)•Supports in-band and flow control– No extra pins are needed– Allows the receiver to momentarily throttle the transmitter back when overflow is about to occur– Uses the special built-in block code capability to interleave flow control information seamlessly withuser data•Automatic packet formatting optimizations•Internal loopback modes are provided•Connects to legacy VLYNQ devices

Figure 1 shows a functional block diagram of the VLYNQ port.

Figure 1. VLYNQ Port Functional Block Diagram

VLYNQ is an interface defined by Texas Instruments and does not conform to any other industry standard.

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