Texas Instruments TMS320C645X Manual de usuario

TMS320C645x DSP

General-Purpose Input/Output (GPIO)

User’s Guide

Literature Number: SPRU724

December 2005

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3General-Purpose Input/Output (GPIO)SPRU724

Preface

Read This First

About This Manual

This document describes the general-purpose input/output (GPIO) peripheral

in the digital signal processors (DSPs) of the TMS320C645x™DSP family.

Notational Conventions

This document uses the following conventions.

-Hexadecimal numbers are shown with the suffix h. For example, the

following number is 40 hexadecimal (decimal 64): 40h.

-When referencing specific register bits, the X in the register bit name is

replaced with the bit number; for example, GPXDIR refers to the bit field

of the GPIO direction register and GP15DIR refers to bit 15 of GPDIR.

-Registers in this document are shown in figures and described in tables.

JEach register figure shows a rectangle divided into fields that represent

the fields of the register. Each field is labeled with its bit name, its

beginning and ending bit numbers above, and its read/write properties

below. A legend explains the notation used for the properties.

JReserved bits in a register figure designate a bit that is used for future

device expansion.

Related Documentation From Texas Instruments

The following documents describe the C6000™devices and related support

tools. Copies of these documents are available on the Internet at www.ti.com.

Tip: Enter the literature number in the search box provided at www.ti.com.

TMS320C6000 CPU and Instruction Set Reference Guide (literature

number SPRU189) gives an introduction to the TMS320C62xtand

TMS320C67xtDSPs, development tools, and third-party support.

TMS320C6455 Technical Reference (literature number SPRU965) gives an

introduction to the TMS320C6455tDSP and discusses the application

areas that are enhanced.

Trademarks

4General-Purpose Input/Output (GPIO) SPRU724

TMS320C6000 Programmer’s Guide (literature number SPRU198)

describes ways to optimize C and assembly code for the

TMS320C6000tDSPs and includes application program examples.

TMS320C6000 Code Composer Studio Tutorial (literature number

SPRU301) introduces the Code Composer Studiotintegrated develop-

ment environment and software tools.

Code Composer Studio Application Programming Interface Reference

Guide (literature number SPRU321) describes the Code Composer

Studiotapplication programming interface (API), which allows you to

program custom plug-ins for Code Composer.

TMS320C64x+ Megamodule Reference Guide (literature number

SPRU871) describes the TMS320C64x+ digital signal processor (DSP)

megamodule. Included is a discussion on the internal direct memory ac-

cess (IDMA) controller, the interrupt controller, the power−down control-

ler, memory protection, bandwidth management, and the memory and

cache.

TMS320C6000 DSP Peripherals Overview Reference Guide (literature

number SPRU190) provides a brief description of the peripherals avail-

able on the TMS320C6000 digital signal processors (DSPs).

TMS320C6455 Chip Support Libraries (CSL) (literature number SPRC234)

is a download with the latest chip support libraries.

Trademarks

Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,

TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks of

Texas Instruments.

Related Documentation From Texas Instruments / Trademarks

Contents

5General-Purpose Input/Output (GPIO)SPRU724

Contents

1 Overview 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 GPIO Function 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Interrupt and Event Generation 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Emulation Halt Operation 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Registers 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Interrupt Per-Bank Enable Register (BINTEN) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Direction Register (DIR) 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Output Data Register (OUT_DATA) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Set Data Register (SET_DATA) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Clear Data Register (CLR_DATA) 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Input Data Register (IN_DATA) 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Set Rising Edge Interrupt Register (SET_RIS_TRIG) 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG) 23. . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 Set Falling Edge Interrupt Register (SET_FAL_TRIG) 24. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG) 25. . . . . . . . . . . . . . . . . . . . . . . . . .

Figures

6General-Purpose Input/Output (GPIO) SPRU724

Figures

1 TMS320C645x DSP Block Diagram 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 GPIO Peripheral Block Diagram 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Interrupt Per-Bank Enable Register (BINTEN) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Direction Register (DIR) 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Output Data Register (OUT_DATA) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Set Data Register (SET_DATA) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Clear Data Register (CLR_DATA) 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Input Data Register (IN_DATA) 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 Set Rising Edge Interrupt Register (SET_RIS_TRIG) 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG) 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 Set Falling Edge Interrupt Register (SET_FAL_TRIG) 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG) 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

7General-Purpose Input/Output (GPIO)SPRU724

Tables

1 GPIO Interrupt and EDMA Event Configuration Options 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 GPIO Registers 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions 16. . . . . . . . . . . . . . . . . . . . .

4 Direction Register (DIR) Field Descriptions 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Output Data Register (OUT_DATA) Field Descriptions 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Set Data Register (SET_DATA) Field Descriptions 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Clear Data Register (CLR_DATA) Field Descriptions 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Input Data Register (IN_DATA) Field Descriptions 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 Set Rising Edge Interrupt Register (SET_RIS_TRIG) Field Descriptions 22. . . . . . . . . . . . . . .

10 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG) Field Descriptions 23. . . . . . . . . . . . .

11 Set Falling Edge Interrupt Register (SET_FAL_TRIG) Field Descriptions 24. . . . . . . . . . . . . .

12 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG) Field Descriptions 25. . . . . . . . . . . .

8General-Purpose Input/Output (GPIO) SPRU724

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9General-Purpose Input/Output (GPIO)SPRU724

General-PurposeInput/Output(GPIO)

This document describes the general-purpose input/output (GPIO) peripheral

in the digital signal processors (DSPs) of the TMS320C645x™DSP family.

1 Overview

The general-purpose input/output (GPIO) peripheral provides dedicated

general-purpose pins that can be configured as either inputs or outputs. When

configured as an output, you can write to an internal register to control the state

driven on the output pin. When configured as an input, you can detect the state

of the input by reading the state of an internal register.

In addition, the GPIO peripheral can produce CPU interrupts and EDMA

synchronization events in different interrupt/event generation modes.

Figure 1 shows the GPIO peripheral in the TMS320C645x™DSP. Figure 2

shows the GPIO peripheral block diagram.

Overview

General-Purpose Input/Output (GPIO)10 SPRU724

Figure 1. TMS320C645x DSP Block Diagram

L1 S1 M1 D1

Data path A

Data path B

S2M2 L2

L1 data memory controller

Cache control

Memory protection

Interrupt

and exception

controller

Power control

Instruction decode

16/32−bit instruction dispatch

Instruction fetch

SPLOOP buffer

C64x+ CPU

IDMA

Bandwidth management

Cache control

L1 program memory controller Advanced

event

triggering

(AET)

L2 memory

controller

Bandwidth

management

Memory

protection

registers

Configuration

L1P

cache/SRAM

L1D

cache/SRAM

PLL2

DDR2 memory

EMIFA

Other

peripherals

EDMA

Boot

configuration

Switched central resource

PLL2

L2 memory

controller

memory

External

controller

DMA

Master

DMA

Slave

Cache

control

Bandwidth management

Memory protection

GPIO

Some GPIO pins are MUXed with other device pins. Refer to the device-specific

datasheet for details on specific MUXing and for the availability of the register

bits. GPINT[0:15] are all available as synchronization events to the EDMA

controller and as interrupt sources to the CPU.

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