Texas Instruments TPS65980EVM Manual de usuario

TPS65980EVM

User's Guide

Literature Number: SLVUA50

April 2014

Contents

1 Introductions....................................................................................................................... 4

2 Setup.................................................................................................................................. 4

2.1 Power Supply Inputs..................................................................................................... 4

2.2 Jumper Settings .......................................................................................................... 5

2.3 Device Configurations ................................................................................................... 6

2.4 Test Points ................................................................................................................ 8

3 Board Assembly and Layout ................................................................................................. 9

4 Schematic ......................................................................................................................... 11

5 Bill of Materials .................................................................................................................. 12

2Table of Contents SLVUA50–April 2014

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List of Figures

1 Connection Points ........................................................................................................... 4

2 Low Voltage Input............................................................................................................ 6

3 High Voltage Input During Sleep .......................................................................................... 6

4 High Voltage Input With Lower CBL_OUT Current Limit............................................................... 7

5 High Voltage Input With Higher CBL_OUT Current Limit .............................................................. 7

6 Top Layer Assembly......................................................................................................... 9

7 Bottom Layer Assembly..................................................................................................... 9

8 Top Layer Routing ......................................................................................................... 10

9 Bottom Layer Routing...................................................................................................... 10

10 Schematic ................................................................................................................... 11

SLVUA50–April 2014 List of Figures

TBT

DEV_EN

OFF|ON

CBL_ILIM

HI|LOW

DEV

OUT

TBT

OUT

CBL

OUT

User's Guide

SLVUA50–April 2014

TPS65980EVM

1 Introductions

The Texas Instruments TPS65980EVM evaluation module (EVM) helps designers evaluate the operation

and performance of the TPS65980: a DC/DC switching regulator that receives power from a Thunderbolt

bus ranging from 2.5V to 15.75V on TBT_IN and generates three separate 3.3V supply outputs

TBT_OUT, CBL_OUT, and DEV_OUT.

The TBT_OUT supply provides power to the local peripheral Thunderbolt™ controller and support

circuitry. The CBL_OUT supply provides power back to the Thunderbolt™ cable and has adjustable

current limit. The DEV_OUT supply provides power to all other circuitry in the device to perform its

designed function.

The TPS65980 is available in a 24-pin 5mm x 4mm x 0.9mm QFN package.

Table 1. Device and Package Configurations

CONVERTER IC PACKAGE

U1 TPS65980RHF RHF

2 Setup

This section describes the jumpers and connectors on the EVM as well as how to properly connect, set

up, and use the TPS65980EVM.

2.1 Power Supply Inputs

Figure 1 shows the connection points needed to fully and correctly interface with the TPS65980EVM.

Figure 1. Connection Points

4TPS65980EVM SLVUA50–April 2014

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Setup

The TPS65980 has three operating modes dictated by the voltage applied on TBT_IN. The total power

available at each of the outputs is determined by the operating mode. Table 2 summarizes the operating

modes in terms of input voltage range and output current ranges.

Input/Output Supply Ranges

Operating Mode TBT_IN Vrange TBT_OUT Irange(1) CBL_OUT DEV_OUT

Irange(1) Irange(1)

Low Voltage 2.5V – 3.4V 5mA – 50mA Output Disabled Output Disabled

High Voltage 10V – 15.75V 235mA – 1A 0 – 1.44A(1) 0 – 2.5A

High Voltage 5.2V – 15.75V 5mA – 31mA 0 – 235mA 0 – 700mA

(Sleep)

(1) Note: the total combined output current from TBT_OUT, CBL_OUT, and DEV_OUT should never

exceed 3.5A.

2.2 Jumper Settings

There are two digital input signals which can be set with jumpers as defined in Table 3. These signals

can be set to a logical value of “0” or “1” by moving the jumper between the 2 available positions (left and

right). See the TPS65980 data sheet for more information on the functionality of these signals.

Digital Signal Jumpers

Header Name Logic Jumper Position Effect

J5 DEV_EN 1 Left (TBT_OUT) DEV_OUT

Disabled

DEV_EN 0 Right (GND) DEV_OUT Enabled

J6 CBL_ILIM 1 Left (TBT_OUT) CBL_OUT using

higher current limit

CBL_ILIM 0 Right (GND) CBL_OUT using

lower current limit

SLVUA50–April 2014 TPS65980EVM

TBT

DEV_EN

OFF|ON

CBL_ILIM

HI|LOW

DEV

OUT

TBT

OUT

CBL

OUT

3.0V – 3.319V

0mA – 700mA

3.221V – 3.319V

5mA – 31mA

3.171V – 3.319V

0mA – 235mA

5.2V – 15.75V

TBT

DEV_EN

OFF|ON

CBL_ILIM

HI|LOW

DEV

OUT

TBT

OUT

CBL

OUT

OUTPUT

OFF

3.135V – 3.4V

5mA – 50mA

OUTPUT

OFF

2.5V – 3.4V

Setup

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2.3 Device Configurations

Figure 2,Figure 3,Figure 4, and Figure 5illustrate the three operating modes discussed in section 2.1 as

well as the two programmable CBL_OUT current limits.

This is the average output voltage range for normal loads. During light load, the peak output voltage from TBT_OUT

may surpass 3.4V, but not exceeding 3.42V

Figure 2. Low Voltage Input

This is the average output voltage range for normal loads. During light load, the average output voltage from

CBL_OUT may reach 3.4 with peaks not exceeding 3.42V.

Figure 3. High Voltage Input During Sleep

6TPS65980EVM SLVUA50–April 2014

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TBT

DEV_EN

OFF|ON

CBL_ILIM

HI|LOW

DEV

OUT

TBT

OUT

CBL

OUT

3.0V – 3.319V

0mA – 2500mA

3.221V – 3.319V

235mA – 1000mA

3.12V – 3.319V

0mA – 1440mA

10V – 15.75V

TBT

DEV_EN

OFF|ON

CBL_ILIM

HI|LOW

DEV

OUT

TBT

OUT

CBL

OUT

3.0V – 3.319V

0mA – 2500mA

3.221V – 3.319V

235mA – 1000mA

3.171V – 3.319V

0mA – 720mA

5.2V – 15.75V

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Setup

A This is the average output voltage range for normal loads. During light load, the average output voltage from

TBT_OUT and CBL_OUT may reach 3.4 with peaks not exceeding 3.42V

B The total combined output current from TBT_OUT, CBL_OUT, and DEV_OUT should never exceed 3.5A.

Figure 4. High Voltage Input With Lower CBL_OUT Current Limit

A This is the average output voltage range for normal loads. During light load, the average output voltage from

TBT_OUT and CBL_OUT may reach 3.4 with peaks not exceeding 3.42V

B The total combined output current from TBT_OUT, CBL_OUT, and DEV_OUT should never exceed 3.5A.

Figure 5. High Voltage Input With Higher CBL_OUT Current Limit

SLVUA50–April 2014 TPS65980EVM

Setup

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2.4 Test Points

Several test points are provided solely for the purpose measuring certain signals. It is NOT recommended

to use the test points to supply power to TBT_IN or load TBT_OUT, CBL_OUT, or DEV_OUT.

Table 2. Test Point Descriptions

Test Point Signal Description

TP1 GND

TP2 DEV_OUT

TP3 Switching Node

TP4 BOOT

TP5 GND

TP6 TBT_IN

TP7 GND

TP8 TBT_OUT

TP9 Compensation Pin

TP10 GND

TP11 GND

TP12 Soft Start Pin

TP13 RESET_N Signal

TP14 HV_OK Signal

TP15 GND

TP16 CBL_OUT

8TPS65980EVM SLVUA50–April 2014

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Board Assembly and Layout

3 Board Assembly and Layout

Figure 6 and Figure 7 show the top and bottom assembly for the TPS65980EVM.

Figure 6. Top Layer Assembly

Figure 7. Bottom Layer Assembly

SLVUA50–April 2014 TPS65980EVM

Board Assembly and Layout

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Figure 8 and Figure 9 show the top and bottom layout for the TPS65980EVM.

Figure 8. Top Layer Routing

Figure 9. Bottom Layer Routing

10 TPS65980EVM SLVUA50–April 2014

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