Texas Instruments LM8365EVM Manual de usuario
LM8365EVM User Guide
User's Guide
Literature Number: SNVU493
October 2015
SNVU493–October 2015
Introduction
The Texas Instruments LM8365EVM evaluation module (EVM) helps designers evaluate the operation
and performance of the LM8365 Micropower Undervoltage Supervisor with Programmable Output Delay.
For this EVM, the 2.7 V reset threshold LM8365 will be used. The EVM demonstrates proper functionality
of the LM8365 via selection of 3 distinct capacitors corresponding to programmable delay times. For more
information about the LM8365 functional and electrical characteristics, consult the LM8365 datasheet
(SNVS233).
The EVM contains one LM8365 Micropower Undervoltage Supervisor (See Table 1).
Table 1. Device and Package Configurations
REF DES IC PACKAGE
U1 LM8365BALMF27/NOPB SOT-23
1 Features
• INPUT Voltage Range: 1 V to 6 V
• Extremely Low Quiescent Current: 0.65 µA, at VIN = 2.87 V
• Threshold Voltage of 2.7 V
• High Accuracy Threshold Voltage (± 2.5%)
• Active Low, Open Drain Output
• Surface Mount Package (5-Pin SOT-23)
• Programmable Output Delay
– o 3 capacitor options for programmable delay
• Board Size: 1.50” x 1.15”
2Introduction SNVU493–October 2015
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SNVU493–October 2015
Setup
This section describes the connectors on the EVM as well as how to properly connect, set up, and use the
LM8365EVM. Ensure the external power supply is turned off while making connections on the board.
1 Input/Output Connector Description
• TP1 – VIN is the input power supply.
• TP2 – RST is the RESEToutput.
• TP3 – DLY is the positive side of the delay capacitor(s). This can be monitored to observe capacitor
behavior during delay charging/discharging.
• TP4 – GND is the ground.
2 Header Description
• J1 is the header that selects the 0.01 µF capacitor for programmable delay.
• J2 is the header that selects the 0.1 µF capacitor for programmable delay.
• J3 is the header that selects the 1 µF capacitor for programmable delay.
3 Board Setup
Before applying power to the LM8365EVM, all external connections should be verified. An external power
supply should be turned off and connected with proper polarity to the VIN (TP1) and GND (TP4)
connectors. The input voltage range for the EVM is 1 V to 6 V. The RST (TP2) pin can be used to monitor
the RESET output of the LM8365 in response to various input voltages. The DLY (TP3) terminal provides
a means for observation of the capacitor charging/discharging behavior.
Furthermore, the LM8365EVM allows for programming of the RESET output time delay by selecting from
3 different sized capacitors through the use of headers J1, J2, and J3. These capacitors, labeled C1, C2,
and C3 are 0.01 µF, 0.1 µF, and 1 µF respectively. To select a capacitor, the provided jumper should be
connected to the respective header. If the jumpers are left unpopulated, the EVM will be programmed with
the minimum amount of delay. Multiple capacitors can also be connected in parallel by placing multiple
jumpers.
Once all the connections to the LM8365EVM have been verified, power can be applied to VIN, and
evaluation can begin.
3
SNVU493–October 2015 Setup
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Applications
For the following operation examples, we will use an LM8365 with a typical voltage threshold of 2.7 V.
1 RST Response to VIN Undervoltage
In a typical application, the RESET output can order a microprocessor to enter reset when VCC drops
below its minimum operating voltage. Jumpers J1, J2, and J3 are left unpopulated resulting in the
minimum programmed output delay. As shown in Figure 1, the RST voltage follows VIN as long as the
VIN voltage is above the RESET threshold. When VIN falls below this threshold, the RESET pin outputs
low. When VIN rises above the threshold, the RST voltage is pulled back up to VIN, corresponding to the
RESET pin outputting high. The LM8365 provides proper voltage supervision in critical situations like
undervoltage input to a microprocessor.
Figure 1. RST Response to Low VIN
4Applications SNVU493–October 2015
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RST Hysteresis Behavior
2 RST Hysteresis Behavior
One valuable piece of information to understand is the hysteresis around the RESET threshold. J1, J2,
and J3 are unpopulated resulting in the minimum programmed output delay. The RESET pin outputs high
only when VIN rises above the RESET threshold plus a certain amount of hysteresis. Figure 2 shows the
observed hysteresis, which can eliminate erratic reset responses in certain situations, for example, when
the input voltage is hovering very close to the threshold voltage.
Figure 2. RST Response to Threshold VIN
5
SNVU493–October 2015 Applications
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Programmed Delay with 0.1 µF Capacitor
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3 Programmed Delay with 0.1 µF Capacitor
A typical application usually requires a certain delay before the microprocessor is pulled out of reset once
the VCC rises above its minimum operating voltage. This is to allow some time for the VCC to settle to a
stable voltage before the microprocessor begins running. Figure 3 shows this delay, which is programmed
by populating J2. This corresponds to a CD capacitor of 0.1 µF. In an application, this provides the user
confidence that the microprocessor will exit its reset state when its VCC has stabilized above the minimum
operating voltage.
Figure 3. 0.1 µF Capacitor Programmed Delay
6Applications SNVU493–October 2015
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Programmed Delay with 1 µF Capacitor
4 Programmed Delay with 1 µF Capacitor
In some supervising applications, a long output delay is necessary. This provides some time for VCC to
stabilize above the RESET threshold before the supervised device can exit reset state. Using the exact
same setup as in Section 3 Programmed Delay with 0.1 µF Capacitor, we populate J3 instead. This
corresponds to a CD capacitor of 1 µF.
Figure 4. 1 µF Capacitor Programmed Delay
7
SNVU493–October 2015 Applications
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CD Voltage Behavior
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5 CD Voltage Behavior
Aside from observing the programmed output delay, the LM8365EVM provides the option to observe the
behavior of the selected capacitor(s). For this example, we use the same setup as Section 4 Programmed
Delay with 1 µF Capacitor. The behavior of the 1 µF CD capacitor is shown in Figure 5.
It should be noted that when the DLY terminal voltage is measured using an oscilloscope probe, the CD
capacitor may exhibit some leakage current into the oscilloscope probe. As a result, the RESET pin may
output with a slightly longer delay.
Figure 5. 1 µF Capacitor Delay Behavior
8Applications SNVU493–October 2015
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Fast RST Response to Falling VIN
6 Fast RST Response to Falling VIN
In an application, it is beneficial to have flexibility in time delay for exiting reset state, but when entering
reset state we need extremely fast response. For example, if we have a microprocessor running code, it is
crucial that this device does not operate below its specified operating voltage. This could potentially lead
to disastrous results. Figure 6 shows the reaction time of the RESET output when VIN falls below the
RESET threshold.
Figure 6. RST Output Low Response
9
SNVU493–October 2015 Applications
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SNVU493–October 2015
Board Layout
Figure 7 shows the board layout for the LM8365EVM. Please note that we have provided an unpopulated
footprint for C4 which allows room for an input capacitor.
Figure 7. Top Layer Layout
10 Board Layout SNVU493–October 2015
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