Texas Instruments LMK00105 Manual de usuario

SNLU097A–March 2012–Revised July 2019

LMK00105 User’s Guide

User's Guide

SNLU097A–March 2012–Revised July 2019

LMK00105 User’s Guide

This user guide describes how to set up and operate the LMK00105 evaluation board kit (EVK). The

LMK00105 is a high performance, low noise, low voltage CMOS fanout buffer. The core voltage can be

2.5 or 3.3 volts, while the power supply for the outputs can be selected from: 1.5 V, 1.8 V, 2.5 V, or 3.3 V,

provided that it does not exceed the core supply voltage™

Contents

1 Introduction ................................................................................................................... 2

2 Quick Start Setup............................................................................................................ 2

2.1 Quick Start Description............................................................................................. 3

3 Signal Path and Control Switches......................................................................................... 3

4 Power Supplies .............................................................................................................. 4

5 Clock Inputs .................................................................................................................. 4

5.1 Crystal Oscillator Interface......................................................................................... 4

5.2 Configuring OSCin for a Crystal Mode........................................................................... 4

6 Clock Outputs ................................................................................................................ 4

7 Schematics ................................................................................................................... 5

8 PCB Layout................................................................................................................... 7

9 Bill of Materials............................................................................................................... 9

List of Figures

1 LMK00105 Quick Start Setup.............................................................................................. 2

2 Schematic Sheet 1 .......................................................................................................... 5

3 Schematic Sheet 2 .......................................................................................................... 6

4 PCB Top ...................................................................................................................... 7

5 Bottom Side (Layer Inverted, Not to Scale) .............................................................................. 8

List of Tables

1 Part Description.............................................................................................................. 2

2 Default Clock Output Modes / Interfaces................................................................................. 3

3 Input Selection (0=SW OFF, 1=SW ON) ................................................................................. 3

4 Output Enable Selection (0=OFF, 1=ON) ............................................................................... 3

5 Power Supply Configuration................................................................................................ 4

6 Bill of Materials............................................................................................................... 9

Output

Power Supply

Core

Power Supply

Single Ended

Oscillator Input

CLKin

Diﬀerential

Input Select

DIP Switches

CLKout0-

CLKout1

CLKout2-C

CLKout4C

Introduction

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LMK00105 User’s Guide

1 Introduction

This user guide describes how to set up and operate the LMK00105 evaluation board kit (EVK). The

LMK00105 is a high performance, low noise, low voltage CMOS fanout buffer. The core voltage can be

2.5 or 3.3 volts, while the power supply for the outputs can be selected from: 1.5 V, 1.8 V, 2.5 V, or 3.3 V,

provided that it does not exceed the core supply voltage.

Table 1. Part Description

BUFFER IC PACKAGE

U1 LMK00105 LLP-24

2 Quick Start Setup

Figure 1. LMK00105 Quick Start Setup

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Quick Start Setup

SNLU097A–March 2012–Revised July 2019

LMK00105 User’s Guide

2.1 Quick Start Description

The LMK00105 EVK allows full verification of the device functionality and performance specifications. To

quickly set up and operate the board with basic equipment, refer to the quick start procedure below and

test setup shown in Figure 1.

1. 1. Verify the output mode control switches, S1[1:4], match the states shown in Table 2 to reflect the

default output clock interfaces configured on the EVK.

Table 2. Default Clock Output Modes / Interfaces

SW POSITION/NAME SW STATE

S1[1]/SEL 0 (OFF)

S1[2]/NC Unused

S1[3]/OE 1 (OFF)

S1[4]/NC Unused

2. 2. Connect the Vdd SMA from the board to a 3.3 V source. This powers the core portions of the

LMK00105.

3. 3. Connect the Vddo SMA from the board to a 3.3 V source. This powers the output drivers of the

LMK00105

4. 4. Set the desired clock input using the input selection control switches, S1[1], per Table 3. A

differential clock source can be connected to SMAs CLKin/CLKin*.

Table 3. Input Selection (0=SW OFF, 1=SW ON)

SELECTED INPUT DEFAULT INPUT MODE S1CLKin_Sel State

CLKin/CLKin* Differential clock 0

OSCin Select OSCin 1

Note: CLKin path is configured by default to receive a differential clock as the input. The SMA input is

AC coupled to the device inputs and terminated with 100 Ωdifferential. Refer to the Clock Inputs

section to configure the EVK for a single-ended input.

5. 5. Connect and measure any clock output SMA labeled CLKoutX to an oscilloscope or other test

instrument using SMA cable(s). The output clock will be level-translated/buffered copy of the selected

clock input or crystal oscillator. Note: All output clocks are AC-coupled to the SMA connectors to

ensure safe use with RF instruments.

Note: Switching noise from one or more un-terminated outputs may impair the signal quality of the

measured output(s). To minimize switching noise and EMI, properly terminate any unused output path

using an SMA load or the component options near the SMA outputs, or alternatively, remove the 0 Ω

series resistor nearest the unused output pin.

3 Signal Path and Control Switches

The LMK00105 supports single-ended or differential clocks on CLKin. A second input, OSCin, has an

integrated crystal oscillator interface that supports a fundamental mode, AT-cut crystal or an external

single- 4 LMK00105 Users Guide SNLU097 March 2012 ended clock. The two-input multiplexer is pin-

controlled. To achieve the maximum operating frequency and lowest additive jitter, it is recommended to

use a differential clock with high input slew rate (>1 V/ns) and DC coupling to the CLKin port.

All control pins are configured with the control switch, S3. The output enable logic is shown in Table 4.

Table 4. Output Enable Selection (0=OFF, 1=ON)

CLKout ENABLE MODE S1[3]-OE

Disabled/Hi-Z 0

Enabled 1

Power Supplies

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LMK00105 User’s Guide

4 Power Supplies

By default, Vdd and Vddo are supplied by two external power supplies. To modify the EVK with a different

power supply configuration, populate the resistor options as shown in Table 5. Then, apply the appropriate

voltage(s) to the EVK power input(s).

Decoupling capacitors and 0-ohm resistor footprints, which can accommodate ferrite beads, can be used

to isolate the EVK power input(s) from the device power pins. Do not disconnect or ground any of the

Vddo pins as they are all internally connected inside the device.

Table 5. Power Supply Configuration

DUAL EXTERNAL INPUTS(DEFAULT) SINGLE EXTERNAL INPUT 3.3 V

Vdd input Apply 3.3 V Apply 3.3 V

Vddo input Apply Voltage ≤Vdd Not used

R26 0 ΩDNP

R27 DNP 0 Ω

R28 0 Ω0Ω

5 Clock Inputs

The SMA inputs labeled CLKin &CLKin* are configured to receive a differential clock or single ended

clock. Best performance is achieved with a DC-coupled differential input clock. To configure CLKin for a

single-ended clock remove R8. Then either CLKin or CLKin* may be driven single ended.

5.1 Crystal Oscillator Interface

The LMK00105 has an integrated crystal oscillator interface (OSCin/OSCout) that supports a fundamental

mode, AT-cut crystal. If the crystal input is selected, an optional onboard crystal on either footprint Y1 or

Y2 will start-up and the oscillator clock can be measured on any enabled output.

A crystal with the HC49 footprint can be populated on the bottom side of the PCB. Alternatively, a 3.2 x

2.5 mm crystal can be populated on Y2, located on the top side. Only one crystal footprint should be used

at a time.

The values of C12 and C10 (CEXT) depend on the load capacitance (CL) specified for the crystal. The OSC

input capacitance (CIN) of the device is 1 pF differential, and the trace capacitance (CTRACE) of OSCin and

OSCout is around 1 pF. If the selected crystal is specified for CLof 18 pF, the CEXT is calculated as

follows:

CEXT= (CL–CIN–CTRACE/2) * 2 (1)

CEXT = (18 pF – 1 pF – 1 pF/2) * 2 (2)

CEXT = 33 pF (3)

5.2 Configuring OSCin for a Crystal Mode

To configure the board to use crystal mode remove C15 to disconnect the OSCin Port. Install 0 Ωresistors

on R14 and R9. Install a crystal in either footprint (Y1 or Y2) and install the proper load capacitors in C10

and C12.

6 Clock Outputs

All clock outputs are LVCMOS. In the case that not all outputs are used, any unused outputs should be

left floating.

1 2

LMK00101 Main Schematic

1/9/2012

LMK0105ENG_Sheet1.SchDoc

Sheet Title:

Size: Schematic:

Mod. Date:

File:

Rev:

Sheet: of

Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this

speciﬁcation or any information contained therein. Texas Instruments and/or its licensors do not

warrant that this design will meet the speciﬁcations, will besuitable for your application or ﬁt for

any particular purpose, or will operate in an implementation. T

exas Instruments and/or its

licensors do not warrant that the design is production worthy.You should completely validate

and test your design implementation to conﬁrm the system functionality for your application. http://www.ti.com

Contact: http://www.national.com/support

LMK00105 EVK

Project:

Designed for: Public Release

870600754 X1

Assembly Variant: Customer

CLKin*

142-0701-851

CLKin

142-0701-851

100

GND

R12

DNP 51

R13

DNP

R10

DNP

R24

DNP

VDDO

GND

VDD

VDDO

5.6pF

C10

DNP

5.6pF

C12

DNP

R14

DNP

OSCin

142-0701-851

0.1 F

C15

R20

GND

40 MHz

DNP

R19

R18

GND

0.1 F

C11

DNP

GND

R25

DNP

0.1 F

GND GND

GND

CLKout3

142-0701-851

GND

CLKout2

142-0701-851

GND

CLKout4

142-0701-851

GND

0.1 F

C18

CLKout0

142-0701-851

GND

0.1 F

C19

GND

CLKout1

142-0701-851

GND

VDD

10 F

1 F

0.01 F

GND

VDD

SEL

C1_P

C1_N

Cin_N

Cin_P

GND

VDDO

GND GND

GND

100

DNP

100

R11

DNP

0R17

0R21

A6S-4104-H

R22

R23

R16

Note: Parts with Designators greater than or equal to 300 are on the bottom side.

100pF

C16

GND

100pF

C17

GND

100pF

GND

100pF

GND

Vddo

CLKout0

GND

CLKout1

Vddo

GND 7

Vdd 8

GND

OSCout 10

GND 11

GND 12

CLKout2 13

Vddo 14

CLKout3 15

GND 16

OSCin 9

Vddo 18

GND

CLKin*

CLKin

SEL

Vdd

CLKout4 17

DAP 25

LMK00105

GND

100pF

C14

GND

VDD

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Schematics

SNLU097A–March 2012–Revised July 2019

LMK00105 User’s Guide

7 Schematics

Figure 2. Schematic Sheet 1

2 2

LMK00101 Power Supply

1/9/2012

LMK0105ENG_Sheet2.SchDoc

Sheet Title:

Size: Schematic:

Mod. Date:

File:

Rev:

Sheet: of

Texas Instruments and/or its licensors do not warrant the accur

acy or completeness of this

speciﬁcation or any information contained therein. Texas Instruments and/or its licensors do not

warrant that this design will meet the speciﬁcations, will besuitable for your application or ﬁt for

any particular purpose, or will operate in an implementation. T

exas Instruments and/or its

licensors do not warrant that the design is production worthy.You should completely validate

and test your design implementation to conﬁrm the system functionality for your application. http://www.ti.com

Contact: http://www.national.com/support

LMK00105 EVK

Project:

Designed for: Public Release

870600754 X1

Assembly Variant: Customer

600754 001

551

PCB Part Number: REV A

Vdd

142-0701-851

Vdd_TB

TERMBLOCK_2

DNP

R29

R30

DNP

Vdd_In

ADJ 6

GND 3

DAP

OUT 5

BYP 1

LP3878SD-ADJ/NOPB

DNP

10 F

C23

1 F

C24

0.01 F

C25

GND

VDD

10 F

C304

DNP 10 F

C306

DNP

2200pF

C305

DNP

0.01 F

C307

DNP

51k

R310

DNP 2.00k

R312

DNP

866

R311

DNP

GND

GND TP_VDD_LDO

TP_Vdd

TP_Vdd_In

R31

DNP

R309

DNP

ADJ 6

GND 3

DAP

OUT 5

BYP 1

LP3878SD-ADJ/NOPB

DNP

10 F

C300

DNP 10 F

C302

DNP

2200pF

C301

DNP

0.01 F

C303

DNP

51k

R306

DNP 1.30k

R308

DNP

866

R307

DNP

GND

TP_VDDO_LDO

R27

DNP

1 F

C21

VDDO

10 F

C20

R28

DNP

Vddo

142-0701-851

R26

GND

TP_Vddo

SO1

0.375" Standoﬀ

SO2

0.375" Standoﬀ

SO3

0.375" Standoﬀ

SO4

0.375" Standoﬀ

0.1 F

C22

GND

Resistor Combinations for Diﬀerent Output Voltages

R116 and R151 = Ra

R117 and R152 = Rb

Output Voltage Ra Rb

3.3 V 10.7 kOhms 4.7 kOhms

2.5 V 7 kOhms 4.7 kOhms

1.8 V 2.7 kOhms 4.7 kOhms

1.5 V 2.4 kOhms 4.7 kOhms

Vddo_TB

TERMBLOCK_2

DNP

SO5

0.375" Standoﬀ

SO6

0.375" Standoﬀ

LOGO

PCB

Texas Instruments

LOGO

PCB

ESD Susceptible

Schematics

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Figure 3. Schematic Sheet 2

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PCB Layout

SNLU097A–March 2012–Revised July 2019

LMK00105 User’s Guide

8 PCB Layout

Figure 4. PCB Top

PCB Layout

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Figure 5. Bottom Side (Layer Inverted, Not to Scale)

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Bill of Materials

SNLU097A–March 2012–Revised July 2019

LMK00105 User’s Guide

9 Bill of Materials

Table 6. Bill of Materials

ITEM DESCRIPTION QTY DESIGNATOR MANUFACTURER

1CAP, CERM, 0.1uF, 16V, +/-10%, X7R,

0603 8 C1, C2, C3, C9, C11, C15, C18, C19 TDK

2CAP, CERM, 10uF, 10V, +/-10%, X5R,

0805 3 C4, C20, C23 MuRata

3 CAP, CERM, 1uF, 16V, +/-10%, X7R, 0603 3 C5, C21, C24 TDK

4CAP, CERM, 0.01uF, 100V, +/-5%, X7R,

0603 2 C6, C25 Kemet

5CAP, CERM, 100pF, 50V, +/-5%,

C0G/NP0, 0603 5 C7, C8, C14, C16, C17 AVX

6CAP, CERM, 0.1uF, 16V, +80/-20%, Y5V,

0603 1 C22 TDK

7 Connector, SMT, End launch SMA 50 ohm 10 CLKin, CLKin*, CLKout0, CLKout1,

CLKout2, CLKout3, CLKout4, OSCin,

Vdd, Vddo Emerson Network

Power Connectivity

8 RES, 0 ohm, 5%, 0.1W, 0603 13 R4, R5, R6, R10, R16, R17, R18,

R19, R21, R22, R23, R26, R29 Vishay-Dale

9 RES, 100 ohm, 5%, 0.1W, 0603 1 R8 Vishay-Dale

10 RES, 51 ohm, 5%, 0.1W, 0603 1 R20 Vishay-Dale

11 DIP Switch, 4 position slide actuatoor,

SPST, SMD 1 S1 Omron Electronic

Components

12 0.375" Standoff 6 SO1, SO2, SO3, SO4, SO5, SO6

13 Testpoint NA TP_Vdd, TP_Vdd_In, TP_VDD_LDO,

TP_Vddo, TP_VDDO_LDO NA

14 LMK00105 1 U1 Texas Instruments

15 CAP, CERM, 5.6pF, 50V, +/-5%,

C0G/NP0, 0603 0 C10, C12 AVX

16 CAP, CERM, 10uF, 10V, +/-10%, X5R,

0805 0 C300, C302, C304, C306 MuRata

17 CAP, CERM, 2200pF, 100V, +/-5%, X7R,

0603 0 C301, C305 AVX

18 CAP, CERM, 0.01uF, 25V, +/-5%,

C0G/NP0, 0603 0 C303, C307 TDK

19 RES, 51 ohm, 5%, 0.1W, 0603 0 R1, R2, R3, R12, R13, R24, R25 Vishay-Dale

20 RES, 100 ohm, 5%, 0.1W, 0603 0 R7, R11 Vishay-Dale

21 RES, 0 ohm, 5%, 0.1W, 0603 0 R9, R14, R27, R28, R30, R31, R309 Vishay-Dale

22 RES, 51k ohm, 5%, 0.1W, 0603 0 R306, R310 Vishay-Dale

23 RES, 866 ohm, 1%, 0.1W, 0603 0 R307, R311 Vishay-Dale

24 RES, 1.30k ohm, 1%, 0.1W, 0603 0 R308 Vishay-Dale

25 RES, 2.00k ohm, 1%, 0.1W, 0603 0 R312 Vishay-Dale

26 Micropower 800mA Low Noise "Ceramic

Stable" Adjustable Voltage Regulator for

1V to 5V Applications, 8-pin LLP, Pb-Free 0 U2, U3 Texas Instruments

27 Crystal, xxxMHz, xxpF 0 Y1

28 Crystal, Citizen CS325, 52 MHz 0 Y2 Citizen

Revision History

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Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (March 2012) to A Revision ....................................................................................................... Page

• Changed document throughout.......................................................................................................... 2

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