Texas Instruments Bq25606 Manual de usuario

SLUUBL3–June 2017

bq25606 PWR772 Evaluation Module

User's Guide

SLUUBL3–June 2017

bq25606 PWR772 Evaluation Module

This user's guide provides detailed testing instructions for the bq25606 evaluation module (EVM). Also

included are descriptions of the necessary equipment, equipment setup, test procedures, the printed-

circuit board layouts, schematics, and the bill of materials (BOM).

Throughout this user's guide, the abbreviations EVM,bq25606EVM,PWR772, and the term evaluation

module are synonymous with the bq25606 evaluation module, unless otherwise noted.

Contents

1 Introduction ................................................................................................................... 2

1.1 EVM Features....................................................................................................... 2

1.2 I/O Descriptions..................................................................................................... 2

2 Test Summary................................................................................................................ 3

2.1 Equipment ........................................................................................................... 3

2.2 Equipment Setup.................................................................................................... 3

2.3 Test Procedure...................................................................................................... 5

3 PCB Layout Guideline....................................................................................................... 6

4 Board Layout, Schematic, and Bill of Materials.......................................................................... 7

4.1 Board Layout ........................................................................................................ 7

4.2 Schematic............................................................................................................ 9

4.3 Bill of Materials .................................................................................................... 10

List of Figures

1 Original Test Setup for bq25606 EVM.................................................................................... 4

2 bq25606EVM Top Overlay ................................................................................................. 7

3 bq25606EVM Top Solder Mask............................................................................................ 7

4 bq25606EVM Top Layer ................................................................................................... 7

5 bq25606EVM Signal Layer 1 .............................................................................................. 7

6 bq25606EVM Signal Layer 2 .............................................................................................. 7

7 bq25606EVM Bottom Layer ............................................................................................... 7

8 bq25606EVM Bottom Solder Mask........................................................................................ 8

9 bq25606EVM Bottom Overlay ............................................................................................. 8

10 Schematic for bq25606EVM-772 .......................................................................................... 9

List of Tables

1 Device Data Sheets ......................................................................................................... 2

2 EVM Connections............................................................................................................ 2

3 EVM Jumper Connections and Shunt Installation....................................................................... 2

4 Recommended Operating Conditions..................................................................................... 3

5 bq25606EVM-772 Bill of Materials....................................................................................... 10

Trademarks

All trademarks are the property of their respective owners.

Introduction

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1 Introduction

1.1 EVM Features

For detailed features and operation, refer to Table 1 for a list of devices and their data sheets.

Table 1. Device Data Sheets

Device Data Sheet EVM Label Variant

bq25606 SLUSCK6 BQ25606EVM-772 004

The bq25606 evaluation module (EVM) is a standalone charger module without I2C control.

1.2 I/O Descriptions

Table 2 lists the jumper connections available on this EVM.

Table 2. EVM Connections

Jack Description

J1-VAC Input positive terminal

J1-GND Ground Input: negative terminal (ground terminal)

J2-PMID PMID pin connection

J2-GND Ground

J3 Output mini-USB port

J4-SYS Connected to system

J4-GND Ground

J5-BATSNS_ICHG BATSNS or ICHG pin connection

J5-BAT Connected to battery pack positive node

J5-GND Ground

J6 I2C 4-pin connector

J7 USB-TO-GPIO connector (Not populated)

Table 3 lists the EVM jumper connections.

Table 3. EVM Jumper Connections and Shunt Installation

Jack Description bq25606 Setting

JP1 PSEL pin selection Not installed

JP2 CE pin setting: pull low to enable the charge Installed

JP3 OTG pin setting: pull high to enable OTG mode Short OTG to GND

JP4 STAT, PG, CE, INT, and OTG pins pullup source (SYS or

BAT) Short to SYS

JP5 TS pin to GND Not installed

JP6 TS resistor divider pullup source (REGN) connection Installed

JP7 Internal 10 kΩto GND to TS pin Installed

JP8 BATSNS selection Not installed

JP9 QON and VSET pin setting Not installed

JP10 STAT pin setting Installed

JP11 Add SYS cap Not installed

JP12 SDA and PG pin setting Installed

JP13 D+ and PSEL to J3 Not Installed

JP14 D– and PG to J3 Not Installed

JP15 D– and PG pin setting Not installed

JP16 Add VBUS cap Not installed

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Test Summary

SLUUBL3–June 2017

bq25606 PWR772 Evaluation Module

Table 3. EVM Jumper Connections and Shunt Installation (continued)

Jack Description bq25606 Setting

JP17 Add PMID cap Not installed

JP18 Add AT cap Not installed

S1 QON control Default open

S2 Switch to short indicator LEDs Default open

Table 4 lists the recommended operating conditions for this EVM.

Table 4. Recommended Operating Conditions

Symbol Description MIN TYP MAX Unit

Supply voltage, VVBUS Input voltage from AC adapter 3.9 5.0 13.5 V

Battery voltage, VBAT Voltage applied at VBAT terminal 0 4.208 4.4 V

IBAT Fast charging current 0 3.0 A

Discharging current through internal MOSFET 6.0 A

Supply current, IIN Maximum input current from AC adapter input 0 3.0 A

2 Test Summary

2.1 Equipment

This section includes a list of supplies required for testing this EVM.

1. Power Supplies: Power supply #1 (PS#1): a power supply capable of supplying 5 V at 3 A is required.

While this part can handle larger voltage and current, it is not necessary for this procedure.

2. Load #1: (4-quadrant supply, constant voltage < 4.5 V) A 0–20 V, 0–5 A, > 30-W system, DC

electronic load and setting as constant voltage load mode

or:

Kepco load: BOP 20–5M, DC 0 to ±20 V, 0 to ±5 A (or higher)

3. Load #2: Use with Boost Mode

VAC to GND load, 10 Ω, 5 W or greater.

4. Meters: Six Fluke 75 multimeters, (equivalent or better)

or:

Four equivalent voltage meters and two equivalent current meters. The current meters must be

capable of measuring 5-A+ current

2.2 Equipment Setup

Use the following list to set up the equipment:

1. Set PS#1 for 5-V DC, 3-A current limit and then turn off the supply.

2. Connect the output of PS#1 in series with a current meter (multimeter) to J1 (VAC and GND). It is

recommended to connect one voltage meter across TP24 and TP27 to measure the input current

sensing resistor voltage. The sensing resistor is 10 mΩ.

3. Connect one voltage meter across TP21 (VAC) and TP18 (GND), connect another voltage meter

across TP1 (VBUS) and TP18 (GND).

4. Turn on Load #1, set to constant voltage mode and output to 2.5 V. Turn off (disable) load. Connect

load to J5 (BAT and GND).

5. Connect one voltage meter across TP9 (BAT) and TP17 (GND) to measure the battery voltage and

another voltage meter across TP28 and TP29 to measure the battery current sensing resistor voltage.

The sensing resistor is 10 mΩ. An alternate method is to use the optional current meter in series to

measure the battery current.

6. Install shunts as shown in Table 3.

Test Summary

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Figure 1. Original Test Setup for bq25606 EVM

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Test Summary

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bq25606 PWR772 Evaluation Module

2.3 Test Procedure

2.3.1 Charger Mode Verification

1. Enable Load #1 from Section 2.2, step 4. Measure the voltage across J4 and J5 as follows:

•Measure →V(TP8(SYS), TP17(GND)) = 3.65 V (Typical)

•Measure →V(TP9(BAT), TP17(GND)) = 2.5 V (Typical)

•Measure →IBAT ( = pre-charge current)

2. Change Load #1 to 3.7 V

•Measure →V(TP8(SYS), TP17(GND)) = 3.8 V (Typical)

•Measure →V(TP9(BAT), TP17(GND)) = 3.7 V (Typical)

•Measure →IBAT ( = fast charge current)

3. Adjust R10 to change charging current

Adjust R11 to change input current limit

4. Turn off and disconnect Load #1

5. Turn off and disconnect PS#1

2.3.2 Boost Mode Verification

1. Do not install JP3

2. If the constant voltage load connected from BAT to GND is not a four-quadrant supply (sources

current), remove the load and use the power source disconnected in step 1, set to 3.7 V and 2-A

current limit and connect between BAT and GND

3. Apply 10 Ω(5 W or greater) across J1 VAC(+) to GND(–)

4. Verify VVBUS to GND since VBUS is the actual boost mode output voltage

Measure →VVBUS = 5.15 V (Typical)

5. Turn off and disconnect power supply

6. Remove 10-Ωresistor at VAC

2.3.3 Helpful Tips

1. The leads and cables to the various power supplies, batteries, and loads have resistance. The current

meters also have series resistance. The charger dynamically reduces charge current depending on the

voltage sensed at its VBUS pin (using the VINDPM feature), BAT pin (as part of normal termination),

and TS pin (through its battery temperature monitoring feature via battery thermistor). Therefore,

voltmeters must be used to measure the voltage as close to the IC pins as possible instead of relying

on the digital readouts of the power supply. If a battery thermistor is not available, make sure shunts

JP6 and JP7 are in place.

2. When using a source meter that can source and sink current as your battery simulator, TI highly

recommends adding a large (1000+ μF) capacitor at the EVM BAT and GND connectors in order to

prevent oscillations at the BAT pin due to mismatched impedances of the charger output and source

meter input within their respective regulation loop bandwidths. Configuring the source meter for 4-wire

sensing eliminates the need for a separate voltmeter to measure the voltage at the BAT pin.

When using 4-wire sensing, always ensure that the sensing leads are connected in order to prevent

accidental overvoltage by the power leads.

3. For precise measurements of charge current and battery regulation near termination, the current meter

in series with the battery or battery simulator should not be set to auto-range and may need be

removed entirely. An alternate method for measuring charge current is to either use an oscilloscope

with Hall effect current probe or place a 1% or better, thermally capable (for example, 0.010 Ωin 1210

or larger footprint) resistor in series between the BAT pin and battery and measure the voltage across

that resistor. The bq25606EVM has the sensing resistors onboard.

PCB Layout Guideline

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3 PCB Layout Guideline

Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the

components minimizing high-frequency current path loop is important to prevent electrical and magnetic

field radiation and high-frequency resonant problems. This PCB layout priority list must be followed in the

order presented for proper layout:

1. Place the input capacitor as close as possible to the PMID pin and GND pin connections and use the

shortest copper trace connection or GND plane.

2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this

trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the

charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic

capacitance from this area to any other trace or plane.

3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a

short copper trace connection or GND plane.

4. Route analog ground separately from the power ground. Connect analog ground and connect power

ground separately. Connect analog ground and power ground together using a power pad as the

single ground connection point or use a 0-Ωresistor to tie analog ground to power ground.

5. Use a single ground connection to tie the charger power ground to the charger analog ground just

beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise

coupling.

6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.

7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB

ground. Ensure that there are sufficient thermal vias directly under the IC connecting to the ground

plane on the other layers.

8. The via size and number should be enough for a given current path.

See the EVM design for the recommended component placement with trace and via locations. For the

QFN information, refer to Quad Flatpack No-Lead Logic Packages (SCBA017) and QFN/SON PCB

Attachment (SLUA271).

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Board Layout, Schematic, and Bill of Materials

SLUUBL3–June 2017

bq25606 PWR772 Evaluation Module

4 Board Layout, Schematic, and Bill of Materials

4.1 Board Layout

Figure 2 through Figure 9 illustrate the EVM PCB layout images.

Figure 2. bq25606EVM Top Overlay Figure 3. bq25606EVM Top Solder Mask

Figure 4. bq25606EVM Top Layer Figure 5. bq25606EVM Signal Layer 1

Board Layout, Schematic, and Bill of Materials

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Figure 6. bq25606EVM Signal Layer 2 Figure 7. bq25606EVM Bottom Layer

Figure 8. bq25606EVM Bottom Solder Mask Figure 9. bq25606EVM Bottom Overlay

1 2

3 4

5 6

7 8

9 10

DNP

R21

DNP

200

R19

DNP

200

R20

DNP SDA_/PG

SCL_OTG

PGND

VBUS 1

D- 2

D+ 3

ID 4

GND 5

VAC

PGND

SCL_OTG

SDA_/PG

/CE

D+_PSEL

PGND

VAC

GND

PMID

GND

Vbus: 3.9V to 14V

1000pF

DNP

2.21kR4

10.0k

R5DNP

JP3

/CE

AGND

TP2TP1

1µF

TP3 TP4 TP7

13V

DNP

2.21k

R17

30.1k

R23

R26

DNP

0.1µF

C11

DNP

System

GND

PGND

Battery

PGND

PULL-UP

GND

10µF

C10

10µF

C19

DNP

20V

DNP

ICHG: 0 ~ 2.5A

40V

DNP

0.047µF

R25

TP6

BATSNS_ICHG

PGND

1µH

DNP

4.7k

R15

DNP

AGND

DNP

STAT_/IMON

REGN

CSD17571Q2

5,6,8 4,7

1,2,

PGND

JP16

DNP

JP17

DNP

PGND

1µF

C18

DNP

SCL_OTG

SDA_/PG

VBUS PMID

VAC

ACDRV

VAC

SDA_/PG

D+_PSEL

D-_/PG

10k ohm

R10

PGND

/CE

10K

20V

DNP

JP1

AGND

10.0k

REGN

D+_PSEL

JP2

/CE

AGND

PMID

10µF

DNP

10µF

C17

DNP

10µF

1000pF

DNP

4.7µF

AGND

PMID

/QON_VSET

JP5

10.0k

R24

5.23k

R22

JP6

REGN

JP7

REGN

110pF

DNP

INT_ILIM

AGND

SW1

DNP

PGND

JP4

PULL-UP

JP18

DNP

JP11

DNP

1000pF

C12

DNP

10µF

C13

4.7µF

C20

DNP

4.7µF

C14

DNP

NT1

Net-Tie

R16

DNP

Green

REGN

RTOP TS

PSEL

GND

REGN

/CE

GND

OTG

TP9

TP8

SYS

BAT

SYS

TP5

REGN BATSNS_ICHG INT_ILIMSCL_OTG

TP10 TP11

TP12 TP13

D-_/PGACDRV

TP14 TP15

/QON_VSETD+_PSEL

TP16

/CE

TP17 TP18 TP19 TP20

AGND

PGND

BAT

SYS

PULLUP

AGND

10k ohm

R11

PULL-UP

SW3

DNP

SW4

DNP

SW2

DNP

BAT

SYS

PMID

JP13

SCL_OTG

JP9

AGND

/QON_VSET

1µF

C15

0.1µF

C16

AGND

DNP

STAT_/IMON

BATSNS_ICHG

BTST

JP10

2.21k

Green

JP12

SDA_/PG

TP21

VAC

R27

D-_/PG

10.0k

R29

PGND

D-_/PG

VBUS

AGND

JP14

JP15

DNP

10.0k

R13

DNP PULL-UP

10.0k

R14

TP22 TP23

0.01

R31

158

R12

1.00k

221

2.80k

JP8

DNP BATSNS_ICHG

BAT

BATCON

0.01

R30

40V

TP24

0.01

R18

TP27

TP25 TP26

TP28

TP29

1µH

ACDRV

BAT 13

BAT 14

ICHG 10

BTST 21

PAD 25

PGND 17

PGND 18

PMID

D+

REGN 22

OTG

STAT 5

SW 19

SW 20

SYS 15

SYS 16

TS 11

VBUS

VAC

9ILIM 8

D-

VSET 12

bq25606RGER

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Board Layout, Schematic, and Bill of Materials

SLUUBL3–June 2017

bq25606 PWR772 Evaluation Module

4.2 Schematic

Figure 10 illustrates the schematic for the bq25606 EVM.

Figure 10. Schematic for bq25606EVM-772

Board Layout, Schematic, and Bill of Materials

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4.3 Bill of Materials

Table 5 lists the bq25606EVM-772 BOM.

Table 5. bq25606EVM-772 Bill of Materials

Designator Qty Value Description Package Reference Part Number Manufacturer Alternate Part

Number Alternate

Manufacturer

!PCB 1 Printed Circuit Board PWR772 Any

C1 1 1uF CAP, CERM, 1 µF, 35 V, +/- 10%, X5R, 0603 0603 GMK107BJ105KA-T Taiyo Yuden

C4 1 10uF CAP, CERM, 10 µF, 25 V, +/- 10%, X7S, 0805 0805 GRM21BC71E106KE11L Murata

C6 1 4.7uF CAP, CERM, 4.7 µF, 16 V, +/- 10%, X5R, 0603 0603 GRM188R61C475KAAJ Murata

C7 1 0.047u

FCAP, CERM, 0.047 µF, 25 V, +/- 10%, X7R, 0402 0402 GRM155R71E473KA88D Murata

C9, C10, C13 3 10uF CAP, CERM, 10 µF, 10 V, +/- 10%, X7R, 0805 0805 GRM21BR71A106KE51L Murata

C15 1 1uF CAP, CERM, 1 µF, 25 V, +/- 10%, X7R, 0805 0805 GRM219R71E105KA88D Murata

C16 1 0.1uF CAP, CERM, 0.1 µF, 25 V, +/- 10%, X7R, 0402 0402 GRM155R71E104KE14D Murata

D4, D5 2 Green LED, Green, SMD 1.6x0.8x0.8mm LTST-C190GKT Lite-On

D7 1 40V Diode, Schottky, 40 V, 0.38 A, SOD-523 SOD-523 ZLLS350TA Diodes Inc.

J1, J2, J4 3 Conn Term Block, 2POS, 3.81mm, TH 2POS Terminal Block 1727010 Phoenix Contact

J3 1 Connector, Receptacle, Micro-USB Type B, R/A, Bottom Mount

SMT 7.5x2.45x5mm 0473460001 Molex

J5 1 Terminal Block Receptacle, 3x1, 3.81mm, R/A, TH Term Block, 3 pos 1727023 Phoenix Contact

J6 1 Header (friction lock), 100mil, 4x1, R/A, TH 4x1 R/A Header 22-05-3041 Molex

JP1, JP4, JP9 3 Header, 100mil, 3x1, Tin, TH Header, 3 PIN, 100mil, Tin PEC03SAAN Sullins Connector

Solutions

JP2, JP3, JP5, JP6, JP7,

JP10, JP12, JP13, JP14 9 Header, 100mil, 2x1, Tin, TH Header, 2 PIN, 100mil, Tin PEC02SAAN Sullins Connector

Solutions

L2 1 1uH Inductor, 1 µH, 3.2 A, 0.028 ohm, SMD 2.5x2mm MPIM252010F1R0M-LF Microgate

LBL1 1 Thermal Transfer Printable Labels, 0.650" W x 0.200" H - 10,000

per roll PCB Label 0.650"H x 0.200"W THT-14-423-10 Brady

Q1 1 30V MOSFET, N-CH, 30 V, 22 A, DQK0006C (WSON-6) DQK0006C CSD17571Q2 Texas Instruments None

R2, R25, R27 3 0 RES, 0, 5%, 0.063 W, 0402 0402 CRCW04020000Z0ED Vishay-Dale

R3 1 1.00k RES, 1.00 k, 1%, 0.063 W, 0402 0402 CRCW04021K00FKED Vishay-Dale

R4, R7, R17 3 2.21k RES, 2.21 k, 1%, 0.063 W, 0402 0402 CRCW04022K21FKED Vishay-Dale

R6, R14, R24, R29 4 10.0k RES, 10.0 k, 1%, 0.063 W, 0402 0402 CRCW040210K0FKED Vishay-Dale

R8 1 221 RES, 221, 1%, 0.063 W, 0402 0402 CRCW0402221RFKED Vishay-Dale

R9 1 2.80k RES, 2.80 k, 1%, 0.063 W, 0402 0402 CRCW04022K80FKED Vishay-Dale

R10, R11 2 10k

ohm Trimmer, 10k ohm, 0.25W, TH 4.5x8x6.7mm 3266W-1-103LF Bourns

R12 1 158 RES, 158, 1%, 0.063 W, 0402 0402 CRCW0402158RFKED Vishay-Dale

R18, R30, R31 3 0.01 RES, 0.01, 1%, 1 W, 2010 2010 WSL2010R0100FEA18 Vishay-Dale

R22 1 5.23k RES, 5.23 k, 1%, 0.063 W, 0402 0402 CRCW04025K23FKED Vishay-Dale

R23 1 30.1k RES, 30.1 k, 1%, 0.063 W, 0402 0402 CRCW040230K1FKED Vishay-Dale

S2 1 Switch, SPST, 2 Pos, 25mA, 24VDC, SMD 3.71x5.8mm 218-2LPST CTS Electrocomponents

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