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OMAP-L137 Low-Power Applications Processor

1 OMAP-L137 Low-Power Applications Processor

1.1 Features

1• Supports up to Four SP Additions Per Clock,

• Software Support Four DP Additions Every 2 Clocks

– TI DSP/BIOS™ • Supports up to Two Floating-Point (SP or

– Chip Support Library and DSP Library DP) Reciprocal Approximation (RCPxP) and

• Dual Core SoC Square-Root Reciprocal Approximation

– 375- and 456-MHz ARM926EJ-S™ RISC MPU (RSQRxP) Operations Per Cycle

– 375- and 456-MHz C674x VLIW DSP – Two Multiply Functional Units

• ARM926EJ-S Core • Mixed-Precision IEEE Floating Point Multiply

– 32-Bit and 16-Bit (Thumb®) Instructions Supported up to:

– DSP Instruction Extensions – 2 SP x SP -> SP Per Clock

– Single Cycle MAC – 2 SP x SP -> DP Every Two Clocks

– ARM® Jazelle® Technology – 2 SP x DP -> DP Every Three Clocks

– Embedded ICE-RT™ for Real-Time Debug – 2 DP x DP -> DP Every Four Clocks

• ARM9™ Memory Architecture • Fixed-Point Multiply Supports Two 32 x 32-

– 16KB of Instruction Cache Bit Multiplies, Four 16 x 16-Bit Multiplies, or

Eight 8 x 8-Bit Multiplies per Clock Cycle,

– 16KB of Data Cache and Complex Multiples

– 8KB of RAM (Vector Table) – Instruction Packing Reduces Code Size

– 64KB of ROM – All Instructions Conditional

• C674x Instruction Set Features – Hardware Support for Modulo Loop

– Superset of the C67x+ and C64x+ ISAs Operation

– Up to 3648 MIPS and 2736 MFLOPS C674x – Protected Mode Operation

– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) – Exceptions Support for Error Detection and

– 8-Bit Overflow Protection Program Redirection

– Bit-Field Extract, Set, Clear • 128KB of RAM Shared Memory

– Normalization, Saturation, Bit-Counting • 3.3-V LVCMOS I/Os (Except for USB Interfaces)

– Compact 16-Bit Instructions • Two External Memory Interfaces:

• C674x Two-Level Cache Memory Architecture – EMIFA

– 32KB of L1P Program RAM/Cache • NOR (8- or 16-Bit-Wide Data)

– 32KB of L1D Data RAM/Cache • NAND (8- or 16-Bit-Wide Data)

– 256KB of L2 Unified Mapped RAM/Cache • 16-Bit SDRAM with 128-MB Address Space

– Flexible RAM/Cache Partition (L1 and L2) – EMIFB

• Enhanced Direct Memory Access Controller 3 • 32-Bit or 16-Bit SDRAM with 256-MB

(EDMA3): Address Space

– 2 Transfer Controllers • Three Configurable 16550-Type UART Modules:

– 32 Independent DMA Channels – UART0 with Modem Control Signals

– 8 Quick DMA Channels – Autoflow Control Signals (CTS, RTS) on UART0

– Programmable Transfer Burst Size Only

• TMS320C674x Fixed- and Floating-Point VLIW – 16-Byte FIFO

DSP Core – 16x or 13x Oversampling Option

– Load-Store Architecture with Nonaligned • LCD Controller

Support • Two Serial Peripheral Interfaces (SPIs) Each with

– 64 General-Purpose Registers (32-Bit) One Chip Select

– Six ALU (32- and 40-Bit) Functional Units • Multimedia Card (MMC)/Secure Digital (SD) Card

• Supports 32-Bit Integer, SP (IEEE Single Interface with Secure Data I/O (SDIO)

Precision/32-Bit) and DP (IEEE Double

Precision/64-Bit) Floating Point

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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• Two Master and Slave Inter-Integrated Circuit (I2C • 10/100 Mbps Ethernet MAC (EMAC):

Bus™) – IEEE 802.3 Compliant (3.3-V I/O Only)

• One Host-Port Interface (HPI) with 16-Bit-Wide – RMII Media-Independent Interface

Muxed Address/Data Bus for High Bandwidth – Management Data I/O (MDIO) Module

• Programmable Real-Time Unit Subsystem • Real-Time Clock with 32-kHz Oscillator and

(PRUSS) Separate Power Rail

– Two Independent Programmable Realtime Unit • One 64-Bit General-Purpose Timer (Configurable

(PRU) Cores as Two 32-Bit Timers)

• 32-Bit Load and Store RISC Architecture • One 64-Bit General-Purpose Watchdog Timer

• 4KB of Instruction RAM per Core (Configurable as Two 32-Bit General-Purpose

Timers)

• 512 Bytes of Data RAM per Core • Three Enhanced Pulse Width Modulators

• PRUSS can be Disabled via Software to (eHRPWMs):

Save Power – Dedicated 16-Bit Time-Base Counter with

– Standard Power-Management Mechanism Period and Frequency Control

• Clock Gating – 6 Single Edge, 6 Dual Edge Symmetric, or 3

• Entire Subsystem Under a Single PSC Clock Dual Edge Asymmetric Outputs

Gating Domain – Dead-Band Generation

– Dedicated Interrupt Controller – PWM Chopping by High-Frequency Carrier

– Dedicated Switched Central Resource – Trip Zone Input

• USB 1.1 OHCI (Host) with Integrated PHY (USB1) • Three 32-Bit Enhanced Capture (eCAP) Modules:

• USB 2.0 OTG Port with Integrated PHY (USB0) – Configurable as 3 Capture Inputs or 3 Auxiliary

– USB 2.0 High- and Full-Speed Client Pulse Width Modulator (APWM) Outputs

– USB 2.0 High-, Full-, and Low-Speed Host – Single-Shot Capture of up to Four Event Time-

– End Point 0 (Control) Stamps

– End Points 1,2,3,4 (Control, Bulk, Interrupt or • Two 32-Bit Enhanced Quadrature Encoder Pulse

ISOC) RX and TX (eQEP) Modules

• Three Multichannel Audio Serial Ports (McASPs): • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA)

– Six Clock Zones and 28 Serial Data Pins [ZKB Suffix], 1.0-mm Ball Pitch

– Supports TDM, I2S, and Similar Formats • Commercial, Industrial, Extended, or Automotive

– DIT-Capable (McASP2) Temperature

– FIFO Buffers for Transmit and Receive

1.2 Applications

• A/V Receivers • Home Theatre Systems

• Automotive Amplifiers • Professional Audio

• Soundbars • Network Streaming Audio

1.3 Description

The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a

TMS320C674x DSP core. It consumes significantly lower power than other members of the

TMS320C6000™ platform of DSPs.

The OMAP-L137 device enables original-equipment manufacturers (OEMs) and original-design

manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich

user interfaces, and high processing performance life through the maximum flexibility of a fully integrated

mixed processor solution.

The dual-core architecture of the OMAP-L137 device provides benefits of both DSP and Reduced

Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core

and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and

processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and

memory system can operate continuously.

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The ARM core has a coprocessor 15 (CP15), protection module, and data and program Memory

Management Units (MMUs) with table look-aside buffers. The ARM core has separate 16-KB instruction

and 16KB of data caches. Both memory blocks are four-way associative with virtual index virtual tag

(VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P)

is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative

cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between

program and data space. L2 memory can be configured as mapped memory, cache, or combinations of

the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB of

RAM shared memory is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output

(MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/12/4

serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as

watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose

input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other

peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width

modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can

be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit

enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an

asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a

higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137

device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps

in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the OMAP-L137 device to easily control peripheral

devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each of the peripherals, see the related sections later in this document

and the associated peripheral reference guides.

The OMAP-L137 device has a complete set of development tools for both the ARM and DSP. These

include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows®

debugger interface for visibility into source code execution.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE

OMAPL137 BGA (256) 17.00 mm x 17.00 mm

(1) For more information on these devices, see Section 8, Mechanical Packaging and Orderable

Information.

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Switched Central Resource (SCR)

BOOT ROM

256KB L2 RAM

32KB

L1 RAM

32KB

L1 Pgm

16KB

I-Cache

16KB

D-Cache

AET

4KB ETB

C674x

DSP CPU

ARM926EJ-S CPU

With MMU

DSP Subsystem

ARM Subsystem

JTAG Interface

System Control

Input

Clock(s)

64KB ROM

8KB RAM

(Vector Table)

Power/Sleep

Controller

Memory

Protection

Multiplexing

RTC/

32-kHz

OSC

PLL/Clock

Generator

w/OSC

General-

Purpose

Timer

General-

Purpose

Timer

(Watchdog)

Serial Interfaces

I C

(2)

2SPI

(2)

UART

(3)

Audio Ports

McASP

w/FIFO

(3)

DMA

Peripherals

Display Internal Memory

LCD

Ctlr 128KB

RAM

External Memory Interfaces

Connectivity

EDMA3

Control Timers

eHRPWM

(3)

eCAP

(3)

eQEP

(2)

(10/100)

EMAC

(RMII)

MDIO

USB1.1

OHCI Ctlr

PHY

USB2.0

OTG Ctlr

PHY

HPI MMC/SD

(8b)

EMIFA(8b/16B)

NAND/Flash

16b SDRAM

EMIFB

SDRAM Only

(16b/32b)

GPIO PRU

Subsystem

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1.4 Functional Block Diagram

Note: Not all peripherals are available at the same time due to multiplexing.

Figure 1-1. OMAP-L137 Functional Block Diagram

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Table of Contents

1 OMAP-L137 Low-Power Applications Processor .16.10 External Memory Interface A (EMIFA) .............. 84

1.1 Features .............................................. 16.11 External Memory Interface B (EMIFB) .............. 95

1.2 Applications........................................... 26.12 Memory Protection Units .......................... 103

1.3 Description............................................ 26.13 MMC / SD / SDIO (MMCSD)....................... 106

1.4 Functional Block Diagram ............................ 46.14 Ethernet Media Access Controller (EMAC)........ 109

2 Revision History ......................................... 66.15 Management Data Input/Output (MDIO)........... 114

6.16 Multichannel Audio Serial Ports (McASP0, McASP1,

3 Device Overview ......................................... 8and McASP2) ...................................... 116

3.1 Device Characteristics................................ 86.17 Serial Peripheral Interface Ports (SPI0, SPI1)..... 129

3.2 Device Compatibility.................................. 96.18 Enhanced Capture (eCAP) Peripheral............. 148

3.3 ARM Subsystem...................................... 96.19 Enhanced Quadrature Encoder (eQEP)

3.4 DSP Subsystem..................................... 12 Peripheral .......................................... 151

3.5 Memory Map Summary ............................. 23 6.20 Enhanced High-Resolution Pulse-Width Modulator

3.6 Pin Assignments .................................... 26 (eHRPWM)......................................... 153

3.7 Terminal Functions.................................. 27 6.21 LCD Controller ..................................... 157

4 Device Configuration.................................. 48 6.22 Timers.............................................. 172

4.1 Boot Modes ......................................... 48 6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) .. 174

4.2 SYSCFG Module.................................... 49 6.24 Universal Asynchronous Receiver/Transmitter

(UART)............................................. 179

4.3 Pullup/Pulldown Resistors .......................... 51 6.25 USB1 Host Controller Registers (USB1.1 OHCI).. 181

5 Device Operating Conditions ........................ 52 6.26 USB0 OTG (USB2.0 OTG) ........................ 182

5.1 Absolute Maximum Ratings Over Operating Case

Temperature Range 6.27 Host-Port Interface (UHPI)......................... 190

(Unless Otherwise Noted) ................................. 52 6.28 Power and Sleep Controller (PSC) ................ 197

5.2 Handling Ratings.................................... 52 6.29 Programmable Real-Time Unit Subsystem

5.3 Recommended Operating Conditions............... 53 (PRUSS) ........................................... 200

5.4 Notes on Recommended Power-On Hours (POH) .54 6.30 Emulation Logic.................................... 203

5.5 Electrical Characteristics Over Recommended 6.31 IEEE 1149.1 JTAG ................................ 210

Ranges of Supply Voltage and Operating Case 6.32 Real Time Clock (RTC) ............................ 212

Temperature (Unless Otherwise Noted) ............ 55 7 Device and Documentation Support.............. 215

6 Peripheral Information and Electrical 7.1 Device Support..................................... 215

Specifications........................................... 56 7.2 Documentation Support............................ 216

6.1 Parameter Information .............................. 56

6.2 Recommended Clock and Control Signal Transition 7.3 Community Resources............................. 217

Behavior............................................. 57 7.4 Trademarks ........................................ 217

6.3 Power Supplies...................................... 57 7.5 Electrostatic Discharge Caution ................... 217

6.4 Reset ................................................ 58 7.6 Glossary............................................ 217

6.5 Crystal Oscillator or External Clock Input........... 61 8 Mechanical Packaging and Orderable

6.6 Clock PLLs .......................................... 63 Information............................................. 218

6.7 Interrupts ............................................ 67 8.1 Thermal Data for ZKB ............................. 218

6.8 General-Purpose Input/Output (GPIO).............. 76 8.2 Packaging Information ............................. 218

6.9 EDMA ............................................... 79

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the changes made to the SPRS563F device-specific data

manual to make it an SPRS563G revision.

Scope: Applicable updates to the OMAP-L137 Low-Power Applications Processor device family,

specifically relating to the OMAP-L137 device, which are all now in the production data (PD) stage of

development, have been incorporated.

Revision History

SEE ADDITIONS/MODIFICATIONS/DELETIONS

• Turned on Navigation Icons on top of first page.

• Updated Features, Applications, and Description for consistency and translation.

Global • Moved Trademarks information from first page to within Section 7, Device and Documentation Support.

• Moved ESDS Warning to within Section 7, Device and Documentation Support.

Section 1.1 Deleted Highlights section. Information was duplicated elsewhere in Features.

Features

Section 1.2 Added NEW section.

Applications

Section 1.3 Added NEW Device Information Table.

Description Table 3-2, C674x Cache Registers:

Section 3.4.2.4 • Updated/Changed REGISTER DESCRIPTION for BYTE ADDRESSES 0000, 0020, and 0040 from

C674x CPU "...See the System reference Guide..." to "See the Technical Reference Manual..."

Table 3-20, Universal Serial Bus (USB) Terminal Functions:

Section 3.7 • Updated/Changed USB0_VDDA12 DESCRIPTION from "...must always be connected via a 1 μF

Terminal Functions capacitor..." to "...is recommended to be connected via a 0.22-μFcapacitor..."

Section 3.7.11

Universal Table 3-15, Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions:

Asynchronous • Updated/Changed footnote from "...Applications Processor System Reference Guide - Literature Number

Receiver/Transmitter SPRUG84..." to "...C6000 DSP+ARM Processor Technical Reference Manual (SPRUH92)..."

s (UART0, UART1,

UART2)

Section 3.7.22 Moved to within Section 3.7, Terminal Functions

Unused USB0 Table 3-26, Unused USB0 and USB1 Pin Configurations:

(USB2.0) and USB1 • Updated/Changed USB0_VDDA12 Configuration by combining both Configuration columns and

(USB1.1) Pin changing text to "Internal USB0 PHY output connected to an external..."

Configurations Section 5.2, Handling Ratings:

Section 5

Device Operating • Split handling, ratings, and certifications from the Abs Max table and placed in NEW Handling Ratings

Conditions table.

Section 5.4

Notes on Table 5-1, Recommended Power-On Hours:

Recommended • Added Silicon Revision column.

Power-On Hours

(POH) Table 6-24, EMIFA Asynchronous Memory Switching Characteristics:

Section 6.10.6 • Updated/Changed the MIN, NOM, and MAX equations for NO. 3, 10, 15, and 24 from "...(EWC*16)..." to

EMIFA Electrical "...EWC..."

Data/Timing Section 5.3, Recommended Operating Conditions:

• Added "Unless specifically indicated" to "These I/O specifications apply to ..." footnote

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Revision History (continued)

SEE ADDITIONS/MODIFICATIONS/DELETIONS

Table 6-28, EMIFB SDRAM Interface Timing Requirements:

• Updated/Changed Parameter No. 19 from "tsu(DV-CLKH)" to "t(DV-CLKH)"

• Added new column: "CVDD = 1.3V"

• Added new footnote containing "...range rated devices for 456 MHz max CPU operating..."

• Added new footnote containing "...range rated devices for 400/375/300/266/200 MHz max CPU

operating ..."

Table 6-29, EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature

Range:

• Updated/Changed table title from "...Switching Characteristics..." to "...Switching Characteristics for

Commercial (Default) Temperature Range"

Section 6.11.3 • Added new footnote containing "...range rated devices for 456 MHz max CPU operating ..."

EMIFB Electrical • Added new footnote containing "...range rated devices for 400/375/300/266/200 MHz max CPU

Data/Timing operating..."

• Updated/Changed CVDD = 1.3V MIN column values for Parameter No. 4, 6, 8, 10, 12, 14, 16, and 18

from "0.9" to "1.1"

• Updated/Changed CVDD = 1.3V MAX column values for Parameter No. 3, 5, 7, 9, 11, 13, 15, and 17

from "5.1" to "4.25"

• Populated CVDD = 1.2V column with values (was empty)

• Updated/Changed Parameter No. 18 from "tena(CLKH-DLZ)" to "t(CLKH-DLZ)"

Table 6-30, EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive

Temperature Ranges:

• Added NEW table

Table 6-47, McASP Registers Accessed Through DMA Port:

Section 6.16

Multichannel Audio • Updated/Changed Read Accesses Register Description from "XBUSEL = 0 in XFMT" to "RBUSEL = 0 in

Serial Ports RFMT"

(McASP0, McASP1, • Updated/Changed Write Accesses Register Description from "RBUSEL = 0 in RFMT" to "XBUSEL = 0 in

and McASP2) XFMT"

Section 7.6 Added NEW section.

Glossary

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3 Device Overview

3.1 Device Characteristics

Table 3-1 provides an overview of the OMAP-L137 low power applications processor. The table shows

significant features of the device, including the capacity of on-chip RAM, peripherals, and the package

type with pin count.

Table 3-1. Characteristics of the OMAP-L137 Processor

HARDWARE FEATURES OMAP-L137

EMIFB 16/32bit, up to 256MB SDRAM

Asynchronous (8/16-bit bus width) RAM, Flash, 16bit up to 128MB SDRAM, NOR,

EMIFA NAND

Flash Card Interface MMC and SD cards supported.

EDMA3 32 independent channels, 8 QDMA channels, 2 Transfer controllers

2 64-Bit General Purpose (each configurable as 2 separate 32-bit timers, 1 configurable

Timers as Watch Dog)

UART 3 (one with RTS and CTS flow control)

SPI 2 (each with one hardware chip select)

I2C 2 (both Master/Slave)

Multichannel Audio

Peripherals 3 (each with transmit/receive, FIFO buffer, 16/12/4 serializers)

Serial Port [McASP]

Not all peripherals pins 10/100 Ethernet MAC

are available at the with Management Data 1 (RMII Interface)

same time (for more I/O

detail, see the Device

Configurations section). eHRPWM 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs

eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs

eQEP 2 32-bit QEP channels with 4 inputs/channel

UHPI 1 (16-bit multiplexed address/data)

USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY

USB 1.1 (USB1) Full-Speed OHCI (as host) with on-chip PHY

General-Purpose 8 banks of 16-bit

Input/Output Port

LCD Controller 1

PRU Subsystem 2 Programmable PRU Cores

(PRUSS)

Size (Bytes) 488KB RAM

DSP

32KB L1 Program (L1P)/Cache (up to 32KB)

32KB L1 Data (L1D)/Cache (up to 32KB)

256KB Unified Mapped RAM/Cache (L2)

DSP Memories can be made accessible to ARM, EDMA3, and other peripherals.

On-Chip Memory ARM

Organization 16KB I-Cache

16KB D-Cache

8KB RAM (Vector Table)

64KB ROM

ADDITIONAL SHARED MEMORY

128KB RAM

C674x CPU ID + CPU Control Status Register 0x1400

Rev ID (CSR.[31:16])

C674x Megamodule Revision ID Register 0x0000

Revision (MM_REVID[15:0]) 0x0B7D F02F (Silicon Revision 1.0)

JTAG BSDL_ID DEVIDR0 register 0x8B7D F02F (Silicon Revision 1.1)

0x9B7D F02F (Silicon Revisions 3.0, 2.1, and 2.0)

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Table 3-1. Characteristics of the OMAP-L137 Processor (continued)

HARDWARE FEATURES OMAP-L137

674x DSP at 375 MHz(1.2V) or 456 MHz (1.3V)

CPU Frequency MHz ARM926 at 375 MHz(1.2V) or 456 MHz (1.3V)

Core (V) 1.2V / 1.3V

Voltage I/O (V) 3.3 V / 1.8 V (1.8 V for USB only)

Package 17 mm x 17 mm, 256-Ball 1 mm pitch, PBGA (ZKB)

Product Preview (PP),

Advance Information 375 MHz Versions -PD

Product Status(1) (AI), 456 MHz Version - PD

or Production Data

(PD)

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

3.2 Device Compatibility

The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.

The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both

the C64x+ and C67x+ DSP families.

3.3 ARM Subsystem

The ARM Subsystem includes the following features:

• ARM926EJ-S RISC processor

• ARMv5TEJ (32/16-bit) instruction set

• Little endian

• System Control Co-Processor 15 (CP15)

• MMU

• 16KB Instruction cache

• 16KB Data cache

• Write Buffer

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

• ARM Interrupt controller

3.3.1 ARM926EJ-S RISC CPU

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of

ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications

where full memory management, high performance, low die size, and low power are all important. The

ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to

trade off between high performance and high code density. Specifically, the ARM926EJ-S processor

supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,

providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code

overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both

hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a

complete high performance subsystem, including:

• ARM926EJ -S integer core

• CP15 system control coprocessor

• Memory Management Unit (MMU)

• Separate instruction and data caches

• Write buffer

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• Separate instruction and data (internal RAM) interfaces

• Separate instruction and data AHB bus interfaces

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available

at http://www.arm.com

3.3.2 CP15

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and

data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers

are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as

supervisor or system mode.

3.3.3 MMU

A single set of two level page tables stored in main memory is used to control the address translation,

permission checks and memory region attributes for both data and instruction accesses. The MMU uses a

single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The

MMU features are:

• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.

• Mapping sizes are:

– 1MB (sections)

– 64KB (large pages)

– 4KB (small pages)

– 1KB (tiny pages)

• Access permissions for large pages and small pages can be specified separately for each quarter of

the page (subpage permissions)

• Hardware page table walks

• Invalidate entire TLB, using CP15 register 8

• Invalidate TLB entry, selected by MVA, using CP15 register 8

• Lockdown of TLB entries, using CP15 register 10

3.3.4 Caches and Write Buffer

The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following

features:

• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)

• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with

two dirty bits in the Dcache

• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory

region using the C and B bits in the MMU translation tables

• Critical-word first cache refilling

• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,

providing a mechanism for both lockdown, and controlling cache corruption

• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG

RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the

TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the

possibility of TLB misses related to the write-back address.

• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of

the Dcache or Icache, and regions of virtual memory.

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