Texas Instruments TAS2505 Manual de usuario

TAS2505 Application Reference Guide

Reference Guide

Literature Number: SLAU472

February 2013

Chapter 1

SLAU472–February 2013

TAS2505 Device Overview

•Chapter 1: Device Overview

•Chapter 2: TAS2505 Application

•Chapter 3: Device Initialization

•Chapter 4: Example Setups

•Chapter 5: Register Map and Descriptions

space

Features: Applications:

• Digital input mono speaker amp • Portable Audio Devices

• Supports 8-kHz to 96-kHz Sample Rates • White goods

• Mono Class-D BTL Speaker Driver (2.0 W Into • Portable Navigation Devices

4Ωor 1.7 W Into 8 Ω)

• Mono Headphone/Lineout Driver

• Two Single-Ended Inputs With Output Mixing and

Level Control

• Embedded Power-on-Reset

• Integrated LDO

• Programmable Digital Audio Processing Blocks

for Bass Boost, Treble, EQ With up to Six

Biquads for Playback

• Integrated PLL Used for Programmable Digital

Audio Processing Blocks

• I2S, Left-Justified, Right-Justified, DSP, and TDM

Audio Interfaces

• I2C and SPI control with auto-increment

• Full Power-Down Control

• Power Supplies:

– Analog: 1.5 V–1.95 V

– Digital Core: 1.65 V–1.95 V

– Digital I/O: 1.1 V–3.6 V

– Class-D: 2.7 V–5.5 V (SPKVDD ≥AVDD)

• 4mm × 4mm 24-Pin QFN Package

I2C is a trademark of NXP B.V. Corporation.

2TAS2505 Device Overview SLAU472–February 2013

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DIN

BCLK

WCLK

MCLK

SPKVSS

AVSS

SCL/SSZ

SDA/MOSI

GPIO/DOUT

DVSS

AINL

AINR

SPKP

SPKM

HPOUT

RST

MISO

SPI_SEL

SCLK

SPKVDD

AVDD

LDO_SEL

DAC Signal

Proc.

Data

Interface

SPI/I2C

Control Block PLL Interrupt

Control

Primary I2S

Interface

Pin Muxing / Clock Routing

LDO

POR

Supplies

Mono 6

'DAC

DVDD

IOVDD

Secondary I2S

Interface

Dig

Vol

6 dB to +24 dB

(6 dB steps)

-6 dB to +29 dB

and Mute

(1 dB steps)

0 dB to -78 dB

and Mute

(Min 0.5 dB steps)

0 dB to -78 dB

and Mute

(Min 0.5 dB steps)

0 dB to -78 dB and Mute

(Min 0.5 dB steps)

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Description

1.1 Description

The TAS2505 is a low power digital input speaker amp with support for 24-bit digital I2S data mono

playback.

In addition to driving a speaker amp upto 4-Ω, the device also features a mono headphone driver and a

programmable digital-signal processing block. The digital audio data format is programmable to work with

popular audio standard protocols (I2S, left/right-justified) in master, slave, DSP and TDM modes. The

programmable digital-signal processing block can support Bass boost, treble, or EQ functions. An on-chip

PLL provides the high-speed clock needed by the digital signal-processing block. The volume level can be

controlled by register control. The audio functions are controlled using the I2C™ serial bus or SPI bus. The

device includes an on-board LDO that runs off the speaker power supply to handle all internal device

analog and digital power needs. The included POR as power-on-resetcircuit reliably resets the device into

its default state so no external reset is required at normal usage; however, the device does have a reset

pin for more complex system initialization needs. The device also includes two analog inputs for mixing

and muxing in both speaker and headphone analog paths.

Figure 1-1. Simplified Block Diagram

The device can cover operations from 8kHz mono playback to mono 96kHz DAC playback, making it ideal

for portable battery-powered audio and telephony applications. The playback path offers signal processing

blocks for filtering and effects, flexible mixing of analog input signals as well as programmable volume

controls. The voltage supply range for theTAS2505 for analog is 1.5V–1.95V, and for digital it is

1.65V–1.95V. To ease system-level design, a low-dropout regulator (LDO) is integrated to generate the

appropriate analog supply from input voltages ranging from 2.7V to 5.5V. Digital I/O voltages are

supported in the range of 1.1V–3.6V. The required internal clock of the TAS2505 can be derived from

SLAU472–February 2013 TAS2505 Device Overview

DIN

BCLK

WCLK

MCLK

SPKVSS

AVDDAVSS LDO_SEL SPKVDD

SCL/SSZ

SDA/MOSI

GPIO/DOUT

RST

DVDD DVSS IOVDD IOVSS

AINL

SPKP

SPKM

HOST PROCESSOR

0.1PF22PF

SVDD

0.1PF

22PF

+1.8VA

8-:or

4-:

Speaker

+1.8VD IOVDD

AINR

Analog Input

TAS2505

HPOUT

Headphone jack

MISO

SPI_SEL

SCLK

IOVDD

0.1PF

2.7k 2.7k

47PF

0.1PF 0.1PF10PF10PF

Typical Circuit Configuration

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multiple sources, including the MCLK, BCLK or GPIO/DOUT pins or the output of the internal PLL, where

the input to the PLL again can be derived from the MCLK, BCLK or GPIO/DOUT pins. Although using the

internal, fractional PLL ensures the availability of a suitable clock signal, it is not recommended for the

lowest power settings. The PLL is highly programmable and can accept available input clocks in the range

of 512kHz to 50MHz.

The device is available in the 4mm × 4mm, 24-pin QFN package.

1.2 Typical Circuit Configuration

Figure 1-2. Typical Circuit Configuration

4TAS2505 Device Overview SLAU472–February 2013

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DIN

BCLK

WCLK

MCLK

SPKVSS

AVDDAVSS LDO_SEL SPKVDD

SCL/SSZ

SDA/MOSI

GPIO/DOUT

RST

IOVDD IOVSS

AINL

SPKP

SPKM

HOST PROCESSOR

0.1PF22PF

SVDD

0.1PF

22PF

8-:or

4-:

Speaker

IOVDD

AINR

Analog Input

TAS2505

HPOUT

Headphone jack

MISO

SPI_SEL

SCLK

IOVDD

0.1PF

2.7k 2.7k

47PF

DVDDDVSS

0.1PF

10PF

0.1PF 10PF

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Circuit Configuration with Internal LDO

1.3 Circuit Configuration with Internal LDO

Figure 1-3. Application Schematics for LDO

SLAU472–February 2013 TAS2505 Device Overview

Chapter 2

SLAU472–February 2013

TAS2505 Application

2.1 Terminal Descriptions

2.1.1 Digital Pins

Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins

have a default function, and also can be reprogrammed to cover alternative functions for various

applications.

The fixed-function pins are RST LDO_SEL and the SPI_SEL pin, which are HW control pins. Depending

on the state of SPI_SEL, the two control-bus pins SCL/SSZ and SDA/MOSI are configured for either I2C or

SPI protocol.

Other digital IO pins can be configured for various functions via register control. An overview of available

functionality is given in Section 2.1.3.

2.1.2 Analog Pins

Analog functions can also be configured to a large degree. For minimum power consumption, analog

blocks are powered down by default. The blocks can be powered up with fine granularity according to the

application needs.

2.1.3 Multifunction Pins

Table 2-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be

programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).

Table 2-1. Multifunction Pin Assignments

1 2 3 4 5 6 7

Pin Function MCLK BCLK WCLK DIN GPIO SCLK MISO

/DOUT

APLL Input S(1) S(2) E S(3)

BCodec Clock Input S(1),D(4) S(2) S(3)

CI2S BCLK input S(2),D

DI2S BCLK output E(5)

EI2S WCLK input E, D

FI2S WCLK output E

GI2S DIN E, D

IGeneral Purpose Output I E

IGeneral Purpose Output II E

JGeneral Purpose Input I E

JGeneral Purpose Input II E

JGeneral Purpose Input III E

(1) S(1): The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.

(2) S(2): The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.

(3) S(3): The GPIO/DOUT pin can drive the PLL and Codec Clock inputs simultaneously.

(4) D: Default Function

(5) E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/DOUT has

been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)

6TAS2505 Application SLAU472–February 2013

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Terminal Descriptions

Table 2-1. Multifunction Pin Assignments (continued)

1 2 3 4 5 6 7

Pin Function MCLK BCLK WCLK DIN GPIO SCLK MISO

/DOUT

KINT1 output E E

LINT2 output E E

MSecondary I2S BCLK input E E

NSecondary I2S WCLK input E E

OSecondary I2S DIN E E

PSecondary I2S BCLK OUT E E

QSecondary I2S WCLK OUT E E

RSecondary I2S DOUT E

SAux Clock Output E E

SLAU472–February 2013 TAS2505 Application

Terminal Descriptions

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2.1.4 Register Settings for Multifunction Pins

To configure the settings seen in Table 2-1, please see the letter-number combination in Table 2-2 for the

appropriate registers to modify. In Table 2-2, the letter/number combination represents the row and the

column number from Table 2-1 in bold type.

Please be aware that more settings may be necessary to obtain a full interface definition matching the

application requirement (see Page 0, Register 25 to 33).

Table 2-2. Multifunction Pin Register Configuration

Required Register

Description Required Register Setting Description Setting

Page 0, Register 4, Bits D3- Page 0, Register 55, Bits

A1 PLL Input on MCLK K7 INT1 output on MISO

D2 = 00 D4-D1 = 0100

Page 0, Register 4, Bits D3- Page 0, Register 52, Bits

A2 PLL Input on BCLK L5 INT2 output GPIO/DOUT

D2 = 01 D5-D2 = 0110

Page 0, Register 54, Bits

D2-D1 = 01 Page 0, Register 55, Bits

A4 PLL Input on DIN/MFP1 L7 INT2 output on MISO

Page 0, Register 4, Bits D3- D4-D1 = 0101

D2 = 11

Page 0, Register 52, Bits Page 0, Register 52, Bits

D5-D2 = 0001 Secondary I2S BCLK input D5-D2 = 0001

A5 PLL Input on GPIO/DOUT M5

Page 0, Register 4, Bits D3- on GPIO/DOUT Page 0, Register 31, Bits

D2 = 10 D6-D5 = 00

Page 0, Register 56, Bits

Codec Clock Input on Page 0, Register 4, Bits D1- Secondary I2S BCLK input D2-D1 = 01

B1 M6

MCLK D0 = 00 on SCLK Page 0, Register 31, Bits

D6-D5 = 01

Page 0, Register 52, Bits

Codec Clock Input on Page 0, Register 4, Bits D1- Secondary I2S WCLK in on D5-D2 = 0001

B2 N5

BCLK D0 = 01 GPIO/DOUT Page 0, Register 31, Bits

D4-D3 = 00

Page 0, Register 52, Bits Page 0, Register 56, Bits

Codec Clock Input on D5-D2 = 0001 Secondary I2S WCLK in on D2-D1 = 01

B5 N6

GPIO/DOUT Page 0, Register 4, Bits D1- SCLK Page 0, Register 31, Bits

D0 = 10 D4-D3 = 01

Page 0, Register 52, Bits

Page 0, Register 27, Bit D3 Secondary I2S DIN on D5-D2 = 0001

C2 I2S BCLK input on BCLK O5

= 0 GPIO/DOUT Page 0, Register 31, Bit D0

= 0

Page 0, Register 56, Bits

Page 0, Register 27, Bit D3 Secondary I2S DIN on D2-D1 = 01

D2 I2S BCLK output on BCLK O6

= 1 SCLK Page 0, Register 31, Bit D0

= 1

Page 0, Register 27, Bit D2 Secondary I2S BCLK OUT Page 0, Register 52, Bits

E3 I2S WCLK input on WCLK P5

= 0 on GPIO/DOUT D5-D2 = 1000

Page 0, Register 27, Bit D2 Secondary I2S BCLK OUT Page 0, Register 55, Bits

F3 I2S WCLK output WCLK P7

= 1 on MISO D4-D1 = 1001

Page 0, Register 54, Bits Secondary I2S WCLK OUT Page 0, Register 52, Bits

G4 I2S DIN on DIN Q5

D2-D1 = 01 on GPIO/DOUT D5-D2 = 1001

Secondary I2S WCLK OUT Page 0, Register 55, Bits

H5 N/A Q7 on MISO D4-D1 = 1010

8TAS2505 Application SLAU472–February 2013

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Audio Analog I/O

Table 2-2. Multifunction Pin Register Configuration (continued)

Required Register

Description Required Register Setting Description Setting

General Purpose Out I on Page 0, Register 53, Bits Secondary I2S DOUT on Page 0, Register 55, Bits

I5 R7

GPIO/DOUT D3-D1 = 010 MISO D4-D1 = 1000

General Purpose Out II Page 0, Register 55, Bits Aux Clock Output on Page 0, Register 52, Bits

I7 S5

on MISO D4-D1 = 0010 GPIO/DOUT D5-D2 = 0100

General Purpose In I on Page 0, Register 54, Bits Page 0, Register 55, Bits

J4 S7 Aux Clock Output on MISO

DIN D2-D1 = 10 D4-D1 = 0011

General Purpose In II on Page 0, Register 52, Bits

J5 GPIO/DOUT D5-D2 = 0010

General Purpose In III on Page 0, Register 56, Bits

J6 SCLK D2-D1 = 10

INT1 output on Page 0, Register 52, Bits

K5 GPIO/DOUT D5-D2 = 0101

2.2 Audio Analog I/O

The TAS2505 features a mono audio DAC. It supports a wide range of analog interfaces to support

different headsets such as 16-Ωto 200-Ωimpedance and analog line outputs. TheTAS2505 can drive a

speaker upto 4-Ωimpedance.

2.3 Analog Signals

The TAS2505 analog signals consist of:

• Analog inputs AINR and AINL, which can be used to pass-through or mix analog signals to output

stages

• Analog outputs class-D speaker driver and headphone/lineout driver providing output capability for the

DAC, AINR, AINL, or a mix of the three

2.3.1 Analog Inputs AINL and AINR

AINL (pin 3 or C2) and AINR (pin 4 or B2) are inputs to Mixer P and Mixer M along with the DAC output.

Also AINL and AINR can be configured inputs to HP driver. Page1 / register 12 provides control signals for

determining the signals routed through Mixer P, Mixer M and HP driver. Input of Mixer P can be

attenuated by Page1 / register 24, input of Mixer M can be attenuated by Page1 / register 25 and input of

HP driver can be attenuated by Page1 / register 22. Also AINL and AINR can be configured to a monaural

differential input with use Mixer P and Mixer M by Page1 / register 12 setting. All the options can be

viewed in the functional block diagram, Figure 2-6.

2.4 Audio DAC and Audio Analog Outputs

The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital

delta-sigma modulator, and an analog reconstruction filter. The high oversampling ratio (normally DOSR is

between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated

within the delta-sigma modulator stays outside of the audio frequency band. Audio analog outputs include

mono headphone and lineout and mono class-D speaker outputs. Because the TAS2505 contains a mono

DAC, it inputs the mono data from the left channel, the right channel, or a mix of the left and right

channels as [(L + R) ÷ 2], selected by page 0, register 63, bits D5–D4. See Figure 1-1 for the signal flow.

2.4.1 DAC

The TAS2505 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of the

mono DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter,

multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide

enhanced performance at low sampling rates through increased oversampling and image filtering, thereby

keeping quantization noise generated within the delta-sigma modulator and observed in the signal images

SLAU472–February 2013 TAS2505 Application

Audio DAC and Audio Analog Outputs

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strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize

power dissipation and performance, the TAS2505 allows the system designer to program the

oversampling rates over a wide range from 1 to 1024 by configuring page 0, register 13 and page 0 /

lower oversampling ratios for higher input data rates.

The TAS2505 DAC channel includes a built-in digital interpolation filter to generate oversampled data for

the delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on

required frequency response, group delay, and sampling rate.

DAC power up is controlled by writing to page 0, register 63, bit D7 for the mono channel. The mono-

channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D7.

The DAC path of the TAS2505 features many options for signal conditioning and signal routing:

• Digital volume control with a range of -63.5 to +24dB

• Mute function

In addition to the standard set of DAC features the TAS2505 also offers the following special features:

• Digital auto mute

• Adaptive filter mode

2.4.1.1 DAC Processing Blocks

The TAS2505 implements signal-processing capabilities and interpolation filtering via processing blocks.

These fixed processing blocks give users the choice of how much and what type of signal processing they

may use and which interpolation filter is applied.

The choices among these processing blocks allows the system designer to balance power conservation

and signal-processing flexibility. Table 2-3 gives an overview of all available processing blocks of the DAC

channel and their properties. The resource-class column gives an approximate indication of power

consumption for the digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog

power consumption of the drivers (AVDD) may differ.

The signal-processing blocks available are:

• First-order IIR

• Scalable number of biquad filters

The processing blocks are tuned for common cases and can achieve high image rejection or low group

delay in combination with various signal-processing effects such as audio effects and frequency shaping.

The available first-order IIR and biquad filters have fully user-programmable coefficients.

Table 2-3. Overview – DAC Predefined Processing Blocks

Processing First-Order Number of Resource

Interpolation Filter Channel

Block No. IIR Available Biquads Class

PRB_P1 A Mono Yes 6 6

PRB_P2 A Mono No 3 4

PRB_P3 B Mono Yes 6 4

10 TAS2505 Application SLAU472–February 2013

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