Tektronix 7D01 Manual de usuario

Tektrone<

COMMITTED

EXCELLENCE

PLEASE

CHECK

FOR

CHANGE

INFORMATION

THE

REAR

THIS

MANUAL.

7D01

LOGIC

ANALYZER

(Serial

No.

BO20000

and

up)

WITH OPTIONS

INSTRUCTION

MANUAL

Tektronix,

Inc.

P.O.

Box

500

Beaverton,

Oregon

97077

Serial

Number

070-2206-02

First

Printing

OCT

1976

Product

Group

Revised

OCT

1982

1976,

1977,

1979

Tektronix,

Inc.

All

rights

reserved.

Contents

of this

publication

may

not

reproduced

any

form

without

the

written

permission

Tektronix,

Inc.

Products

Tektronix,

Inc.

and

its

subsidiaries

are

covered

U.S.

and

foreign

patents

and/or

pending

patents.

sath)

TEKTRONIX,

TEK,

SCOPE-MOBILE,

and

W'%

are

registered

trademarks

Tektronix,

Inc.

TELEQUIP-

MENT

registered

trademark

Tektronix

U.K.

Limited.

Printed

U.S.A.

Specification

and

price

change

privileges

are

reserved.

7D01

Instruction

(SN

BO20000

up)

TABLE

CONTENTS

PAGE

LIST'OF

ILLUSTRATIONS,

sscice

ccs

awmmats

amma

LISTIOP

TABLES

oew cst

wea

RRM

ETT

wai

SAFETY

SUMMARY

0.0...

eee

iii

SECTION

GENERAL

INFORMATION

INTRODUCTION.

0...

cee

eee

1-1

GLOSSARY

mee

1-1

INSTALLATION...

ese

mee

eee

EBS

1-1

PACKAGING

FOR

SHIPMENT.

..........50005

1-2

SPECIFICATION.«.:0:0

ses

smmee

eee

MMO

ETS

RBH

1-3

STANDARD

ACCESSORIES...

....

00.

eee

1-9

SECTION

OPERATING

INSTRUCTIONS

FRONT

PANEL

CONTROLS,

CONNECTORS

AND

INDICATORS............

2-1

DETAILED

OPERATING

INFORMATION..........

2-1

AUXILIARY

FUNCTIONS

.............200-

2-1

INTERNAL

STRAP

SELECTIONS.

............

2-4

SIGNAL

CONNECTIONS

..........02000005

2-6

DISPLAYING

DATA...

2...

2.2

eee

2-7

TRIGGERING...

2...

eee

2-7

CLOCK

QUALIFIER

OPERATION

............

2-8

ASYNCHRONOUS

AND

SYNCHRONOUS

DATA

SAMPLING)...

www

ees

mimi

bea

2-9

OPERATIONAL

ANALYSIS

............00484

2-10

APPLICATIONS

«0:66

mimm

WHS

12-13

INTRODUCTION...

sees

isswisme

cis wad

2-13

FAULT

IDENTIFICATION

..............2.24

2-13

DELAY

WORDS

..........

0.0004

eee

2-13

DELAY

EVENTS...

1...

eee

ee es

2-14

STATE

TABLE

AND

MAPPING

DISPLAYS

.....

2-14

MICROPROCESSOR

ANALYSIS............5-.

2-16

STORAGE

BUFFER

ANALYSIS.............-.

2-17

FUNCTIONAL

CHECK

wwcccw

nmeee

esas

2-17

THE

REMAINING

PORTION

THIS

TABLE

CON-

TENTS

LISTS

THE

SERVICING

INSTRUCTIONS.

THESE

SERVICING

INSTRUCTIONS

ARE

FOR

USE

QUALI-

FIED

PERSONNEL

ONLY.

AVOID

ELECTRICAL

SHOCK,

NOT

PERFORM

ANY

SERVICING

OTHER

THAN

THAT

CALLED

OUT

THE

OPERATING

IN-

STRUCTIONS

UNLESS

QUALIFIED

SO.

REV

JUN

1980

PAGE

SECTION

THEORY

OPERATION

BLOCK

DIAGRAM

DESCRIPTION.

...........000.%

3-1

DETAILED

CIRCUIT

DESCRIPTION.

.............

3-3

FRONT

PANEL

WIRING

seme

css

samme

eee

3-3

WORD

RECOGNIZER.

«sss

amew

cis

BRB

3-3

MEMORY

EER

RHR

DAT

WHAM

3-4

TRIGGER.

MOER

TLE

RRA

emma

3-7

TIME:

BASE

SHH

Hdisi

mmarew

3-9

VERTICAL

OUTPUT

........

eee

3-9

HORIZONTAL

OUTPUT...

....

eee

3-10

CURSOR,

ok.

cna

meme

hae

WES

3-10

POWER

SUPPLIES.

«iw

ewe

3-12

SECTION

MAINTENANCE

PREVENTIVE

MAINTENANCE.

............000,

4-1

CLEANING

0...

4-1

VISUAL

INSPECTION.

...

0...

0000s

4-1

LUBRICATION.

...

swe

awe

BHR

4-1

SEMICONDUCTOR

CHECKS,

............00058

4-2

TROUBLESHOOTING:

«swiss

css

HTS

wee

4-3

TROUBLESHOOTING

EQUIPMENT

............

4-3

TROUBLESHOOTING

TECHNIQUES

...........

4-3

CORRECTIVE

MAINTENANCE.

...........2000.

4-7

OBTAINING

REPLACEMENT

PARTS

...........

SOLDERING

TECHNIQUES.

............000,

4-7

COMPONENT

REMOVAL

AND

REPLACEMENT.....

4-8

ADJUSTMENT

AFTER

REPAIR.

............4.4

4-14

SECTION

PERFORMANCE

CHECK

AND

ADJUSTMENT

PRELIMINARY

INFORMATION

............4.

5-1

TEST

EQUIPMENT

REQUIRED..............4.

5-1

PRELIMINARY

PROCEDURE...............4.

5-3

PERFORMANCE

CHECK

AND

ADJUSTMENT

PROCEDURE...

.......

eee

5-5

SECTION

REPLACEABLE

ELECTRICAL

PARTS

SECTION

INSTRUMENT

OPTIONS

SECTION

DIAGRAMS

AND

CIRCUIT

BOARD

ILLUSTRATIONS

SECTION

REPLACEABLE

MECHANICAL

PARTS

CHANGE

INFORMATION

7D01

Instruction

(SN

BO20000

up)

FIGURE

Frontis-

NO.

piece

1-1

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

2-11

2-12

3-2

3-3

LIST

ILLUSTRATIONS

PAGE

7DO1

Logic

Analyzer.

2...

7D01

Dimensional

Drawing...

........0005%

1-8

Front-panel

controls,

connectors,

and

indicatOlsS:

ssa wee

eee

2-2

Internal

Display

Clock

Source

and

Full

Display/First

Trigger

Selectors...

......0.%

2-4

Internal

Signal

Selector...

...

2...

eee

ueee

2-5

assignments

for

Data

Out

connector

J120.

0.0...

2-6

Suggested

methods

for

terminating

data

outputs

from

Data

Out

connector

S120

2-7

Suggested

method

for

assembling

remote

Manual

Reset

button

............4.%

2-7

Typical

channel

pretrigger

data

display’:

sass

wim

ees

RRR

ees

2-8

Equipment

setup

and

displays

for

finding

data

fault

and

examining

onananalogdisplay

..........0

05 ee

eee

2-14

Equipment

setup

and

data

display

window

that

has

been

positioned

after

preselected

word

has

occurred

times......

2-15

Equipment

setup

and

display

window

that

has

been

positioned

after

10,500

clock

pulses

have

occurred.

.........-.206.

2-15

Typical

setup

for

troubleshooting

microprocessor

system...

2...

0.002

eee

2-16

Typical setup

and

display

for

trouble-

shooting

storage

buffer...

.......00000%

2-17

7001

Block'Diagram:

«ss

wae

ces

Www

3-2

Equivalent

circuit

for

one

channel

P6451

Data

Acquisition

Probe

.........0055

3-3

Truth

Table

for

Store/Display

Clock

Gate

3-5

PAGE

Electrical

Characteristics.

wae

ees

eee

1-3

Environmental

Characteristics...

........000.4

1-8

Physical

Characteristics.

«si

saws

aia

male

as 1-8

Format Output

Levels:

sic swe

eet

2-1

Minimum

Clock

Pulses

Required

Display

Data

(After

the

MANUAL,

RESET

Button

Pressed)

2...

2-9

FIGURE

NO.

3-4

3-5

3-6

3-7

3-8

4-2

4-3

4-5

4-6

4-7

4-10

4-11

PAGE

Latch

Clock

timing

for

4-channel

Operations

«aa.

DRM

3-5

Latch

Clock

timing

for

8-channel

Operation.

3-6

Memory

Selector

timing

for

4-channel

operation

(display

time

only)..............

3-6

Memory

Selector

timing

for

8-channel

operation

(display

time

only).

..........005

3-6

Binary

output

U628

versus

channel

displayed.

2...

3-9

Lubrication

procedure

for

typical

cam

SWItCH)

cme

Rew

MSH

4-2

Circuit

board

locations...

2.0.00.

eee

4-5

Power

supply

volt

test

point

location.

.......

4-6

Location

securing

screws

the

Memory

circuit

board

...........04

eee

4-8

Multi-pin

connector

and

number

orientation

for

the

Memory

circuit

board

.......

4-9

Location

of securing

screws

the

Interface

circuit

board...

.... 2...

0.2

000

4-10

Locations

of securing

screws

the

Output

circuit

board...

2...

eee

4-10

Locations

securing

screws

and

shield

the

Power

Supply

board

..............

4-11

Locations

securing

screws

the

Cursor

circuit

board

5.:0%

& &

sw we

ee oe

4-11

Locations

hex

nuts

and

screws

front

sub

panel

which

secure

the

Word

Recog-

nizer

circuit

board!

saw

eis

emw

4-12

Exploded

view

circuit-board

ana

Terrules

cis

seam

ees

wiwawe

wae

4-14

The

illustrations

Section

are

located

near

their

associated

Diagrams

the

foldout

pages.

TABLE

PAGE

Operational

Analysis...

1.0.0...

eee

2-10

Power

Supply

Tolerances

........00

0000

4-6

Test

Equipments

«iis

waeee

eae

BRE

ETT

5-1

Option

Information

Locator.

..........0.0.005

7-1

REV.

MAR

1977

—~

7D01

Instruction

(SN

BO20000

up)

SAFETY

SUMMARY

The

following

safety

information

provided

ensure

safe

operation

this

instrument.

WARNING

information

intended

protect

the operator;

CAUTION

information

intended

to protect

the

instrument.

The

following

are

general safety

pre-

cautions

that

must

observed

during

all

phases

operation

and

maintenance.

reduce

electrical-shock

hazard,

the

mainframe

(oscilloscope)

chassis

must

properly

grounded.

Refer

the

mainframe

manual

for

grounding

information.

Ground

the

Instrument

Not

Operate

Explosive

Atmosphere

not

operate

this

instrument

area

where

flammable

gases

fumes

are

present.

Such

operation

could

cause

explosion.

Avoid

Live

Circuits

Electrical-shock

hazards

are

present

this

instrument.

The

protective

instrument

covers

must

not

removed

operating

personnel.

Component

replacement

and

internal

adjustments

must

referred

qualified

service

personnel,

Not

Service

Adjust

Alone

not

service

make

internal

adjustments

this

instrument

unless

another

person,

capable

giving

first

aid

and

resusci-

tation,

present.

7D01

(SN

B020000

up)

7D01

FEATURES

The

7D01

Logic

Analyzer

will

store

and

display

channels

digital

data

when

installed

7000-series

mainframe.

The

cursor

function

provides

intensified

zone

the

data

display,

and

corresponding

numerical

readout

display

shows

the

logic

state

for

each

displayed

channel

data.

The

position

the

cursor,

relative

to the

trigger,

also

displayed

the

crt

readout.

Cursor

readout

displayed

either

3-bit

4-bit

bytes.

Digital

data

can

stored

formats:

channels

1016

bits/channel,

channels

508

bits/channel,

channels

254

bits/channel.

The

sample

rate

selectable

from

nanoseconds

milliseconds/sample

(in

5-2-1

sequence)

when

using the

internal

time

base,

can

used

with

external

clock

signal

(up

megahertz).

The

7D01

can

triggered

from

sources:

channel

data,

external

signal,

built-in

16-channel

word

recognizer,

man-

ually.

The

triggered

data

can be

produced

following

the

trigger

(POST

TRIG),

centered

around

the

trigger

(CENTER),

pre-

ceeding

the

trigger

(PRE

TRIG).

The

input

threshold

can be

varied

from

minus

volts

plus

volts,

set

plus

1.4

volts

for

TTL

logic

levels.

The

Word

Recognizer

produces

output

when

the

logic

states

the

input

data

channels

match

the

states

of the

corres-

ponding

Word

Recognizer

switches.

Two

qualifier

inputs

are

also

provided

enable

the

Word

Recognizer

output.

The

Word

Recognizer

operates

either

the

synchronous

asynchronous

mode.

variable

filter

(to

least

300

nanoseconds)-allows

rejection

brief

false-trigger

signals.

REV

JAN

1979

_—-]

——]

—)

—Joe5J

-J

~~)

—~)

sonics

—

Section

1—-7D01

(SN

B020000

up)

GENERAL

INFORMATION

INTRODUCTION

7D01

Operator’s

Manual

The

Operator’s

manual

contains the

information

necessary

operate

the

7D01

Logic

Analyzer.

The

manual

divided

into

three

sections,

each

covering

specific

topic

of the

instrument.

Section

provides

basic

description

the

7D01,

glossary

logic

terms,

installation

instructions,

and

specifications.

Section

contains

operating

information

for

the

instrument.

Information

concerning

available

op-

tions

for

the

7D01

tabbed

page

Section

7D01

Instruction

Manual

The

Instruction

manual

provides

operating

and

servicing

information

for

the

7D01

Logic

Analyzer.

The

manual

divided

into

ten

sections.

Operating

information

covered

the

first

two

sections;

servicing

information

contained

the

remaining

eight

sections

the

manual.

Schematics

are

located

the

rear

the

manual

and

can

unfolded

and

used

for

reference

while

reading

other

parts

the

manual.

The

reference

designators

and

symbols

used

the

schematics

are

defined

the

first

page

the

Diagrams

section.

Abbreviations

used

the

manuals,

except

the

parts

list

and

schematics,

comply

with

the

American

National

Standards

Institute

Y1.1-1972

publication.

The

parts

lists

are

computer

printouts

and

use

computer-

supplied

abbreviations.

GLOSSARY

The

terms

listed

this

glossary

are

used

throughout

this

manual.

Asynchronous—Multiple

digital

information

transferred

non-common

clock

rates.

Bit—The

smallest

increment

digital

information.

CPU—Central

Processing

Unit.

ECL—Emitter-Coupled

Logic.

Jitter—A

form

distortion

asynchronous

systems

that

due

timing

variations

of the

received

data.

Multiplexing—The

combining

multiple

inputs

into

single

output.

Parallel-to-Serial

Conversion—The

technique

storing

digital

pattern

from

parallel

bus,

then

transferring

that

pattern

out

serial

bus.

REV

OCT

1982

Parity

Bits—Bits

added

the

data

stream

which

enable

the

receiver

verify

whether

the

data

correctly

incor-

rectly

received.

PROM—Programmable

Read

Only

Memory.

RAM—Random

Access

Memory.

Serial

Data—Data

transferred

single

line.

Serial

data

logic

derived

sequential

mode.

Store

Clock—The

clock

used

store

information

into

the

7D01

memory.

Synchronous—Digital

information

transferred

with

the

same

clock

reference.

Threshold

Voltage—The

comparator

input

voltage

the

inverting

input,

which

used

reference.

Thus,

the

signal

the

non-inverting

input

above

the

threshold

voltage,

the

output

HI;

the

signal

below

the

threshold

voltage,

the

output

LO.

TTL—Transistor-Transistor

Logic.

“Wired-OR"—ECL

gate

outputs

that

are

connected

together

yield

the

equivalent

output

gate.

INSTALLATION

The

7D01

calibrated

and

ready

use

when

received.

designed

occupy

vertical

and

horizontal

plug-in

com-

partment

all

7000-series

mainframes

with

readout

except

the

7104,

which

may

suffer

crt

damage

that

will

not

cov-

ered

the

instrument

warranty,

and

the

Digital

Processing

Oscilloscope

(DPO),

which

will

not

digitize

the

7D01

out-

puts.

There

are

some

operating

modes,

however,

that

will

not

provide

proper

operation.

These

modes

are

discussed

under

Displaying

Data

Section

Install

the

7D01

the

two

compartments

the

right

side

three-compartment

mainframe,

the

right

vertical

and

horizontal

compart-

ments

the

center

four-compartment

mainframe.

NOTE

Some

rackmounted

mainframes

have

vertically

mounted

rods

front

the

plug-in

compart-

ments

that

interfere

with

the

installation

the

7D01,

Detach

these

rods

removing

the

mount-

ing

screws

each

end

before

installing

the

7D01.

1-1

General

Information—7D01

(SN

B020000

up)

install

the

7D01

the

mainframe,

align

the

7D01

tracks

with

the

rails

vertical

and

horizontal

plug-in

compart-

ment.

Gently

slide

the

7D01

into

the

mainframe

and

push

firmly

lock the

7D01

front panel

flush

with

the

mainframe.

remove

the

7D01,

grasp

the

release

latch

the

lower

left

corner

and

pull

the

7D01

out

the

mainframe.

PACKAGING

FOR

SHIPMENT

this

instrument

shipped

for

long

distances

commercial

transportation,

it is

recommended

that

the

instrument

packaged

the

original

manner

for

maxi-

mum

protection.

The

carton

and

packing

material

which

your

instrument

was

shipped

should

saved

and

used

for

this

purpose.

the

original

packaging

unfit

for

use

not

available,

package

the

instrument

follows:

Obtain

carton

corrugated

cardboard

with

least

200

pound

test

strength

and

inside

dimensions

less

than

six

inches

than

the

instrument

dimensions;

this

will

allow

for

cushioning.

1-2

Surround

the

instrument

with

polyethylene

sheeting

protect

the

finish

the

instrument.

Cushion

the

instrument

all

sides

tightly

packing

dunnage

urethane

foam

between

the

carton

and

the

instrument,

allowing

three

inches

all

sides.

Seal

the

carton

with

shipping

tape

industrial

stapler.

Also,

this

instrument

shipped

Tektronix

Service

Center

for

service

repair,

attach

tag

the

instrument

showing

the

following:

Owner

the

instru-

ment

(with

address),

the

name

individual

your

firm

that

can

contacted,

complete

instrument

type

and

serial

number,

and

description

the

service

required.

Mark

the

address

the

Tektronix

Service

Center,

and

your

return

address,

the

carton

one

prominent

locations.

REV.

MAR

1977

General

Information—7D01

(SN

B020000

up)

SPECIFICATION

The

electrical

specifications

listed

Table

1-1

apply

when

the

following

conditions

are

met:

(1)

The

instrument

must

have

been

adjusted

ambient

temperature

between

+20°

and

+30°

(+68°

and

+86°

F),

(2)

the

instrument

must

operating

ambient

temperature

between

0°

and

+40°

(+32°

and

+104°

F),

and

(3)

the

instrument

must

have

been

operating

for

least

minutes.

TABLE

1-1

Electrical

Characteristics

Characteristic

CLOCK

AND

DATA

INPUTS

Performance

Requirement

Probe

Inputs

(Clock,

Qualifier,

and

Data)

Input

and

within

5%,

paralleled

approx.

pF.

Threshold

Voltage

VAR

(at

Monitor

Jack)

—12

less,

least

+12

TTL

+1.4

within

0.2

Minimum

Logic

Swing

500

plus

threshold

voltage

p-p

less,

centered

threshold

voltage.

Maximum

Logic

Swing

—60

less,

least

threshold

voltage

plus

Maximum

Non-Destructive

Input

Voltage

—60

less,

least

+60

External

Clock

Minimum

Clock

Period

0-3

less.

0-7

less.

0-15

less.

Minimum

Clock

Pulse

Width

Level

0-3

less

ns or

less

0-7

less

0-15

less 20

less

Minimum

Data

Setup

Time

0-3

less.

0-7

less.

0-15

less.

Minimum

Data

Hold

Time

Ons

less.

Clock

Qualifier

Setup

Time

Hold

Time

P6451

Probe

Ons

External

Input

(measured

external

input

connector)

REV

OCT

1982

General

Information—7D01

(SN

B020000

up)

TABLE

1-1

(CONT.)

Electrical

Characteristics

Characteristic

Performance

Requirement

CLOCK

AND

DATA

INPUTS

(CONT.)

Internal

Clock

Minimum

Sample

Interval

0-3

less.

0-7

less.

0-15

less.

Minimum

Data

Pulse

Width

(to

Ensure

Recording)

sample

interval

plus

less.

INTERNAL

CLOCK

Crystal

Oscillator

Frequency

100

MHz

within

0.005

MHz.

Sample

Intervals

ns to

ms/sample

1-2-5

sequence.

TRIGGER

Trigger

Sources

CHO

Triggers

rising

edge

data.

External

Trig/Qualifier

Input

Threshold

+1.4

within

0.2

(TTL

Level).

Minimum

Pulse

Width

less.

Max

Safe

Input

Voltage

—5 V

less,

least

+10

Word

Recognizer

Data

inputs,

Probe

Qualifier,

and

External

Qualifier.

Output

true

when

input

conditions

match

switch

settings

(HI,

LO).

Minimum

Input

Pulse

Width

(Asynchronous

Mode)

Any

Single

Channel

less.

Channels

0-3

less.

Any

Other

Combination

less.

Filter

Continuously

variable

least

300

ns.

Synchronous

Mode

Coincidence

matching

combination

and

external

clock

edge

must

occur

for

recognition.

Minimum

Setup

Time

12.5

less.

Minimum

Hold

Time

8.5

less.

1-4

REV

OCT

1982

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