Sun Microsystems SME5224AUPA-400 Manual de usuario

DATASHEET

SME5224AUPA-400

UltraSPARC™-II CPU Module

400 MHz CPU, 4.0 MB E-Cache

MODULE DESCRIPTION

The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400) delivers high performance

computing in a compact design. Based on the UltraSPARC™-II CPU, this module is designed using a small

form factor board with an integrated external cache. It connects to the high bandwidth Ultra™ Port Architec-

ture UPA bus via a high speed sturdy connector. The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, can

plug into any UPA connector, saving system design costs and reducing the production time for new systems.

Heatsinks are attached to components on the module board. The module board is encased in a plastic shroud.

The purpose of this shroud is to protect the components and channel airﬂow. Module design is geared

towards ease of upgrade and ﬁeld support.

Module Features Module Beneﬁts

Ease of System Design • Small form factor board with integrated external cache

and UPA interface

• JTAG boundary scan and performance instrumentation

• PCB provides a multi-power plane bypass, reducing

systemboard design requirements

Performance • High performance UltraSPARC™ CPU at 400MHz

• Four megabytes of external cache using high speed

• Dedicated high bandwidth bus to processor

Glueless MP Support •

• Implements the high performance AUPA interface

• Supports up to 16 Mbyte of external cache in a

four-way MP system

Simplify System Qualiﬁcations by

Complying with Industry and Government

Standards • Backwards compatibility with systems implementing a

UPA interface

• Plastic shroud protects components and channels

airﬂow

• Multi-layer PCB controls EMI radiation

• Edge connectors and ejectors

• Small form factor board encased in a heat resistant

shroud

• On-board voltage regulator accepts 2.6 volts for the

Vdd_core; compatible with existing systems

July 1999

SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module

July 1999

Sun Microsystems, Inc

CPU DESCRIPTION

UltraSPARC-II CPU

The UltraSPARC™-II CPU is the second generation in the UltraSPARC™ s-series microprocessor family.

A complete implementation of the SPARCV9 architecture, it has binary compatibility with all previous ver-

sions of the SPARC™ microprocessor family.

The UltraSPARC™-II CPU is designed as a cost effective, scalable and reliable solution for high-end worksta-

tions and servers. Meeting the demands of mission critical enterprise computing, theUltraSPARC™-II CPU

runs enterprise applications requiring high data throughput. It is characterized by a high integer and ﬂoating

point performance: optimally accelerating application performance, especially multimedia applications.

Delivering high memory bandwidth, media processing and raw compute performance, the UltraSPARC™-II

CPU incorporates innovative technologies which lower the cost of ownership.

CPU Features CPU Beneﬁts

Architecture • 64-bit SPARC-V9 architecture increases the

network computing application’s performance

•Thirty-two 64-bit integer registers • Allows applications to store data locally in the

•Superscalar/Superpipelined • Allows for multiple integer and ﬂoating point

execution units leading to higher application

performance

•High performance memory interconnect • Alleviating the bottleneck of bandwidth to main

memory

•Built-in Multiprocessing Capability • Delivering scalability at the system level, thus

increasing the end user’s return on investment

•VIS multimedia accelerating instructions • Reducing the system cost by eliminating the

special purpose media processor

•100% binary compatibility with previous versions

of SPARC™ • Increasing the return on investment of software

applications

•Uses 0.25 micron technology and packaging • Enhanced processor performance with decreased

power consumption, thus increasing the reliability

of the microprocessor

Performance

•Integer • 17.4(SPECint95)

•Floating Point • 25.7 (SPECfp95)

•Bandwidth (BW) to main memory • 1.6 Gbyte/sec (peak) with a 100MHz UPA

Unique Features

•Block load and store instructions • Delivering high performance access to large

datasets across the network

•JTAG Boundary Scan and Performance

Instrumentation • Enabling UltraSPARC™ based systems to offer

features such as: power management, automatic

error correction, and lower maintenance cost

400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module SME5224AUPA-400

Advanced Version

July 1999 Sun Microsystems, Inc

DATA BUFFER DESCRIPTION

UltraSPARC-II Data Buffer (UDB-II)

The UltraSPARC™-II module has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for

a UPA Interconnect system bus width of 128 Data + 16 ECC.

There is a bidirectional ﬂow of information between the external cache of the CPU and the 144-bit UPA inter-

connect. The information ﬂow is linked through the UDB-II, it includes: cache ﬁll requests, writeback data for

dirty displaced cache lines, copyback data for cache entries requested by the system, non-cacheable loads and

stores, and interrupt vectors going to and from the CPU.

Each UDB-II has a 64-bit interface plus eight parity bits on the CPU side, and a 64-bit interface plus eight error

correction code (ECC) bits on the system side.

The CPU side of the UDB-II is clocked with the same clock delivered to UltraSPARC-II (1/2 of the CPU pipe-

line frequency).

EXTERNAL CACHE DESCRIPTION

The external cache is connected to the E-cache data bus. Nine SRAM chips are used to implement the four

megabyte cache. One SRAM is used as the tag SRAM and eight are used as data SRAMs. The tag SRAM is

128K x 36, while the data SRAMs are 256K x 18. All nine SRAMs operate in synchronous register-latch mode.

The SRAM interface to the CPU runs at one-half of the frequency of the CPU pipeline. The SRAM signals

operate at 1.9V HSTL. The SRAM clock is a differential low-voltage HSTL input.[1]

1. PECL (Positive Emitter Coupled Logic) clocks are converted on the module to the HSTL clocks, for the E-cache

interface.

SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module

July 1999

Sun Microsystems, Inc

MODULE COMPONENT OVERVIEW

The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), (see Figure 1), consists of the

following components:

• UltraSPARC™-II CPU at 400 MHz

• UltraSPARC-II Data Buffer (UDB-II)

• 4.0 Megabyte E-cache, made up of eight (256K X 18) data SRAMs and one 128K X 36 Tag SRAM

• Clock Buffer: MC100LVE210

• DC-DC regulator (2.6V to 1.9V)

• Module Airﬂow Shroud

Block Diagram

The module block diagram for the UltraSPARC™–II, 400 MHz CPU, 4 Mbyte E-cache module

is illustrated in Figure 1.

Figure 1. Module Block Diagram

Tag SRAM

128K x 36 SRAM

256K x 18

Tag SRAM ADDR [17:0] + Control

Tag SRAM DATA [24:0] UltraSPARC-II

CPU

UDB-II UDB-II

SRAM ADDR [19:0] + Control

DATA [71:0]DATA [143:72]

UDB-II

Control

UPA Connector

Clock Buffer

Clocks

UPA ADDR [35:0] + Control

SRAM

256K x 18

DC-DC

Regulator

2.6V

1.9V

UPA_DATA [143:0]

400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module SME5224AUPA-400

Advanced Version

July 1999 Sun Microsystems, Inc

SYSTEM INTERFACE

Figure 2 shows the major components of a UPA based uniprocessor system. The system controller[1] for the

UPA bus arbitrates between the UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, and the I/O bridge chip.

The ﬁgure also illustrates a slave-only UPA graphics port for Sun graphics boards.

The module UPA system interface signals run at one-quarter of the rate of the internal CPU frequency.

UPA Connector Pins

The UPA edge connector provides impedance control. The pin assignments are shown with the physical mod-

ule connector and are represented on page 24 and page 25.

UPA Interconnect

The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), supports full master and

slave functionality with a 128-bit data bus and a 16-bit error correction code (ECC).

All signals that interface with the system are compatible with LVTTL levels. The clock inputs at the module

connector, CPU_CLK, UPA_CLK0, and UPA_CLK1, are differential low-voltage PECL compatible.

1. Only two megabytes of external cache are recognized and supported when using the

Dual Processor System Controller (DSC, Marketing Part No.STP2202ABGA).

Figure 2. Uniprocessor System Conﬁguration

I/O Bridge

Chip

UltraSPARC-II

Module

SME5224AUPA-400

Memory

SIMMs

Memory Data Bus

Cross Bar

Switch

UPA Address Bus 0

UPA Data Bus

144

UPA Data Bus

Expansion Bus

UPA

Graphic

Device

System

Controller UPA Address Bus 1

UPA Data Bus

SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module

July 1999

Sun Microsystems, Inc

Module ID

Module IDs are used to conﬁgure the UPA address of a module. The UPA_PORT_ID[4:3] are hardwired on

the module to “0”. UPA_PORT_ID[1:0] are brought out to the connector pins. Each module is hardwired in

the system to a ﬁxed and unique UPA address. This feature supports systems with four or fewer processors.

For systems that need to support eight modules, UPA_SPEED[1] is connected to SYSID[2] in UDB-II to pro-

vide UPA_PORT_ID[2].

Systems which support more than eight modules must map the limited set of UPA_PORT_IDs from this mod-

ule to the range of required UPA_PORT_IDs, by implementation-speciﬁc means in the system.

System ﬁrmware (Open Boot Prom) uses UPA_CONFIG_REG[42:39] for generating correct clocks to the CPU

module and the UPA system ASICs. These bits are hardwired on the module and are known at MCAP[3:0] at

the UltraSPARC-II pins. The 4-bit MCAP value for this module is 0111b.

Module Power

Two types of power are required for this module: VDD at 3.3V, and VDD_CORE at 2.6V. The VDD_CORE supplies the

DC-DC regulator which in turn supplies 1.9 volts to the core of the processor chip, the UDB-II external cache

interface I/O, and the SRAM I/O. A resistor located on the module sends the program value to the power

supply so it generates VDD_CORE at 2.6V to the regulator.

JTAG Interface

The JTAG TCK signal is distributed to UDB-II, SRAMs and the CPU. For additional information about the

JTAG interface, see "JTAG Testability," on page 22, and "JTAG (IEEE 1149.1) Timing," on page 23.

400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module SME5224AUPA-400

Advanced Version

July 1999 Sun Microsystems, Inc

SIGNAL DESCRIPTION[1]

System Interface

Signal Type Name and Function

UPA_ADDR[35:0] I/O Packet switched transaction request bus. Maximum of three other masters and one

system controller can be connected to this bus. Includes 1-bit odd-parity protection.

Synchronous to UPA_CLK.

UPA_ADDR_VALID I/O Bidirectional radial UltraSPARC-II Bus signal between the UltraSPARC-II CPU and the

system. Driven by UltraSPARC-II to initiate UPA_ADDR transactions to the system.

Driven by system to initiate coherency, interrupt or slave transactions to

UltraSPARC-II CPU. Synchronous to UPA_CLK. Active high.

UPA_REQ_IN[2:0] I UltraSPARC-II system address bus arbitration request from up to three other

UltraSPARC-II bus ports, which may share the UPA_ADDR. Used by the

UltraSPARC-II for the distributed UPA_ADDR arbitration protocol. Connection to other

UltraSPARC-II bus ports is strictly dependent on the Master ID allocation.

Synchronous to UPA_CLK. Active high.

UPA_SC_REQ_IN I UltraSPARC-II system address bus arbitration request from the system. Used by the

UltraSPARC-II CPU for the distributed UPA_ADDR arbitration protocol.

Synchronous to UPA_CLK. Active high.

UPA_S_REPLY[4:0] I UltraSPARC-II system reply packet, driven by system controller to the UPA port.

Synchronous to UPA_CLK. Active high. UPA_S_REPLY [4] is a no-connect.

UPA_DATA_STALL I Driven by system controller to indicate whether there is a data stall. Active high.

UPA_P_REPLY[4:0] O UltraSPARC-II system reply packet, driven by the UltraSPARC-II to the system.

Synchronous to UPA_CLK. Active high.

UPA_DATA[127:0] I/O UPA Interconnect data bus.

UPA_ECC[15:0] I/O ECC bits for the data bus. 8-bit ECC per 64-bits of data.

UPA_ECC_VALID I Driven by the system controller to indicate that the ECC is valid for the data on the

UPA interconnect data bus: active high.

UPA_REQ_OUT I/O Arbitration request from this module: active high.

UPA_PORT_ID[1:0] I Module’s identiﬁcation signals: active high. UPA_SPEED[1] acts as a

UPA_PORT_ID[2]

1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25.

Clock Interface

Signal Type Name and Function

UPA_CLK[1:0]_POS

UPA_CLK[1:0]_NEG I UPA Interconnect Clock: two copies are provided, one for the CPU and one for the

UDBs

CPU_CLK_POS

CPU_CLK_NEG I Differential Clock inputs to the clock buffer on the module

UPA_RATIO I This is not used.

UPA_SPEED [0] O UPA_SPEED [0] is an output tied low on the module

UPA_SPEED [1] I/O UPA_SPEED[1] is tied low with 510 ohms and high to 3.3V with 4.7k ohms. It is

also connected to the SYSID [2] on each UDB-II.

UPA_SPEED [2] O UPA_SPEED [2] is tied low on the module

SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module

July 1999

Sun Microsystems, Inc

JTAG/Debug Interface

Signal Type Name and Function

TDO O IEEE 1149 test data output. A three-state signal driven only when the TAP controller is

in the shift-DR state.

TDI I IEEE 1149 test data input. This pin is internally pulled to logic one when not driven.

TCK I IEEE 1149 test clock input. This pin if not hooked to a clock source must always be

driven to a logic 1 or a logic 0.

TMS I IEEE 1149 test mode select input. This pin is internally pulled to logic one when not

driven. Active high.

TRST_L I IEEE 1149 test reset input (active low). This pin is internally pulled to logic one when not

driven. Active low.

Initialization Interface

Signal Type Name and Function

UPA_RESET_L I Driven by the system controller for the POR (power-on) resets and the fatal system

reset. Asserted asynchronously. Deasserted synchronous to UPA_CLK. Active low.

UPA_XIR_L I Driven to signal externally initiated reset (XIR). Actually acts like a non-maskable

interrupt. Synchronous to UPA_CLK. Active low, asserted for one clock cycle.

Miscellaneous Signals

Signal Type Name and Function

TEMP_SENSE_NEG

TEMP_SENSE_POS O Connected to a thermistor[1] adjacent to the CPU package.

1. The thermistor used on the module (SME5224AUPA-400) is manufactured by KOA. Operating at 47K the thermistor has KOA part

number NT32BT473J.

POWER_SET_POS

POWER_SET_NEG O POWER_SET_NEG is tied to GND on the module. POWER_SET_POS is connected

to GND via a 1690-ohm resistor. Sets voltage of programmable supply.

POWER_OV O Connected to GND via a 1180-ohm resistor. Sets overvoltage level for programmable

supply.

400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module SME5224AUPA-400

Advanced Version

July 1999 Sun Microsystems, Inc

UPA AND CPU CLOCKS

Module Clocks

The module receives three differential pair low voltage PECL (LVPECL) clock signals (CPU_CLK, UPA_CLK0

and UPA_CLK1) from the systemboard and terminates them. The CPU_CLK is unique in the system, but the

UPA_CLKs are two of many UPA clock inputs in the system.

The CPU_CLK operates at 1/2 the CPU core frequency. The UPA_CLKs operate at the UPA bus frequency.

The CPU to UPA clock ratios refer to the CPU core to UPA bus clock signal frequency. The CPU on the module

will automatically sense the clock ratio driven by the systemboard as long as the module clock timing is

satisﬁed.

The UltraSPARC-II CPU and UDB-II data buffers detect and support multiple CPU to UPA clock frequency

ratios. The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module is production tested in the 4:1 ratio (400 MHz

CPU and 100 MHz UPA). It can be qualiﬁed at other ratios in speciﬁc systemboards.

System Clocks

The systemboard generates and distributes the CPU and UPA LVPECL clocks. The systemboard includes a

frequency generator, frequency divider, clock buffers, and terminators.

The buffers fan-out the LVPECL clocks to the many UPA devices: the module, cross-bar data switches, system

controller, FFB, and the system I/O bridge. The LVPECL clock trace pairs are routed source-to-destination.

Each net is terminated at the destination. Most destinations are to single devices. The PCB traces for the

LVPECL clocks are balanced to provide a high degree of synchronous UPA device operation.

System Clock Distribution

The goal of this clock distribution is to deliver a quality clock to each system UPA device simultaneously and

with the correct clock relationships to the module clocks. For a discussion on how to layout and balance the

systemboard LVPECL clock signals and UPA bus signals, see the UPA Electrical Bus Design Note (Document

Part Number: 805-0089).

The effective length of the CPU_CLK, UPA_CLK0, and UPA_CLK1 clocks signals on the module are provided

in the UPA AC Timing Speciﬁcation section of this data sheet.

The block diagram for the LVPECL clocks "Clock Signal Distribution," on page 10, illustrates a typical system

clock distribution network. Each clock line is a parallel-terminated, dual trace LVPECL clock signal for the

CPU, the UPA and the SRAM devices.

UltraSPARC-II CPU Module Tested CPU to UPA

Frequency Ratio Other supported CPU to UPA Frequency Ratios

400 MHz, 4 Mbyte E-cache 4:1 3:1, 5:1, 6:1

SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module

July 1999

Sun Microsystems, Inc

LOW VOLTAGE PECL

Two trace signals compose each clock: one positive signal and one negative signal. Each signal is 180-degrees

out of phase with the other. Signal timing is referenced to when the positive LVPECL signal transitions from

low to high at the cross-over point, when the negative signal transitions from high to low. The trace-pair are

routed side-by-side and use parallel termination, (speciﬁc routing techniques are require).

CPU CLOCK INPUT

The PLL in the CPU doubles the clock frequency presented at its clock pin. So, for a 400 MHz core CPU clock

frequency, the CPU_CLK signal is 200 MHz. Therefore, for the CPU, actions will appear to occur at both tran-

sitions of the input CPU_CLK.

CLOCK TRACE DELAYS

The LVPECL propagation time is constant for all clock signals so all balancing is based on length rather than

time. All LVPECL traces are striplines (dielectric and power planes top and bottom) with a ﬁxed 180 ps per

inch propagation time using the FR4, PCB Dielectric.

Clock Buffer

SRAM

UDB-II

SRAM/TAG

UltraSPARC-II

CPU

Clock

Buffer

Clock

Divider

CPU_CLK

UPA_CLK0

UPA_CLK1

UPA_CLK2

UPA_CLKx

UPA_CLK

UPA Device

Module

Connector

Module Boundary

Clock

Generator

UDB-II

UPA Device

Serial

Parallel

Figure 3. Clock Signal Distribution

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