ST STM8S Manual de usuario

April 2018 AN2752 Rev 6 1/40

AN2752

Application note

Getting started with STM8S and STM8AF microcontrollers

Introduction

This application note complements the information contained in STM8S and STM8AF

datasheets by describing the minimum hardware and software environment required to build

an application around these 8-bit microcontrollers.

This document also contains detailed reference design schematics with descriptions of the

main components, and some hardware recommendations.

Some of the information given in Section 9: Software toolchain and Section 10: Setting up

the development environment has a wider scope, to know if it applies to STM8 MCUs

different from those of the STM8S and STM8AF Series contact your local representative.

www.st.com

Contents AN2752

2/40 AN2752 Rev 6

Contents

1 Hardware requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Main operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Power-on/power-down reset (POR/PDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Analog power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Clock management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 Reset management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.3 Ground and power supply (VSS, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.7 User options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Components reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AN2752 Rev 6 3/40

AN2752 Contents

8.1 Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.1.1 SWIM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.1.2 SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.1.3 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.2 Emulator STice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.2.1 STice overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.2.2 STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.2.3 In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.1 Integrated development environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.2 Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.3 Firmware library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10 Setting up the development environment . . . . . . . . . . . . . . . . . . . . . . . 28

10.1 Installing the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10.2 Using the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10.2.1 Project editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.2.2 Online help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10.3 Running the demonstration software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.3.1 Compiling the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.3.2 Selecting the correct debug instrument . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3.3 Connecting the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.3.4 Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10.3.5 Running the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.3.6 Follow up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

11 Documentation and on-line support . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

List of tables AN2752

4/40 AN2752 Rev 6

List of tables

Table 1. Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 2. SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 3. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

AN2752 Rev 6 5/40

AN2752 List of figures

List of figures

Figure 1. Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. External capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Typical layout of VDD/VSS and VCAP/VSS pairs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Analog input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. System clock distribution internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11. Debug system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13. Connection description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 14. STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 15. In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 16. Software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 17. Firmware library examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 18. STVD open example workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 19. STVD MCU edit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 20. STM8 firmware library on-line help manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 21. STVD: Building the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 22. STVD: Selecting the debug instrument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 23. Connecting the debug instrument to the STM8 evaluation board. . . . . . . . . . . . . . . . . . . . 34

Figure 24. STVD: Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 25. STVD: Running the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 26. STM8 evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Hardware requirements summary AN2752

6/40 AN2752 Rev 6

1 Hardware requirements summary

To build an application based on a microcontroller of the STM8S or STM8AF Series, the

board must have at least the following features:

•power supply

•clock management

•reset management

•debugging tool support: single wire interface module (SWIM) connector.

AN2752 Rev 6 7/40

AN2752 Power supply

2 Power supply

2.1 Power supply overview

The device can be supplied through a 3.0 V to 5.5 V external source. An on-chip power

management system provides the 1.8 V digital supply to the core logic, both in normal and

low power modes. It is also capable of detecting voltage drops, on both external

(3.3 V / 5 V) and internal (1.8 V) supplies.

The device provides:

•one pair of pads VDD/VSS (3.3 V ± 0.3 V to 5 V ± 0.5 V) dedicated to the main regulator

ballast transistor supply.

•two pairs of pads dedicated for VDD_IO/VSS_IO (3.3 V ± 0.3 V to 5 V ± 0.5 V), which are

used to power only the I/O’s. On 32-pin packages, only one pair is bonded.

Note: For VDDIO/VSSIO next to VDD/VSS, it is recommended to connect these two pairs together

and to use only a decoupling capacitor. The purpose is to ensure good noise immunity by

reducing the connection length between both supplies and also between VDD/VDDIO and the

capacitor.

•One pair of pads VDDA/VSSA (3.3 V ± 0.3 V to 5 V ± 0.5 V) dedicated to analog

functions. Refer to Section 3: Analog-to-digital converter (ADC) for more details.

Figure 1. Power supply

Note: The capacitors must be connected as close as possible to the device supplies (especially

VDD in case of dedicated ground plane).

Placing a crystal/resonator on OSCIN/OSCOUT is optional. The resonator must be

connected as close as possible to the OSCIN and OSCOUT pins. The loading capacitance

ground must be connected as close as possible to VSS.

Main / Low power

regulator

CPU

RAM

Logic

Analog functions

IOsIOs

XTAL

Star connected

Analog

signal

VCAP

VDD/VDDIO1

VDDIO2

VSSIO2

VDDA

VSSA

OSCIN

OSCOUT

VDDIO

VSSIO

VDDIO

3.3V - 5V

VSS/VSSIO1

ai15330

Power supply AN2752

8/40 AN2752 Rev 6

2.2 Main operating voltages

STM8S and STM8AF devices are made in 0.13 µm technology. The STM8S and STM8AF

core and I/O peripherals need different power supplies. In fact, STM8S and STM8AF

devices have an internal regulator with a nominal target output of 1.8 V.

Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to

the VCAP pin. Refer to the STM8S or STM8AF datasheets (available on www.st.com) for

more information on the VCAP characteristics. Take care to limit the series inductance to

less than 15 nH.

Figure 2. External capacitor

2.3 Power-on/power-down reset (POR/PDR)

The input supply to the main and low power regulators is monitored by a power-on/power-

down reset circuit. The monitoring voltage range is 0.7 V to 2.7 V.

During power-on, the POR/PDR keeps the device under reset until the supply voltages (VDD

and VDDIO) reach their specified working area.

At power-on, a defined reset must be maintained below 0.7 V. The upper threshold for a

reset release is defined in the electrical characteristics section of the product datasheet.

Hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall.

The POR/PDR also generates a reset when the supply voltage drops below the VPOR/PDR

threshold (isolated and repetitive events).

Rleak

ESR ESL

Where:

ESR isthe equivalent seriesresistance

ESL isthe equivalent inductance

AN2752 Rev 6 9/40

AN2752 Power supply

Recommendations

All pins need to be properly connected to the power supplies. It is important to have the

lowest possible impedance for these connections, including pads, tracks and vias. This is

typically achieved with thick track widths and dedicated power supply planes in multi-layer

printed circuit boards (PCBs).

In addition, each power supply pair has to be decoupled with 100 nF filtering ceramic

capacitors (C) with one chemical capacitor (1 to 2 µF) in parallel on the STM8S or STM8AF

device. The ceramic capacitors (including CEXT capacitor between VCAP and VSS pins)

need to be placed as close as possible or below the appropriate pins, on the opposite side

of the PCB. Typical values are 10 nF to 100 nF, but exact values depend on the application

needs. Figure 3 shows the typical layout of the VDD/VSS and VCAP/VSS pairs.

Figure 3. Typical layout of VDD/VSS and VCAP/VSS pairs

069

9'' 9&$3 966

0&8

YLDWR9'' YLDWR966

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Analog-to-digital converter (ADC) AN2752

10/40 AN2752 Rev 6

3 Analog-to-digital converter (ADC)

3.1 Analog power

The ADC has an independent, analog supply reference voltage, isolated on input pin VDDA,

which allows the ADC to be supplied by a very clean voltage source. This analog voltage

supply range is the same as the digital voltage supply range on pin VDD. An isolated analog

supply ground connection on pin VSSA provides further ADC supply isolation. Together, the

analog supply voltage and analog supply ground connection, offer a separate external

analog reference voltage input for the ADC unit on the VREF+ pin. This gives better accuracy

on low voltage input as follows:

•VREF+ (input, analog reference positive): the higher/positive reference voltage for the

ADC needs to be between 250 mV and VDDA. For more details about VREF+ values

refer to the STM8S or STM8AF datasheets. This input is bonded to VDDA in devices

that have no external VREF+ pin (packages with 48 pins or less).

•VREF- (input, analog reference negative): the lower/negative reference voltage for the

ADC has to be higher than VSSA. For more details about VREF- values refer to the

STM8S or STM8AF datasheets. This input is bonded to VSSA in devices that have no

external VREF- pin (packages with 48 pins or less).

3.2 Analog input

STM8S and STM8AF devices have 16 analog input channels, which are converted by the

ADC one at a time, and each of them is multiplexed with an I/O.

The analog input interface of the ADC is shown in Figure 4.

Figure 4. Analog input interface

VIN_EXT REXT

CEXT CSAMP

SWSAMP

VIN

Outside ADC Inside ADC

Otros manuales para STM8S

Este manual sirve para los siguientes modelos

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ST STM32F40 Series Manual de usuario

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ST STM32MP135F-DK Manual de usuario

ST STM32G4 Series Manual de usuario

ST STM8S Instrucciones de instalación y funcionamiento

ST STM32H7B3I-DK Manual de usuario

ST STM32F7 Series Suplemento

ST P-NUCLEO-WB55 Manual de usuario

ST STM32F4DISCOVERY Manual de usuario

ST STEVAL-MKSBOX1V1 Manual de usuario

ST STM32F746IGT6 Manual de usuario

ST UM2708 Manual de usuario

ST STM32F0 Series Instrucciones de instalación y funcionamiento

ST STM32F413 Series Manual de usuario

ST STM32H7B3I-DK Manual de usuario

ST STM32F7508-DK Manual

ST STM32L4 Series Manual de usuario

ST Turbo+ mPSD DK3400 Manual de usuario

ST B-L462E-CELL1 Manual de usuario

ST STEVAL-BFA001V1B Manual de usuario

ST SPIRIT1 Manual de usuario

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ST SimpleMAC STM32W108 Series Manual de usuario

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