SONIX SN8P1829 Manual de usuario

SN8P1829

8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver

SONiX TECHNOLOGY CO., LTD Version1.0

SN8P1829

USER’S MANUAL

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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not

assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent

rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical

implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product

could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or

unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against

all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of

the part.

SN8P1829

8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver

SONiX TECHNOLOGY CO., LTD Version1.0

AMENDMENT HISTORY

Version Date Description

Pre V0.1 Nov. 2003 Preliminary V0.1 first issue

Pre V0.2 Dec. 2003 1. Change Regulator output = 3.8V

2. CPCKS/ PGIACKS clock setting for up-count

3. Add P13M in RAM table

4. PEDGE Register “01”, “10” setting modified. And add P0.1 description

5. Pin assignment : V1/V2/V3 re-arrange.

6. Application circuit : VLCD power came from AVDDR/VDD

Pre V0.3 Jul. 2003 1. Change the minimal different voltage between AVREFH and AVREFL form “1.2V”

to “2.0V”.

2. Modify ADC programming notice.

3. In EOC bit description: Change “reset ADENB bit” to “reset ADS” bit.

4. Modify some electrical characteristics: Varfh, Varfl,add Tast

V1.0 Feb. 2005 1. “B0MOV M, I”, M only supports 0x80~0x87

2. Add external low clock diagram, Figure7-5,7-6

3. Add note for PUSH/POP only one level.

4. External Reset circuit needs 100-ohm resistance. Figure 6-3, 6-4

SN8P1829

8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver

SONiX TECHNOLOGY CO., LTD Page3 Version1.0

Table of Contents

AMENDMENT HISTORY.............................................................................................................. 2

1PRODUCT OVERVIEW..................................................................................................... 7

FEATURES................................................................................................................................... 7

FEATURES TABLE ...................................................................................................................... 7

SYSTEM BLOCK DIAGRAM ........................................................................................................ 8

PIN ASSIGNMENT ....................................................................................................................... 9

PIN DESCRIPTIONS.................................................................................................................. 10

PIN CIRCUIT DIAGRAMS .......................................................................................................... 11

2CODE OPTION TABLE ................................................................................................... 12

3ADDRESS SPACES........................................................................................................ 13

PROGRAM MEMORY (ROM)..................................................................................................... 13

DATA MEMORY (RAM).............................................................................................................. 21

WORKING REGISTERS............................................................................................................. 23

PROGRAM FLAG....................................................................................................................... 26

ACCUMULATOR........................................................................................................................ 27

STACK OPERATIONS................................................................................................................28

PROGRAM COUNTER............................................................................................................... 31

4ADDRESSING MODE...................................................................................................... 34

OVERVIEW................................................................................................................................. 34

SN8P1829

8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver

SONiX TECHNOLOGY CO., LTD Page4 Version1.0

5SYSTEM REGISTER....................................................................................................... 36

OVERVIEW................................................................................................................................. 36

SYSTEM REGISTER ARRANGEMENT (BANK 0)..................................................................... 36

6POWER ON RESET ........................................................................................................ 39

OVERVIEW................................................................................................................................. 39

EXTERNAL RESET DESCRIPTION........................................................................................... 40

LOW VOLTAGE DETECTOR (LVD) DESCRIPTION ................................................................. 41

7OSCILLATORS................................................................................................................ 42

OVERVIEW................................................................................................................................. 42

SYSTEM MODE DESCRIPTION................................................................................................ 48

SYSTEM MODE CONTROL....................................................................................................... 49

WAKEUP TIME........................................................................................................................... 51

8TIMERS COUNTERS....................................................................................................... 53

WATCHDOG TIMER (WDT)....................................................................................................... 53

BASIC TIMER 0 (T0) .................................................................................................................. 55

TIMER COUNTER 0 (TC0)......................................................................................................... 56

TIMER COUNTER 1 (TC1)......................................................................................................... 67

PWM FUNCTION DESCRIPTION.............................................................................................. 76

9INTERRUPT..................................................................................................................... 80

OVERVIEW................................................................................................................................. 80

INTEN INTERRUPT ENABLE REGISTER ................................................................................. 81

SN8P1829

8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver

SONiX TECHNOLOGY CO., LTD Page5 Version1.0

INTRQ INTERRUPT REQUEST REGISTER.............................................................................. 81

INTERRUPT OPERATION DESCRIPTION................................................................................ 82

0SERIAL INPUT/OUTPUT TRANSCEIVER (SIO).................................................. 91

OVERVIEW................................................................................................................................. 91

SIOM MODE REGISTER............................................................................................................ 93

SIOB DATA BUFFER ................................................................................................................. 94

SIOR REGISTER DESCRIPTION .............................................................................................. 94

SIO MASTER OPERATING DESCRIPTION .............................................................................. 95

SIO SLAVE OPERATING DESCRIPTION.................................................................................. 99

SIO INTERRUPT OPERATION DESCRIPTION....................................................................... 104

1I/O PORT............................................................................................................. 105

OVERVIEW............................................................................................................................... 105

I/O PORT FUNCTION TABLE .................................................................................................. 106

PULL-UP RESISTOR (PNUR) REGISTER................................................................................ 106

I/O PORT MODE ...................................................................................................................... 107

THE PORT2 DISCRIPTION...................................................................................................... 108

I/O PORT DATA REGISTER .................................................................................................... 109

2LCD DRIVER....................................................................................................... 110

LCDM1 REGISTER ..................................................................................................................110

LCD TIMING............................................................................................................................. 112

LCD RAM LOCATION .............................................................................................................. 114

33-CHANNEL ADC WITH BATTERY MONITOR................................................. 115

OVERVIEW............................................................................................................................... 115

ADM REGISTER....................................................................................................................... 116

SN8P1829

8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver

SONiX TECHNOLOGY CO., LTD Page6 Version1.0

ADR REGISTERS..................................................................................................................... 116

ADB REGISTERS..................................................................................................................... 117

ADC CONVERTING TIME........................................................................................................ 118

4CHARGE-PUMP, PGIA AND OPA ..................................................................... 119

OVERVIEW............................................................................................................................... 119

BLOCK DIAGRAM.................................................................................................................... 119

VOLTAGE CHARGE-PUMP REGULATOR (CPR)................................................................... 120

PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER (PGIA) ...................................... 123

OPA – OPERATIONAL AMPLIFIER......................................................................................... 125

5APPLICATION CIRCUIT..................................................................................... 126

BLOOD PRESSURE METER APPLICATION CIRCUIT........................................................................... 126

6INSTRUCTION SET TABLE............................................................................... 127

7ELECTRICAL CHARACTERISTIC..................................................................... 128

ABSOLUTE MAXIMUM RATING.............................................................................................. 128

ELECTRICAL CHARACTERISTIC ........................................................................................... 128

8PACKAGE INFORMATION ................................................................................ 130

LQFP80..................................................................................................................................... 130

SN8P1829

8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver

SONiX TECHNOLOGY CO., LTD Page7 Version1.0

PRODUCT OVERVIEW

FEATURES

 Memory configuration

OTP ROM size: 8K * 16 bits

RAM size: 512 * 8 bits (bank 0/1/2)

8-levels stack buffer

LCD RAM size: 4*32 bits

Eight level stack buffer

 I/O pin configuration

Input only: P0, P2

Bi-directional: P1, P5

P2 shared with LCD segment

Wakeup: P0, P1

Pull-up resisters: P0, P1, P2, P5

External interrupt: P0

Port 2 shared with LCD segment

 Six interrupt sources

Four internal interrupts: T0, TC0, TC1, SIO

Two external interrupts: INT0, INT1

 Timer System

T0: 8-bit timer with green mode wakeup function

TC0/TC1: 8-bit timer counters with PWM or buzzer

Real Time Clock (RTC): 0.5/1/2/4 second

On chip watchdog timer

 Powerful instructions

Four clocks per instruction cycle

All instructions are one word length.

Most of instructions are 1 cycle only.

Maximum instruction cycle is “2”.

JMP instruction jumps to all ROM area.

All ROM area look-up table function (MOVC)

Support hardware multiplier (MUL).

 Single power supply: 2.4V ~5.5V

 Built-in Charge-Pump Regulator (CPR)

3.8V output / 5mA driven current

 PGIA: Programmable Gain Instrumentation

Amplifier with fully differential input

Gain 1: 16/32/64/128

Gain 2: 1.3 ~ 2.5

 Two-sets Operational Amplifier

 Three Channel 12-Bit ADC

 Built-in Battery Measurement

 LCD driver:

1/3 duty, 1/3 bias or 1/2 bias

4 common * 32 segment

 SIO function

 Dual clock system offers four operating modes

External high clock: RC type up to 10 MHz

External high clock: Crystal type up to 16 MHz

External Low clock: Crystal 32768Hz, RC mode

Normal mode: Both high and low clock active.

Slow mode: Low clock only.

Sleep mode: Both high and low clock stop.

Green mode: Periodical wakeup by T0 timer.

 Package:

LQFP80

FEATURES TABLE

Timer

CHIP ROM RAM Stack LCD T0 TC0 TC1 I/O ADC PWM

Buzzer SIO Wakeup

Pin no. Package

SN8P1829 8K*16 512*8 8 4*32 V V V 20 12-bit 2 1 6 LQFP80

Table 1-1 Selection table of SN8P1829

SN8P1829

8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver

SONiX TECHNOLOGY CO., LTD Page8 Version1.0

SYSTEM BLOCK DIAGRAM

Figure 1-1 Simplified system block diagram

IR OTP

ROM

H-OSC

TIMING GENERATOR

LCD

DRIVER

RAM

SYSTEM REGISTER

ALU

ACC

INTERRUPT CONTROL TIMER & COUNTER

PORT 0

PORT 1 PORT 2 PORT 5

SEG.

COM.

FLAGS

ADC AIN0~AIN2

L-OSC

SIO TX/RX

PWM0

PWM1

PWM0/Buzzer0

PWM1/Buzzer1

Charge

Pump AVDDCP

PGIA PGIAOUT

PGIAIN+/PGIAIN-

AVDDR

IR OTP

ROM

H-OSC

TIMING GENERATOR

LCD

DRIVER

RAM

SYSTEM REGISTER

ALU

ACC

INTERRUPT CONTROLINTERRUPT CONTROL TIMER & COUNTER

PORT 0

PORT 1 PORT 2 PORT 5

SEG.

COM.

FLAGS

ADC AIN0~AIN2

L-OSC

SIO TX/RXSIO TX/RX

PWM0PWM0

PWM1PWM1

PWM0/Buzzer0

PWM1/Buzzer1

Charge

Pump AVDDCP

PGIA PGIAOUT

PGIAIN+/PGIAIN-

AVDDR

SN8P1829

8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver

SONiX TECHNOLOGY CO., LTD Page9 Version1.0

PIN ASSIGNMENT

SN8P1829 (LQFP80)

C+

VDD

C-

VSS

VLCD

COM0

COM1

COM2

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

AVDDCP 1 O60SEG8

AVDDR 2 59 SEG9

AGND 3 58SEG10

AVREFL4 57SEG11

AIN25 56SEG12

AIN16 55SEG13

AIN07 54SEG14

AVREFH8 53SEG15

PGIABIAS9 52SEG16

PGIAIN+10 51SEG17

PGIAIN-11 50SEG18

PGIAOUT12 49SEG19

OP1IN+13 48SEG20

OP1IN-14 47SEG21

OP1OUT15 46SEG22

OP2IN+16 45SEG23

OP2IN-17 44SEG24/P2.0

OP2OUT18 43SEG25/P2.1

P0.0/INT019 42SEG26/P2.2

P0.1/INT120 41SEG27/P2.3

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P1.0

P1.1

P1.2

P1.3

P5.0/SCK

P5.1/SI

P5.2/SO

P5.3/PWM1/BZ1

P5.4/PWM0/BZ0

VDD

LXIN

LXOUT

XIN

XOUT

VPP/RST

GND

SEG31/P2.7

SEG30/P2.6

SEG29/P2.5

SEG28/P2.4

SN8P1829

8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Regulator + 128 dots LCD driver

SONiX TECHNOLOGY CO., LTD Page10 Version1.0

PIN DESCRIPTIONS

PIN NAME TYPE DESCRIPTION

VDD, VSS P Power supply input pins for digital circuit.

VLCD P Power supply of COM0 ~ COM3, SEG0 ~SEG31.

AVDDR P Regulator power output pin, Voltage=3.8V Maximum output current=5mA.

AGND P Regulator Analog Ground.

AVDDCP P Charge Pump Voltage output. ( connect a 2.2uF or higher capacitor to ground)

RST I System reset input pin. Schmitt trigger structure, active “low”, normal stay to “high”.

XIN, XOUT I, O External oscillator pins. RC mode from XIN.

LXIN, LXOUT I, O Low speed (32768 Hz) oscillator pins. RC mode from LXIN.

P0.0 / INT0 I Port 0.0 and shared with INT0 trigger pin. (Schmitt trigger) / Built-in pull-up resisters.

P0.1 / INT1 I Port 0.1 and shared with INT1 trigger pin. (Schmitt trigger) / Built-in pull-up resisters.

P1.0~P1.3 I/O Port 1.0~P1.3 bi-direction pins / Built-in pull-up resisters.

P5.0 / SCK I/O Port 5.0 bi-direction pin and SIO’s clock input/output / Built-in pull-up resisters.

P5.1 / SI I/O Port 5.1 bi-direction pin and SIO’s data input / Built-in pull-up resisters.

P5.2 / SO I/O Port 5.2 bi-direction pin and SIO’s data output / Built-in pull-up resisters.

P5.3 / BZ1 / PWM1 I/O Port 5.3 bi-direction pin, TC1 ÷ 2 signal output pin or PWM1 output pin.

Built-in pull-up resisters.

P5.4 / BZ0 / PWM0 I/O Port 5.4 bi-direction pin, TC0 ÷ 2 signal output pin or PWM0 output pin.

Built-in pull-up resisters.

P2.0 ~ P2.7 I Port 2.0 ~ Port 2.7 input pins with pull-up register and shared with LCD’s

SEG24~SEG31.

AIN0 ~ AIN3 I Analog signal input pins for ADC converter.

COM0 ~ COM3 O LCD driver common pins.

SEG0 ~ SEG31 O LCD driver segment pins.

AvrefH, AverfL I ADC’s reference high / low voltage input pins.

OP1IN+, OP1IN- I Operational Amplifier 1 Input Channels

OPOUT1 O Operational Amplifier 1 Output Channel

OP2IN+, OP2IN- I Operational Amplifier 2 Input Channels

OPOUT2 O Operational Amplifier 2 Output Channel

PGIAIN+, PGIAIN- I PGIA Input Channels

PGIAOUT O PGIA Output Channel

PGIABIAS I PGIA Bias Voltage input

C+ A Positive capacitor terminal for charge pump regulator

C- A Negative capacitor terminal for charge pump regulator

Table 1-2 SN8P1829 pin description

Tabla de contenidos

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